Test Circuits for Idsat Variation Characterization

The variation in process, device, and circuit is an increasingly difficult and critical concern for future integrated circuit design. Variation may have systematic components such as spatial, device-size, or pattern-density dependency, or it may have random stochastic components such as random doping fluctuations. Increasing effort is needed in the modeling and characterizing of device variations in order to design circuits robustly.

The left figure shows three common types of measuring schemes. Type A is the simplest approach, in which direct probing is used for full electrical characterization of a device. The Type A measuring scheme requires dedicated pads for probing; therefore, only a small number of probing terminals is available. The probing may also introduce extra stress on the device, which could change the device characteristic after measurement. Type B uses multiplexed circuitry to extract DC current-voltage (I-V) measurements. This pad-sharing scheme is more efficient, enabling characterization of more devices than in Type A. Type C is a dedicated circuit structure focused on extracting a specific device parameter, such as VT.

The right figure illustrates a systematic variation of saturation current across a single chip schematically. Several sources may contribute to observed ID(sat) variation, and each must be considered and understood. In deeply scaled technologies, variation in VT is believed to be mostly due to random dopant fluctuation and would not explain systematic dependencies or neighborhood pattern dependencies. Different STI pattern densities can be explored, to see if the resulting device variations show a clear systematic layout density offset. This component is of particular interest, as it is conjectured that stress or thermal annealing process effects may contribute to ID(sat) variation. While previous research efforts have explored the variation and layout dependency of VT and channel length individually, few have focused on the effect of stress or annealing related mobility variation. In this project, our goal is to design test-circuit approaches to isolate the device variation parameters (VT, L, and µ) and dependencies for future technologies, focusing especially on ID(sat) variation. A set of design rules and guidelines can then be formulated to minimize these variations.