" *********************************************************** " * * " * Copyright, (C) Honeywell Information Systems Inc., 1982 * " * * " *********************************************************** " setup, contains the bos toehold and command sys " Modified for IOM operation on 10/7/71 by N. I. Morris " Modified for use of the utility package on 11/5/71 by N. I. Morris " Modified for use on follow-on on 5/11/72 by D R Vinograd " Modified 8/79 by R.J.C. Kissel for expanded BOS. " Modified 4/30/80 by Mike Grady to modify clock pkg. " Modified 9/01/80 by Sherman D. Sprague for DPS8 support " Modified 10/5/81 by Sherman D. Sprague for change in AM store procedure. " Modified 1/08/82 by J. Bongiovanni to do spl on RTB " Modified 9/28/82 by J. Bongiovanni to grab an interrupt mask on RTB, 4MW SCU " Modified 1/22/85 by Paul Farley to add a time delay after status store to " allow for the DAU to do its interrupt service. " ****************************************************** " * * " * * " * Copyright (c) 1972 by Massachusetts Institute of * " * Technology and Honeywell Information Systems, Inc. * " * * " * * " ****************************************************** name setup include bosequ bool scr_mr.id.4mw,000002 use toec place toehold info after body of program include bos_toequ use mainc use standard location counter join /text/mainc,toec include fgbx " " ***************************************************************************** " " IMPORTANT NOTE ! ! ! IMPORTANT NOTE ! ! ! IMPORTANT NOTE ! ! ! " " The toehold M_U_S_T_ be 0 mod 64 locations long because " it must fit into an integral number of disk sectors. " " Also, bce (actually bootload_flagbox) knows the contents of the three " BOS entry sequences (locations 0 to 5 below). Any changes to these " locations must be reflected in bce. " " ***************************************************************************** " Here starts the toe hold prog. Loc 10000(8) follows. " The toehold saves BOS memory up to pgm using kprog in loaddm. Then setup " saves the rest of BOS memory which is pgm and util. inhibit on <+><+><+><+><+><+><+><+><+><+><+><+> scu origsetup+tscu save control unit ret origsetup+switchentry and go to common entry code scu origsetup+tscu entry to ignore switch setting ret origsetup+bosentry scu origsetup+tscu here from Multics, bump ILC ret origsetup+mulentry tra origsetup+lstart here after loading BOS switchentry: vfd 18/origsetup+savmach,6/2,12/scu.ir.bm+scu.ir.abs bosentry: vfd 18/origsetup+savmach,6/0,12/scu.ir.bm+scu.ir.abs mulentry: vfd 18/origsetup+savmach,6/1,12/scu.ir.bm+scu.ir.abs thist_off:oct 0 to turn off history registers cache_off:oct 3 to turn off cache swapsw: oct 0 non-zero when mailbox swapped savsw: oct 0 non-zero when machine image saved lkp_tra: tra origsetup+lkp_done tra on lockup fault org origflagbox-origsetup flagbox area follows flagbox: bss ,lnflagbox " savmach: scpr origsetup+tmode,06 save mode register lcpr origsetup+thist_off,04 turn off history registers lcpr origsetup+cache_off,02 and cache spl origsetup+treg un-wedge EIS box sreg origsetup+treg save machine sti origflagbox+fgbx.rtb save indicators lda origflagbox+fgbx.rtb indicators in AL arl 12 entry code in AL ana =o77,dl mask the entry code stca origflagbox+fgbx.rtb,07 and save it tnz 2,ic if zero, entered from BOS stz origsetup+savsw force saving of machine image cmpa 1,dl if one, entered from Multics tnz 4,ic must bump ILC by 1 lda =1,du adla origsetup+tscu+scu.ilc_word sta origsetup+tscu+scu.ilc_word szn origsetup+swapsw already in toehold? tnz origsetup+noswap1 rscr 4*8 read the clock staq origsetup+tclock and save it rscr 3*8 read the interrupt cells staq origsetup+savint save pending interrupts eax7 7*64 RSCR index in X7 eax6 7*2 controller mask index in X6 svmcm: rscr 2*8,7 read a mask staq origsetup+tmcm,6 and save it fld 0,dl clear AQ sscr 2*8,7 turn off mask bits eax7 -64,7 decrement RSCR index eax6 -2,6 and mask index tpl origsetup+svmcm loop for all masks fld 0,dl staq origsetup+saved_cfg ldx0 SC_MR*8,du Get mode register rscr origsetup+low_port_x0,* On bootload SCU canq scr_mr.id.4mw,du 4MW SCU? tze origsetup+skip_mask_set No ldx0 SC_CFG*8,du Read/diddle config register rscr origsetup+low_port_x0,* On bootload SCU staq origsetup+saved_cfg Save for later anaq origsetup+cfg_mask_mask Strip out Mask A/B staq origsetup+new_cfg lrl scr_cfg2.port_no_shift+36 anq scr_cfg2.port_no_mask,dl Our port number to QL lda =o400000,du Mask A to port 0 arl 0,ql Mask A to our port ldq =o001000,du Mask B off oraq origsetup+new_cfg Rest of CFG register sscr origsetup+low_port_x0,* Set it skip_mask_set: ldaq fvloc+lockup*2 save lockup fault loc staq origsetup+locsav noswap1: ldaq origsetup+scurcu replace with scurcu staq fvloc+lockup*2 " szn origsetup+swapsw already done? tnz origsetup+noswap2 yup tsx2 origsetup+swap swap mailbox with mine noswap2: stc2 origsetup+swapsw done it szn origsetup+savsw should we save memory image? tnz origsetup+nosav if not, don't write out memory eax7 0 write out memory tsx2 origsetup+ioprog nosav: eax7 1 and read in setup tsx2 origsetup+ioprog tsx2 origsetup+swap swap back toehold mailbox stz origsetup+swapsw reset for swap szn origsetup+savsw machine image to be saved? tze origsetup+setup if so, go save it tra origsetup+lstart otherwise, just enter main control " " Come here to restart machine image. tcont: eax7 2 read in core tsx2 origsetup+ioprog tsx2 origsetup+swap restore mailbox stz origsetup+savsw indicate machine image restored ldaq origsetup+saved_cfg Bootload SCU CFG register tze origsetup+skip_mask_restore Not to do ldx0 SC_CFG*8,du sscr origsetup+low_port_x0,* Restore it skip_mask_restore: eax7 7*64 SSCR index in X7 eax6 7*2 controller mask index in X6 rsmcm: ldaq origsetup+tmcm,6 get mask sscr 2*8,7 set in controller eax7 -64,7 decrement SSCR index eax6 -2,6 and mask index tpl origsetup+rsmcm loop for all masks lda origsetup+lkp_tra set up to wait for lockup fault sta fvloc+lockup*2 lda 1,du one in AU sba 1,dl wait for lockup to go off tpnz -1,ic continue if no lockup occurs lkp_done: " YOU NOW HAVE 32 MS TO TURN OFF INHIBIT. GO! ldaq origsetup+locsav restore lockup fault staq fvloc+lockup*2 ldaq origsetup+savint restore interrupts sscr 3*8 .. lreg origsetup+treg restore regs lcpr origsetup+tmode,04 restore mode register lcpr origsetup+tmode+1,02 restore cache mode register rcu origsetup+tscu and continue prog " swap: eax7 swaplen-1 interchange top half of toeho swapl: lda origsetup+mbxloc,*7 with mailbox ldq origsetup+dprog,7 stq origsetup+mbxloc,*7 sta origsetup+dprog,7 eax7 -1,7 tpl origsetup+swapl tra 0,2 ioprog: lda origsetup+devid arl 9-2 (was in 3-8) 4*channel = mbx index eax6 0,au ldq scwr+imbx stq imbx+2,6 ldq lpwr+imbx,7 stq imbx+0,6 stz statq+imbx clear status cioc cow+imbx start io lda statq+imbx examine status tze -1,ic wait for it to come in " " Now pause for status interrupt to complete (~ 350 - 550 usec). " ldq =o377,dl sbq 1,dl nop tnz -2,ic cana origsetup+statmsk check for error tnz origsetup+ioprog if error, try again tra 0,2 statmsk: oct 370000770000 " even savint: bss ,2 interrupt bits for SMIC even tmode: bss ,2 mode registers even tclock: bss ,2 time of toehold entry even scurcu: scu origsetup+lkp_scu ignore lockup faults rcu origsetup+lkp_scu even locsav: bss ,2 lockup fault vector saved here even tmcm: bss ,16 controller masks saved here eight lkp_scu: bss ,8 SCU area for lockup faults eight treg: bss ,8 registers saved here temporarily eight tscu: bss ,8 SCU data saved here temporarily even saved_cfg: bss ,2 Saved CFG for bootload SCU new_cfg: bss ,2 Used to build our CFG even cfg_mask_mask: oct 000777777777 Mask out Mask A and Mask B oct 000777777777 low_port_x0: arg 0,x0 Used to access bootload SCU sscr/rscr org mbxloc zero 0 mbxloc org devid zero 0 devid (3/iom,6/chn,9/devno,18/type) org ttychan zero 0 ttychan bss dprog,swaplen space for IOM program mod 64 This guarantees the toehold is an " integral number of sectors long. " " This is BOS main control. " loc 4600(8) follows org cowsav begin non-toehold part of setup zero 0,0 cowsave org mbbasesav arg 0 mbbasesave org mxbasesav arg 0 mxbasesave org dirbase vfd 24/0,12/seg6length/64 dirbase inhibit on <+><+><+><+><+><+><+><+><+><+><+><+> setup: tsx2 origsetup+savemc stc2 origsetup+savsw indicate machine image has been saved tsx2 origsetup+iappend load pointer regs, dbr, init IOM, inhibit off <-><-><-><-><-><-><-><-><-><-><-><-> lda dirbase write out machine cond ana =o777777770000 ora dir/64,dl tsx2 wtsec nop com|0 dis * lda dirbase read in dir ada =v24/dir/64 sba dir/64,dl tsx2 rdsec nop com|dir dis * tsx2 setone stz com|fdump_state initialize for if command lda com|corearea get loc'n of saved memory ana =o777777770000 mask out the sector count ada =v24/origsetup/64,12/toelen/64 add offset of toehold tsx2 wtsec write out the toehold nop mem|origsetup since toehold skipped itself dis * lda com|corearea save remainder of low core ada =v24/toesaved/64 increment the sector number by what the " toehold saved. sba toesaved/64,dl decrement the sector count by what the " toehold saved. tsx2 wtsec nop mem|toesaved dis * tsx2 getportinfo initialize port array ldx2 com|low_order_port setup for RSCR/SSCR stx2 mem|origsetup+low_port_x0 lda =v24/fvloc/64 restore lockup fault loc ada com|corearea on disk stca fltloc,74 lda fltloc tsx2 rdsec read sector nop tmp|0 dis * ldaq locsav get old pair staq tmp|lockup*2 lda fltloc tsx2 wtsec nop tmp|0 dis * tsx2 type get fresh line on console zero =h??????,1 lda flagbox+fgbx.rtb see if BOS entered manually ana fgbx.bos_entry_mask,dl .. cmpa 1,dl .. tze tstmsg if not, test for panic message tsx2 erpt print message acc "BOS entered manually." tra cready .. tstmsg: lda flagbox+fgbx.rtb look at BOS return flags cana fgbx.mess,du message for to print? tze cready if not, give ready message era fgbx.mess,du turn off bit sta flagbox+fgbx.rtb .. cana fgbx.alert,du turn on audible alarm? tze *+2 if not, skip call tsx2 ttyalert sound the alarm tsx2 erpt print message acc "^A" arg fgmsdesc tra cready fgmsdesc: desc9a flagbox+fgbx.message,64 " inhibit on <+><+><+><+><+><+><+><+><+><+><+><+> lstart: tsx2 origsetup+iappend here at startup and for troub inhibit off <-><-><-><-><-><-><-><-><-><-><-><-> lda dirbase readin mach cond tsx2 rdsec nop com|0 dis * lda com|inputsw look at input mode arl 30 .. cmpa 2,dl in runcom? tmi execint if not, skip following lda com|inputsw pop to previous source als 6 .. sta com|inputsw .. stz com|macroloc clear runcom flags stz com|skipsw .. execint: tsx2 setone set bound of seg 1 tsx2 getportinfo port array info ldx2 com|low_order_port setup for RSCR/SSCR stx2 mem|origsetup+low_port_x0 bready: szn com|readysw shell we print a ready ? tnz cycle not this time cready: tsx2 rd_clock Read the clock lda rdclock.year Get year sbla 1900,dl sta year_temp tsx2 erpt print bos at time acc 'bos ^a^a at ^d:^d:^d ^a ^a ^d/^d/^d' arg bos_version arg bos_version+1 arg rdclock.hr arg rdclock.min arg rdclock.sec arg rdclock.zone_name arg rdclock.day_name arg rdclock.month arg rdclock.day_of_month arg year_temp tra cycle comerr: tsx2 erpt error, print ? acc '^g' arg =h!!? " cycle: lda =h bos load return prompt sta com|curtcmd store it !! tsx2 nextline read next input line fndc: eax7 arglen-1 relocate all descriptors reldesc: lda mem*32768+origsetup,du adla earg,7 insert segment tag, also sta earg,7 .. eax7 -1,7 loop through all descriptors tpl reldesc .. lda arg eax1 0 initialize index rpt nbc/2,2,tze is it built-in command? cmpa bcl,1 ttf -1,1* if so, go to it tsx2 search search BOS command directory tra comerr eax0 0,7 X0 -> directory entry cana =o4000,dl is it a macro file tnz isrun ana =o777,dl mask the length sta bound and save for bound calc. lda arg load command for prompt sta com|curtcmd lda lnpgm*4,dl clear command area mlr (),(pr,rl),fill(0) clear the command area desc9a *,0 desc9a tmp|0,al lda com|utilarea get length of utility package ana =o777,dl cmpa bound get max. bound tpl *+2 lda bound als 2 0 mod 64 to 0 mod 16 sbla 1,dl minus 1 for SDW bound als 21 shift to SDW bound position era ds|tmp*2+1 and insert into bound field ana sdw.bound,du ersa ds|tmp*2+1 cams 0 lda com|utilarea load the utility package tsx2 rdsec nop tmp|0 into segment 1 dis * lda com|1,0 now overlay with command ana =o777777770777 only address and length tsx2 rdsec nop tmp|0 into seg 1 dis * tra mem|origsetup+*+1 go to seg 7 ldaq ds|tmp*2 and set 3 to tmp*2 eraq ds|pgm*2 and vice versa ersa ds|tmp*2 ersq ds|tmp*2+1 ersa ds|pgm*2 ersq ds|pgm*2+1 cams 0 tsx2 pgm|0 tsx2 to loaded command inhibit on zero origsetup+arg,origsetup+line sta origsetup+arg save possible command tsx2 origsetup+iappend reinit setup inhibit off tsx2 setone tsx2 getportinfo ldx2 com|low_order_port setup for RSCR/SSCR stx2 mem|origsetup+low_port_x0 lda dirbase write out machine cond tsx2 wtsec nop com|0 dis * lda arg if chaining, don't type ready tze scanc if zero, rescan command line cmpa =-1 tnz fndc tra bready isrun: mrl (),() move the whole line down desc6a line,73 desc6a line+1(5),73 mlr (),() now insert "RUNCOM RUN " desc6a runcom_run,11 desc6a line,11 scanc: tsx2 nxtlinea rescan the command line tra fndc and process command " bcl: bci 'contin' zero contin bci ' go' zero contin bci ' list' zero list bci 'rename' zero rename bci 'delete' zero delete bci ' flag' zero flag equ nbc,*-bcl " list: eax0 0 now print each command stz line listl: lda com|cmdlst,0 tze listx sta line+1 lda com|cmdlst+1,0 print disk locatin arl 12 right-justify sector addr. sta line tsx2 erpt print acc '^o ^g' arg line arg line+1 listx: eax0 2,0 cmpx0 dirlen-(cmdlst-dir),du tmi listl tra cycle rename: lda arg+2 Get new name. tsx2 search Is it there already. tra *+2 If not, OK. tra comerr Otherwise, error. lda arg+1 Get original name. tsx2 search Look up in directory. tra comerr .. lda arg+2 Get new name. sta com|0,7 Replace name in directory. tra cycle delete: lda arg+1 search for file tsx2 search tra comerr stz com|0,7 zero out directory entry stz com|1,7 .. tra cycle and that's it flag: ldq =o400000,du get bit for flag lda darg+1 get bit position qrl -1,al move to correct position lda arg+2 get ON or OFF cmpa =h on tze flagon go turn it ON cmpa =h off tnz cycle erq =-1 complement bits ansq flagbox+fgbx.flags_word turn off desired bit tra cycle flagon: orsq flagbox+fgbx.flags_word turn on desired bit tra cycle " contin: lda dirbase write out common tsx2 wtsec .. nop com|0 dis * lda =v24/fvloc/64 place scu-rcu in lockup fault adla com|corearea stca fltloc,74 lda fltloc tsx2 rdsec nop tmp|0 dis * ldaq tmp|lockup*2 staq locsav ldaq scurcu on disk staq tmp|lockup*2 lda fltloc tsx2 wtsec nop tmp|0 dis * lda com|corearea restore core ada =v24/toesaved/64 except what we are running in sba toesaved/64,dl tsx2 rdsec nop mem|toesaved dis * inhibit on <+><+><+><+><+><+><+><+><+><+><+><+> ldaq scurcu before inhibit, disable locku staq mem|fvloc+lockup*2 lda abstra go to abs mode sta mem|fvloc+drl*2 drl abstra: tra origsetup+*+1 tsx2 origsetup+restormc lda scu.cu.rfi,dl turn on the refetch bit sta origsetup+tscu+scu.cu_stat_word in SCU data scpr origcom+faultreg,01 clear the fault register eax2 origsetup+tcont to toehold tra origsetup+swap simulating a tsx2 inhibit off <-><-><-><-><-><-><-><-><-><-><-><-> " inhibit on <+><+><+><+><+><+><+><+><+><+><+><+> iappend: stx2 origsetup+initret1 here to init setup mlr (),(),fill(0) copy the descriptor segment desc9a origsetup+dseg,8*2*4 desc9a origds,lnds*4 lpri origsetup+bos_pr load pointer regs ldbr origsetup+bos_dbr tra pgm|*+1 enter appending mode tsx2 initint ints arg execint stz intrpts1 start collecting interrupts lda mbbasesav restore mailbox base sta com|iom_mbbase ldq cowsav set up COW in IOM mailbox stq mem|iom_cow,au restore COW lda mxbasesav restore interrupt base sta com|iom_mxbase tsx2 init_io initialize iom lda ttychan set tty channel # sta com|ttychanno tsx2 ttyinit arg bready lda devid sta com|bos_dvt initret1: eax2 * restore X2 tra -origsetup,2 call was made in absolute mode setone: lda lnpgm/16-1,du restore bound field for segment 1 als 3 shift to bound position era ds|tmp*2+1 ana sdw.bound,du ersa ds|tmp*2+1 cams 0 tra 0,2 " " This routine operates in absolute mode and saves " the Multics machine state for debugging or later " restoration. savemc: inhibit on <+><+><+><+><+><+><+><+><+><+><+><+> spri origcom+prs save pointer registers spl origcom+ptrlen save pointers and lengths stx2 origsetup+mcsavret save for return mlr (),(),fill(0) clear out am store area desc9a 0,0 desc9a origcom+amptwregs,320*4 tsx2 origsetup+check_cpu_type eax4 0,al sam1: eax7 4 eax6 3 set up for a dps8 cmpx4 1,du were we right? tze origsetup+sam2 yes ,now thats a first! eax6 0 so we were wrong its a l68 sam2: lda origsetup+sam5-1,7 load raw instruction word eax5 0,6 set up counter sam3: eaq 0,5 but counter in q qls 4 multiply times 4 cmpx7 2,du is this the sdw regs ? tnz origsetup+sam4 qls 1 it was so make it times 32 sam4: sta origsetup+inst store raw instruction to be XECed asq origsetup+inst add in quadrant offset xec origsetup+inst lets execute it eax5 -1,5 decrement counter tpl origsetup+sam3 lets do it again eax7 -1,7 get another instruction tnz origsetup+sam2 do it again " clear the history reg store area and " save the history registers mlr (),(),fill(0) clear out du storage desc9a 0,0 desc9a origcom+ouhist,128*4*4 ldq 2,du address field step eax6 nscpr-1 # of instructions scpr2: eax7 16 16 instructions to store a history register cmpx4 1,du check cpu type tnz origsetup+l68 skip next inst. if l68 eax7 64 set up for dps8 l68: lda origsetup+scpr,6 pick up inst sta origsetup+inst scpr1: xec origsetup+inst execute it asq origsetup+inst incrment address field eax7 -1,7 decrement loop tnz origsetup+scpr1 not done cmpx4 1,du check cpu type tnz origsetup+skipl68 continue with l68 code cmpx6 3,du is this a du hist coming up tnz origsetup+skipl68 eax6 -1,6 skipl68: eax6 -1,6 tpl origsetup+scpr2 get next inst mlr (),() save registers desc9a origsetup+treg,8*4 desc9a origcom+regs,8*4 mlr (),() save SCU desc9a origsetup+tscu,8*4 desc9a origcom+scu,8*4 sdbr origcom+dbr save dsbr sbar origcom+bar and bar ldaq origsetup+tmode save mode register staq origcom+modereg scpr origcom+faultreg,01 store fault register ldaq origsetup+tclock save clock reading staq origcom+mctime .. ldaq origsetup+savint get interrupts arl 36-16 in one word lls 36-16 .. sta origcom+intrpts save mlr (),() save controller masks desc9a origsetup+tmcm,16*4 desc9a origcom+mcm,16*4 ldaq origsetup+saved_cfg save CFG register from bootload SCU staq origcom+lowport_cfg mcsavret: eax2 * restore return tra 0,2 inst: bss ,1 sam5: ssdp origcom+amsdwptr ssdr origcom+amsdwregs sptp origcom+amptwptr sptr origcom+amptwregs scpr: scpr origcom+ouhist,40 scpr origcom+cuhist,20 scpr origcom+eishist,10 scpr origcom+aphist,00 equ nscpr,*-scpr inhibit off <-><-><-><-><-><-><-><-><-><-><-><-> " " This routine operates in absolute mode and " restores the Multics machine state . restormc: inhibit on <+><+><+><+><+><+><+><+><+><+><+><+> cams 0 clear assoc. memories camp 0 lcpr 0,03 clear history registers lpri origcom+prs ldbr origcom+dbr lbar origcom+bar ldaq origcom+modereg orq =o3,dl give maximum time for lockup fault staq origsetup+tmode lda origcom+intrpts get pending interrupts lrl 36-16 in word-pair als 36-16 .. staq origsetup+savint place for loading later mlr (),() restore controller masks desc9a origcom+mcm,16*4 desc9a origsetup+tmcm,16*4 ldaq origcom+lowport_cfg restore CFG register from bootload SCU staq origsetup+saved_cfg mlr (),() restore registers desc9a origcom+regs,8*4 desc9a origsetup+treg,8*4 mlr (),() restore SCU desc9a origcom+scu,8*4 desc9a origsetup+tscu,8*4 lpl origcom+ptrlen load pointers and lengths tra 0,2 inhibit off <-><-><-><-><-><-><-><-><-><-><-><-> " even opnmsk: oct 777774000000 turn on all int oct 777774000000 runcom_run: bci "runcom run " even temp: oct 0,0 even segdef bos_version bos_version: bss ,2 year_temp:bss ,1 fltloc: vfd 24/0,12/1 bound: dec 0 bss line,14 temp where command is read bss arg,arglen buffer for scanned arguments dec -1 bss darg,arglen buffer for decimal converted args dec -1 bss earg,arglen buffer for EIS args dec -1 eight scuinfo: bss ,8 set by intflt after fault " include bos_sdw include mc include getportinfo include rdclock include scan include nextline include search include rwdev include config_cards include fs_dev_types include rwsec " rdbulk: " Dummy routine, since rwdev should never access wtbulk: " these entry points while setup is running. dis * include rwdisk include error include readc include readt include octwd include conv include strip include getcon include bos_iom_manager include intflt include check_cpu_type include bos_common include scr end " " " ----------------------------------------------------------- " " " " Historical Background " " This edition of the Multics software materials and documentation is provided and donated " to Massachusetts Institute of Technology by Group Bull including Bull HN Information Systems Inc. " as a contribution to computer science knowledge. " This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, " Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell Bull Inc., Groupe Bull " and Bull HN Information Systems Inc. to the development of this operating system. " Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), " renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership " of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for " managing computer hardware properly and for executing programs. Many subsequent operating systems " incorporated Multics principles. " Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., " as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . " " ----------------------------------------------------------- " " Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without " fee is hereby granted,provided that the below copyright notice and historical background appear in all copies " and that both the copyright notice and historical background and this permission notice appear in supporting " documentation, and that the names of MIT, HIS, Bull or Bull HN not be used in advertising or publicity pertaining " to distribution of the programs without specific prior written permission. " Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. " Copyright 2006 by Bull HN Information Systems Inc. " Copyright 2006 by Bull SAS " All Rights Reserved " "