Path: bloom-picayune.mit.edu!snorkelwacker.mit.edu!americast.com!americast.com\!americast-post Newsgroups: americast.mech From: americast-post@AmeriCast.Com Organization: American Cybercasting Approved: americast-post@AmeriCast.com Subject: CIME: RISC Workstations Tackle Tough Engineering Tasks Date: Fri, 13 Nov 92 21:37:04 EST Message-ID: CIME: RISC Workstations Tackle Tough Engineering Tasks Selecting the Proper workstation can be a daunting task given the number of architectures, models, and engineering applications available. The burden of finding the right tools for the job falls in the shoulders of those who know the job best: engineers. By: Michael Puttre Associate Editor The advent of reduced instruction set chip (Risc) architectures has brought about a general increase in workstation performance. Risc workstations process greater amounts of information at rates faster than their more complex predecessors by executing fewer higher-level instructions per processing cycle. There is more than one approach to developing a Risc architecture, however, and engineers have a number of Risc platforms from which to choose. Because these Risc machines are different enough to affect the way they handle various engineering tasks, each task requires the appropriate workstation. Computer-aided design and manufacturing programs, for example, frequently pass data between disk and RAM, a process that relies on integer performance; visualization and analysis applications rely on floating-point performance and graphics processing; and concurrent-engineering functions require sufficient network resources. That is why before making workstation purchases, it is important to define the workload and come up with a hierarchy of components that matter, said Larry Gray, research and development section manager for performance evaluation at Hewlett-Packard Workstation Systems (Fort Collins, Colo.). Gray said there are four major points that should be considered when evaluating workstations. These are: Floating-point processor performance can be measured in Specmarks published by Spec International. Visualization capabilities can be measured by Graphics Performance Committee (GPC) numbers published by the GPC. Networking is a matter of selecting the appropriate network system, generally either token ring or ethernet, and having sufficient bandwidth for data communication. Determine how much reading from disk will be performed and obtain enough disk I/O to handle it. Large parts files, whether they are vector or raster, will require a great deal of I/O. Generally, this is the slowest part of the system. Performance Afloat Floating-point performance is one of the most visible measures of workstation performance. The Specmark benchmark measures the ability of a workstation to handle floating-point calculations. Most of the Risc architectures currently available, including IBM's Power for the RS/6000, Hewlett-Packard's PA-Risc for the HP Apollo Series 700, and the Clipper from Intergraph Corp. (Huntsville, Ala.) have emphasized floating-point processing. The Clipper workstations, for example, make floating-point calculations about twice as fast as they make integer calculations. By enhancing floating-point performance, Intergraph, IBM, and HP have positioned their workstations as solutions for highly technical computing problems. The Clipper's floating-point performance helps it with such applications as finite element analysis (FEA), which is a classic example of the importance of floating-point processing, said Nathan Brookwood, director of marketing for Intergraph's Advanced Processor division (Palo Alto, Calif.). The key to application performance in this area is the ability to do floating-point calculations really fast. Floating-point capabilities affect workstation performance in areas other than FEA number crunching. Visualization, simulation, and other applications with considerable graphics requirements make extensive use of a floating-point CPU. Operations such as hidden surfaces and shading of 3-D graphics require 3-by-3 matrix multiplications, which depend on floating-point processing. Nevertheless, no single workstation feature is responsible for handling all aspects of a given software program. Even such intensive floating-point functions as matrix multiplication have integer requirements such as array updating, said Kevin Gorey, product manager in the Advanced Graphics division of Silicon Graphics Inc. (Mountain View, Calif.). Thus, insufficient integer performance could cause an application to grind to a halt. In addition to handling fixed-point arithmetic, the integer processor performs data address computations for both itself and the floating-point processor. Precisely when data are to be moved between the processors and the data cache is determined by the integer unit. Thus integer performance can have a direct bearing on floating-point performance. For this reason, some Risc workstation vendors, notably Sun and Silicon Graphics, have chosen to pursue a strategy of balancing integer and floating-point performance. While balanced processing engines may not match the floating-point-intensive machines in terms of performance on certain benchmarks, they often offer a wider selection of applications. Benchmarks do not tell you what you are going to do, said Silicon Graphic's Gorey. Vector processors, for example, which emphasize floating-point performance, have very narrow high-peak performance figures. Codes optimized for that sweet spot, such as published benchmarks, will tend to run very fast on floating-point-intensive machines. Other codes that fall outside the peak may not deliver as impressive a performance. A balanced computing engine, on the other hand, may not peak so high, but often has a broader range of applications that run acceptably well because it is easier for software developers to write code for them. This explains why Sun's Sparcstations are used by many application developers, even for developing codes intended for other machines. With an installed base of 700,000 processors, the Sparc is the most popular Risc architecture. At the chip level, the Sparc has balanced integer and floating-point processing. Sun has sought to make its machines appropriate for many applications at the expense of superior floating-point performance. The wide variety of software applications available for Sparcstations has generated a large following of users. Analytical engineers at Pratt & Whitney's Government Engine and Space Propulsion division (West Palm Beach, Fla.) are migrating from a mainframe system to Sparcstation 2 desktop machines largely because of the variety of software they have to run, including Unigraphics, Pro/ Engineer, Marc Analysis, and Icad. Four hundred Sparcstation 2 workstations, the mainframe, and a Cray supercomputer are being networked throughout Pratt & Whitney via ethernet. Single-function machines are not as cost-effective, said Derek Meyer, director of Sparc marketing at Sun Microsystems. Ticking Away A Risc architecture is defined by a set of instructions rather than by physical characteristics of the chip on which they are imprinted. It is possible to make changes in the implementation of the instruction set without making any physical changes to the chip. Common implementation strategies for increasing performance include pushing up the clock rate, measured in megahertz, and increasing the number of calculations per clock tick in the pipeline. Many improvements within a workstation line and even between one generation of Risc chips and the next are due to increases in the processing clock rate. A machine running at 50 MHz will be faster than an identically equipped machine running at 25 MHz. Although the Mips Risc chip used by Silicon Graphics has gone through three incarnations, only the latest R4000 processor actually involved changes in the instruction set. The R3000 chip was basically the original R2000 chip running at a higher clock speed. Clock rate is important for achieving high performance, said Intergraph's Brookwood. High clock rates allow the processor to achieve the throughput required for technical applications. How long it takes a workstation to process a given problem can be measured by the number of instructions it can execute per cycle. Sun's Meyer said that while Sparcstations have moderate clock speeds, they get more done in a given clock tick because the balanced processing architecture means that the floating-point unit does not have to wait for the integer unit to catch up. Look at the overall performance rather than clock speed, Meyer said. Those companies that foster floating-point-intensive architectures have evolved strategies to deal with uneven processor performance. The IBM Power and Intergraph Clipper architectures, for example, have pipelines that are four to five registers deep. During any one clock tick, there are four or five problems at different stages of completion. Even though one particular task might take five clock ticks, other tasks are being completed every tick because pipelining allows multiple problems to be processed simultaneously. One aspect of workstation performance related to clock speed is whether the various subsystems communicate with each other through asynchronous or synchronous connections. Synchronous connections require that the CPU and the bus have the same clock speed. If the CPU is upgraded, all of the other workstation subsystems have to be upgraded. This is less problematic for high-end systems, where upgrades are likely to encompass all subsystems. Asynchronous connections allow subsystems to be upgraded one item at a time, as needed, which might be more appropriate for economy-minded users handling more moderate tasks. Increased Processor Speed Enhances Graphics One strategy being adopted by vendors for improving performance is the concentration of as many workstation compute functions on as few chips as possible. Improvements to the compute technology, such as performing graphics processing on the main CPU rather than relying on a separate graphics processor, increase graphics performance because the step of interchip communications is eliminated. Also, increases in processor speed automatically result in increased graphics performance. The Mips R4000 chip, used by the low-end Iris Indigo workstation, concentrates major functions on the computing side, including graphics processing, on one chip. The chip has a clock speed of 100 MHz on board and 50 MHz off board. The on-board speed is available for graphics processing. By sometime next year, all Silicon Graphics platforms will be equipped with the R4000 chip. Intergraph also believes that the more functions that can be integrated onto the chip, the better. The Clipper currently has 1.5 million transistors per chip, which is enough power to handle graphics processing. As more transistors are added, more functions can be taken over. The problem is more a matter of figuring out what you want to put on the chip rather than lack of space, said Intergraph's Brookwood. Workstations are developing very simple mother boards. Soon, all of the computation will be performed on a main chip with a lot of memory chips added. Putting more functions on the chip also reduces the need to send signals from one chip to another. Interchip communications result in delays and signal-reflection problems. There is also a savings in manufacturing costs. A single larger chip with a reasonable yield is cheaper than many smaller chips. The only caveat to this is that the greater the chip area, the greater the possibility for defects in the manufacturing process. Applications are the most important aspect of computer-aided engineering. While most software is designed to run on more than one platform, there can be significant differences in performance from one workstation to the next. Many of these differences are related to how the code is compiled and to differences in hardware. Engineers should have the ability to retain installed software as well as take advantage of state-of-the-art semiconductors, said Sun's Meyer. It is the job of compiler developers to enhance compiler technology to take advantage of new chip features and support existing software. Product compatibility over the life of an architecture allows users to upgrade software at their leisure and not have to recompile for every workstation model just to run it. At the beginning of this year, Lockheed Corp. (Calabasas, Calif.) purchased 76 Silicon Graphics machines; 50 of them were Indigo Elan workstations for parts-level CAD design. Another 18 were Powervision graphics workstations for integrated design of multipart subsystems. The remaining 8 were processor network resources for running finite element analysis and to function as central file servers. The systems all have binary compatibility with one another so that file transfer is not a problem. At the same time, compiler technology must keep pace with the latest architectural improvements in order for applications to be recompiled and to take advantage of performance enhancements. Software companies have to maintain close relationships with the hardware vendors that run their applications. It is equally important to communicate with the systems software people who develop compilers. The object code of the application must be compiled for the latest version of a particular hardware platform or the improvements will not be reflected. Finally, the more a workstation is called upon to do, the greater the allowance must be for data communication. Frequent calls between disk and main memory will require enough cache memory and I/O to handle the load. Certain applications, such as CAD/CAM systems for relatively small parts files, do not put too much of a burden on I/O. Others, such as CAD/CAM for large subsystem files and solids modelers requiring rapid screen regeneration, require frequent disk calls. Check to see if the application makes numerous disk calls and needs high-performance I/O, said Silicon Graphic's Gorey, adding that upgrading the CPU without proper attention to I/O requirements can throttle processor performance advantages. If the I/O is insufficient, the CPU will just wait at faster and faster rates. Copyright 1992, Mechanical Engineering. For more information, send-email to American Cybercasting Corporation (usa@AmeriCast.COM)