Path: bloom-picayune.mit.edu!snorkelwacker.mit.edu!americast.com!americast.com\!americast-post Newsgroups: americast.ieee From: americast-post@AmeriCast.Com Organization: American Cybercasting Approved: americast-post@AmeriCast.com Subject: SPECIAL REPORT/MEMORY - Fast interfaces for DRAMs Date: Wed, 4 Nov 92 10:20:19 EST Message-ID: <1052.art.1992Nov4.102019@AmeriCast.com> SPECIAL REPORT/MEMORY - Fast interfaces for DRAMs Richard C. Foss, Mosaid Technologies, Inc. Betty Prince, Texas Instruments Inc. The fundamental circuitry between a device's interior logic and its external pins must evolve to meet new speed and power needs If dynamic RAMs and processors are to trade data at close to top speed, the interface between them must be re-engineered. At a minimum, it must support speeds in the 100-500-MHz range, the low end for new dynamic RAM architectures and the high end for t he speed projected for processors by the decade's end. None of the types of interfaces now popular can do this while conserving power and cost to the desired degree. Yet it is hardly prudent to move on to a new form of interfaces without learning from and allowing for what has gone before. TODAY'S LIMITS. Current nominal 5-V interfaces include standard CMOS and TTL. CMOS is usually specified as having a minimum (worst-case) 2-V swing, but (unless dc-loaded for some special application) usually goes rail to rail at 5 V. On the other hand, TTL is typically specified as having a 2-V swing because it does not go rail to rail; the dc load of its fanout and its emitter-follower pull-ups prevent this from occurring. Even so, TTL typically achieves much more than a 2-V swing and, with a 5.5-V maximum Vcc (worst case), it may well operate at almost twice the 2-V level. Low-voltage CMOS and TTL are emerging; the nominal 3.3-V LVCMOS goes rail to rail to about a 3.6-V (worst-case) output swing, while LVTTL retains the 2-V output swing of its more power-hungry predecessor [See Table, p. 56]. Regardless of whether it is pumping lumped-capacitance loads or driving terminated lines, a rail-to-rail swing consumes too much power. The tracks on the typical printed-circuit board look like 100-(ohms) lines, but lumped-capacitance point loads i n a bus environment can complicate things, lowering this figure to an effective characteristic impedance (Zo) well below 50 (ohms). [Fig. 1]. At 100 MHz, each output driver must dissipate over 100 mW to drive a 100-pF lumped load rail to rail with 3.3-V supplies. Each 100-MHz DRAM could have as many as 16 output drivers operating simultaneously, collectively dissipating over 1.6 W. Not surprisingly, the fine print on data sheets for such parts commonly notes that "power consumption is specified with no load." Transition times for 100-MHz signals are necessarily around 2 ns while, for a track distance of 15 cm on a printed- circuit board, transmission time is typically 1 ns. If proper termination is not used, reflections will harm signal integrity under such circumstances. For many years, emitter-coupled logic (ECL) has been the usual choice for high-speed interfaces. The limited swing of ECL signals and ECL's ability to drive terminated lines made it superior in high-speed systems to the ubiquitous TTL interface. TTL, however, is relatively easy to implement in either MOS field-effect or bipolar transistor technology, whereas ECL interface specifications revolve around the technology of bipolar transistors. And attempts to match ECL with FET devices have, to date, had little success. Bipolar CMOS (BiCMOS) technology can overcome this ECL drawback, of course. But whether BiCMOS will be applicable to all future high-speed devices is debatable; the present economics of adding bipolar capability to all MOS chips just for the output drivers casts doubt on its future. NEW PATHS. Because of all these limitations, new proposals are being put forward for achieving ECL's low swing and ability to drive terminated lines with optimized MOS circuits. Common to all the interfaces proposed here--center-tap terminated, Gunning transceiver logic, and low-voltage differential signaling--is a restricted signal swing, on the order of 1 V or less; however, the base levels from which the swing takes place vary widely. In practical terms, it is difficult to define a standard interface in a way that ensures wide acceptance. It is not sufficient that adherence to a standard may result in a working system under ideal conditions; a standard must be based on a realistic means of testing for and specifying worst-case performance. Only then can a component that meets the specification be guaranteed to perform under realistic system conditions. Components with present-day interfaces are already running into test and specification problems. A chip with restricted- swing interfaces is very difficult to test to worst-case specifications. Nor is agreement easy as to what constitutes a realistic environment. Various new approaches for specifying electric interface characteristics are being considered, such as supplying a set of simulation parameters for a circuit's output drivers. This is a radical departure from the traditional component data sheet, and no one yet fully understands how to test an actual product to ensure that its parameters match those of the simulation. Center-tap terminated interface Richard C. Foss Mosaid Technologies Inc. Like low-voltage CMOS, which has adopted logic levels that reflect 30-year-old TTL standards, the center-tap terminated interface is an evolutionary, back-compatible standard that will ease the transition to new speed requirements. When used unterminated in short-run situations, center-tap terminated (CTT) drivers give regular rail-to-rail swings and CTT receivers have standard input threshold levels. But for longer runs where termination is essential, CTT drivers automatically adjust to a restricted swing with a termination voltage near mid-level. The logic swing is set to a minimum of (plus or minus) 400 mV relative to the termination voltage. The same level is used as an external reference input to CTT receivers, allowing tighter control of input levels than with simple CMOS input buffers. None of the circuit elements needed for CTT are really new. Input buffers using internal reference levels have been widely used in dynamic RAMs (DRAMs). Supplying the reference level externally allows the minimum high-input level and maximum low- input level (the worst-case input levels) to be tightened from 2.0 and 0.8 V, respectively, to (plus or minus) 200 mV, while maintaining acceptable margins for design differences and testing requirements. Standard CMOS output buffers in high-speed static RAMs (SRAMs) are routinely tested with terminated lines, and the control of output swing by feedback techniques has many precedents. One circuit implementation uses a digital form of feedback for preventing excessive swing when driving terminated loads [Fig. 2]. The driver's output state is monitored by an input receiver, which also serves as an input buffer when the terminus is an I/O port. While the output is opposite to the desired state, additional output drive is provided, so performance can match regular LVCMOS when driving large, lumped-capacitance loads. Once the output is in the desired state, the drive is cut back so that there will be a limited swing if a termination resistance is present. Latches ensure that any reflection forcing output levels back toward the original state cannot re-trip the more powerful drivers. While back compatibility forces some compromises--in this case, slightly higher power dissipation in the drivers relative to an open-drain asymmetric driver--benefits include lower system power from symmetrical drives. In the long term, systems employing CTT may evolve to use equal plus and minus supplies relative to a ground reference plane, with signals symmetrically disposed. Gunning transceiver logic Richard Rodgers Xerox Corp. Systems will fully utilize the computing power of present- day very large-scale integration only if IC interfaces change radically. The electric noise created by the nearly rail-to-rail swings of 5-V TTL is far too great and drags out settling times far too long. Even the adoption of low-voltage devices with output swings near 3 V will do little to help the arrival of the transmission speeds users demand for system performance. What is needed is the speed and performance of emitter-coupled logic or bipolar CMOS (ECL and BiCMOS), but at the power and cost of TTL- compatible CMOS. Gunning transceiver logic (GTL) implemented in CMOS easily meets these needs. Additionally, since its output voltage level is independent of Vcc, GTL can be a force for stabilizing the interface environment as device voltages are reduced below the 5- V level. Unlike the current-driver interfaces being proposed, for which the output voltage can change dramatically as the output load changes, GTL output voltage levels are essentially the same, both for terminated and unterminated applications. As a single- ended scheme, it does not require two wires for each connection and hence does not increase the pin requirements for each device, as differential interfaces do. Nor is GTL simply a specification in process or a preliminary design; thousands of device s have already been fabricated and boards using GTL are currently being used in a system prototype. The logic's I/O interface lets CMOS devices communicate at very high speed over terminated transmission-line paths. GTL will also enable processors, application-specific ICs (ASICs), and synchronous memories to operate at 100 MHz with conventional clocking. With reduced clock skew and better data synchronization, 400 MHz and higher data rates could be reached. At 0.8 V (nominal), GTL's signal swing is comparable to that of ECL. Because of this similarity, most design tools and practices developed in the last 20 years for building top- performance ECL systems are applicable to GTL interface design. The low signal-voltage levels keep on-chip power low. Whereas an ECL output typically uses about 125 mW, a similar GTL circuit consumes only 10 mW, so it is practical to include hundreds of GTL I/O circuits on one ASIC. A simple way of seeing the power impact of Gunning transceiver logic is to compare the power requirements for high- speed devices with 160 active I/O drivers that use different types of logic levels: emitter-coupled logic (ECL), backplane transceiver logic (BTL--a form of high-speed inter-face developed by National Semiconductor Corp. in the late 1980s and now in the public domain), and GTL. If implemented with ECL, the drivers would consume 20 W with a 50-(ohms) 3.0-V termination at both ends. If the drivers were implemented using BTL, then they would require a power budget of 11 W with a 50-(ohms), 2.0-V termination. For the same number of drivers, however, GTL would draw only 1.5 W with 50-(ohms), 1.2-V terminations, suiting battery-powered portable devices that require high performance. GTL's low output-stage power allows devices to drive a local motherboard bus directly, without external drivers, thereby lowering cost and simplifying the interconnect. The device cost is low, since current CMOS technology is sufficient; BiCMOS could be used, but is not required. Further, GTL designs can be used without modification as the chip's V(DD) level is reduced with new CMOS process developments; GTL parts designed for a V(DD) of 5 V can readily communicate with those designed for 3.3 V or less. The effect will be to stabilize the industry, as V(DD) might be lowered more than once in the next decade. Second-generation GTL CMOS I/O transceivers are currently being used for both backplane and motherboard interchip bus signals in a high-performance computer system intended for volume production. This includes ASICs with up to 160 GTL I/O cells operating at data rates greater than 100 MHz. Many companies are currently investigating or developing GTL devices, and Xerox Corp. has proposed GTL for industry standardization. At present, the technology may be licensed for a nominal fee. A GTL output driver typically uses an open-drain n-channel device, which, when turned off, is pulled up by an external terminating resistor to the terminating voltage, V(TT), which is equal to 1.2 V. A GTL input receiver is a differential comparator with one side connected to the reference voltage, V(REF), which is typically 0.8 V. Alternatively, an active pull-up GTL output driver may be used for short signal paths with no external terminating resistor. For an upper-level return for the pull-up transistor, V(TT) is brought to a device pin so that the 1.2-V upper level is maintained. Figure 2 shows a bidirectional transmission line built using GTL I/O transceiver cells. Low-voltage differential signaling David B. Gustavson Stanford Linear Accelerator Center David V. James and Glen Stone Apple Computer Inc. Stephen Kempainen National Semiconductor Corp. Low-voltage differential signaling, or LVDS, is the current focus of the IEEE Computer Society P1596.3 working group now developing a high-speed signal interface. The group is seeking an alternative to the ECL-level signals specified by the IEEE Std 15 96-1992 Scalable Coherent Interface (SCI). The P1596.3 work is nearing completion. Some additional circuit prototyping and simulation is planned, and some questions remain on how to specify certain parameters. The group's goal is to specify a new interface that will perform at least as well as emitter-coupled logic (ECL) but cost less for CMOS implementations. It is becoming increasingly clear that fast signals must have small amplitudes to keep power consumption to a level that can realistically and cost- effectively be handled by devices. Also, the variety of technologies likely to be used in the next few years should be capable of generating and receiving small-amplitude signals. Most logic signals in use today are single-ended. They propagate on a single conductor to a receiver, where their voltage level is compared to an easily distributed voltage standard (often the ground, but sometimes another reference). But these signals co-exist with noise from many sources. If they are too small, communication becomes unreliable because of noise on the signal conductor or on the reference voltage standard. Practically, the limit for single-ended transmission is a little less than 1 V. For really high speeds and/or really low power, however, much smaller voltage swings are desirable. To eliminate the noise problems, the wiring is arranged so that the reference voltage is exposed to the same noise as the signal. Thus, the reference is generated near the signal driver, follows the same path (twisted pair or coaxial cable), and is compared to the signal at the receiver. It is even better to transmit the signal complement instead of a constant reference so the receiver merely determines which of the two is more positive. A shield on the cable may further improve noise immunity [Fig. 2, bottom right]. At very high speeds, the advantages of this differential signaling become even more significant. The receiver is designed to ignore any voltage that appears equally on the two conductors (common-mode rejection). In high-speed systems of any real size, high-frequency noise makes the concept of a system-wide ground or any other distributed reference a fiction. Noise problems of this sort have been endemic for years, and are often described as ground bounce. The usual solution is to slow the system with low- pass filtering and "settling" delays until it works. It is important to use a differential signaling method that maintains a constant net current flow. The net signaling current usually flows back from the receiver termination to the transmitter through the ground, so any high-frequency variations in that current contribute to system noise. Even if the net current is constant, reversing the direction of the link (by turning drivers off at one end and on at the other) alters the sign of that current, causing noise. Thus for good system design the net current should be zero, or the links should neither be reversed nor turned on and off. (IEEE Std 1596- 1992 Scalable Coherent Interface--known as SCI--mandates differential ECL signaling, with the termination current returned through the cable or cable shield. It also runs the links continuously and in one direction.) Reversing links, in fact, is incompatible with SCI's scalability. Even if the net current is zero, the reversal introduces a sensitivity to physical scale, because the time required for reversal varies with cable length. The smaller the signal, the easier it is to drive and the more difficult it is to receive. Thus a balance must be sought between these conflicting requirements, and the appropriate one depends on the technology considered. The LVDS working group h as chosen a signal peak-to-peak amplitude of 0.25 V (minimum) at the driver, centered on +1.0 V relative to ground. Receivers should accept signals between 0 V and +2.0 V, thus allowing for up to 1 V of common-mode noise or ground shift. This compromise seems compatible with a variety of technologies, and so the standard should be useful for some time. Differential signaling can double the I/O pin count (though this is partially offset by a reduction in the number of ground pins needed). Further, the higher speed capability lets engineers design with data paths that are narrower than would be possible with other, slower schemes, which also reduces the number of pins that would be needed. There are additional refinements. For example, the driver impedance is constrained to be reasonably constant, independent of the logic state; then common-mode noise that propagates backward and reflects off the drivers is not converted into differential noise by different reflection coefficients on the true and complement signal lines. The receivers have on-chip differential termination resistors, possibly active devices that are servo-matched to an external reference (which relaxes the IC fabrication tolerances). LVDS receivers can be designed to accept larger common-mode voltages (at some increase in cost). However, environments that need more than 1 V often need to handle many volts, requiring optical or magnetic isolation instead. P1596.3 is also defining the encodings for 4-bit- and 8-bit- parallel LVDS links suitable for SCI. The first applications for the LVDS signals are a CMOS implementation of SCI, using 1-byte- wide links at 500 Mbytes per second, and RamLink [P1596.4, described on pp. 52-53.] ABOUT THE AUTHORS. Richard C. Foss (SM) is president of Mosaid Technologies Inc., Kanata, Ont., Canada, and a member of Jedec committees on RAM memories (JC-42.3) and on low voltage and interface (JC-16). Betty Prince (M) is manager, new products, for MOS Memory Worldwide Marketing at Texas Instruments Inc., Houston. She has worked in semiconductor memories for most of her professional life, having held marketing positions with Motorola Inc. and Philips before joining TI in 1990. She is a member of Jedec committees JC-42.3 and JC-16; she founded the latter committee and served as its chair from 1989 to 1990. She is also a member of the IEEE Computer Society P1596.3 working group (Ramlink). Richard Rodgers is manager of memory and logic component engineering for Xerox Corp.'s Electronics Operations in El Segundo, Calif. He is also a member of Jedec committees JC-42.3 and JC-16. David B. Gustavson (M), David V. James (M), Glen Stone (M), and Stephen Kempainen (M) are members of the IEEE Computer Society P1596.3 working group. Anyone who wishes to participate should contact working group chair Stephen Kempainen, National Semiconductor Corp., 2900 Semiconductor Dr., Santa Clara, Calif. 95052-8090; 408-721-4785; fax, 408-737-7218; e-mail stephen@lightning.nsc.com. ***************************************************************** Characteristic voltage levels for commonly used logic ================================================================= | Power | Minimum | Maximum | | Supply | high | low | Output | voltage, | output, | output, | swing, | volts | volts | volts | volts ================================================================= TTL | 5 | 2.4 | 0.4 | 2 ----------------------------------------------------------------- Low-Voltage TTL | 3.3 | 2.4 | 0.4 | 2 ----------------------------------------------------------------- CMOS | 5 | Vcc - DV | DV |Vcc (5max) ----------------------------------------------------------------- Low-Voltage CMOS| 3.3 | Vcc - DV | DV |Vcc (3.3max) ----------------------------------------------------------------- Emitter Coupled | | | | logic (10k) | -5.2 | -1.9 | -1.2 | 0.3 ================================================================= DV = voltage drop due to internal drive requirements. ***************************************************************** To Probe Further Computer Architecture: A Quantitative Approach by John Hennessy and David Patterson (Morgan Kaufmann, San Mateo, Calif., 1990) contains an excellent chapter on memory hierarchy, as does High-Performance Computer Architecture by Harold S. Stone (second edition, Addison-Wesley, Reading, Mass., 1990). Computation Structures by Stephen A. Ward and Robert H. Halstead Jr. (MIT Press, Cambridge, Mass., and McGraw-Hill, New York, 1990) discusses the impact of memory structures on design and performance for a wide range of computer architectures. A table in the article "How DEC developed Alpha" [Spectrum, July 1992, pp. 26-31] provides performance ratings for high-speed processors and serves as an indicator of the type of performance required for high-level workstations. It also indicates how cache is used internally in the design of modern reduced- instruction-set processor chips. Each year, in its April issue, Spectrum surveys the latest developments in personal computers and workstations in a special focus report, including system performance and memory available to support such systems. The use of memory in supercomputers was covered in the September issue of Spectrum. HDTV: Advanced Television for the 1990s by K. Blair Benson and Donald G. Fink (Intertext Publications, New York, and McGraw- Hill, New York, 1991) is a source of basic technical information on high-definition television. An overview of international developments in HDTV appeared in "Chasing Japan in the HDTV Race," [IEEE Spectrum, October 1989, pp. 26-30] and is one of the technologies that will be reviewed in the January 1993 issue of Spectrum. A detailed technical discussion of one of the advanced television features--ghost canceling--that will affect memory requirements appeared in "Good-bye to TV ghosts" in last July's Spectrum [pp. 50-52]. Semiconductor Memories by Betty Prince (second edition, John Wiley & Sons Ltd., Chichester, England, 1991) provides a global view of memory chip technologies, including detailed discussions of the internal organization of static and dynamic RAMs, as well as such other solid-state memory technologies as video RAMs, field-alterable ROMs, and flash memories. For anyone interested in semiconductor memories, it is the basic text. Standardization efforts on synchronous dynamic RAMs were first reported by Ron Wilson in "Jedec hustling to spec new SDRAM" in the March issue of the Electronic Engineering Times, p. 1. The best direct source of information about the status of standards for synchronous DRAMs is the Joint Electron Device Engineering Council (Jedec), 200 Pennsylvania Ave., N.W., Washington, D.C. 20006; 202-457-4973. Jedec has taken to issuing periodic updates on the status of standards activities in committees JC-43 and JC-16, despite a longstanding policy of not allowing discussions of ongoing standards activities. When they become available, Jedec standards may be obtained from Global Engineering Documents, 2805 McGaw Ave., Box 19539, Irvine, Calif. 92713-9539; 800-854-7179. New DRAM technologies are discussed each year at the IEEE- sponsored International Solid State Circuits Conference (ISSCC). This year's conference included a special evening discussion session on how ultralarge-scale integration (ULSI) would affect dynamic RAM, in addition to a regular daytime session in which new DRAM technologies were discussed. Copies of the proceedings may be obtained from the IEEE Service Center Single Publication Sales Unit, 445 Hoes Lane, Box 1331, Piscataway, N.J. 08855- 1331. Next year, the conference will be held from Feb. 24 to 26 at the San Francisco Marriott Hotel. For further information, contact Diane Suiters, c/o Courtesy Associates, 655 15th St., N.W., Suite -300, Washington, D.C. 20005; 202-639-4255. Digital Bus Handbook, edited by Joseph Di Giacomo (McGraw- Hill, New York, 1990), contains chapters that discuss topics such as transmission lines, crosstalk, and transceiver technology, as well as other bus-related issues that are very applicable to memory systems. Some basic information on high-speed transceiver logic can be found on pp. 191-196 of Prince's previously cited book, Semiconductor Memories. Also, the IEEE Journal of Solid State Circuits often publishes articles related to this topic, and discussions can often be found in articles concerning dynamic RAM design. The use of lower working voltages for ICs, which has a heavy impact on interface technologies, was the focus of the article, "ICs going on a 3-V diet," by Betty Prince and Roelof H.W. Salters in the May 1992 issue of Spectrum, pp. 22-25. Jedec Standards 8.0 and 8.1, which specify 3-V IC requirements, may be obtained from Global Engineering Documents at the address previously provided. ACKNOWLEDGMENTS. The editors would like thank all of the contributing authors, but especially Betty Prince of Texas Instruments Inc., Houston, Texas, for her help in conceptualizing and organizing this series, as well as in expediting the creation of the articles it contains. In addition, the editors would like to thank the panel of reviewers. Members of that panel included: Harvey C. Nathanson. Westinghouse Science & Technology Center, Pittsburgh; W. David Pricer, IBM Corp., Essex Junction, Vt., Howard Sussman, NEC El ectronics Inc., Natick, Mass.; and Lu Tran, Micron Semiconductor Corp., Boise, Idaho Copyright 1992, IEEE Spectrum. For more information, send-email to American Cybercasting Corporation (usa@AmeriCast.COM)