\documentstyle[doublespace,11pt]{article}
\begin{document}
\title{UROP Proposal - IAP 1988}
\author{Andr\'e DeHon}
\maketitle
\normalsize
\par
The Data Flow Processing Group of the Laboratory for Computer Science
is currently designing the Monsoon Supercomputer.  Monsoon will be a 
multiprocessor dataflow computer with 256 processor/memory modules
interconnected by a high speed routing network.  The routing network
must be capable of routing messages from any one of the 256 processors,
arranged into boards of 16 processors, to any other at a rate of 800
mega-bits per second.  In order to realize Monsoon's networking needs,
a Pachet Switched Routing Chip (PaRC) is being designed to moderate
network traffic and high speed ECL data links are being developed to 
interconnect the 16 processor boards.
\par

When the PaRC chip has been fabricated, it will need extensive testing
to verify that it works adequately and meets its performance
specifications.  During the upcomming term, I will continue the work I started last
semester to further understand PaRC, determine what kinds of testing
is appropriate for the PaRC chip, and help design basic digital
circuits for the testing and verification of PaRC.
\par

I will work with the LSI design tools under which PaRC is being specified
and Chris Joerg who is designing PaRC in order to further understand 
fully the workings of PaRC.  Once I understand PaRC well enough, I will
devise a series of test vectors adequate to test PaRC's 
functionallity.  These can then be used first to test PaRC using simulation
tools and later to test the actual fabricated chip. 
\par

Testing the actual PaRC chip will involve both basic tests of functionallity
which can be done at low speeds and tests at 50 Mhz. \footnote{50 Mhz is the
desired operational speeds for PaRC}  The basic functional test will involve
programming the Digital Analysis System with the test vectors to verify that
it does indeed behave as specified.  In order to test the PaRC at full speed,
I will have to design simple digital circuitry capable of
driving PaRC at 20ns and verifying its response; this test circuitry should
be general so as to test the wide range of cases necessary to prove that
PaRC will function properly.


\end{document}

