Start support for the RISC-V architecture. RISC-V is a new ISA designed to support computer architecture research and education and is now set become a standard open architecture for industry implementations. Committed the minimal amount of changes requires to compile kernel-toolchain. Also committed machine headers and run-time linker (rtld-elf) support. All the development happens in separate branch, with a goal to move development to head in a few weeks. FreeBSD/RISC-V boots to multiuser in Spike simulator.