Hitachi SH Dependent Features
*****************************

Options
=======

AS has no additional command-line options for the Hitachi SH family.

Syntax
======

Special Characters
------------------

! is the line comment character.

You can use ; instead of a newline to separate statements.

Since $ has no special meaning, you may use it in symbol names.

Register Names
--------------

You can use the predefined symbols r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, and r15 to refer to the SH registers.

The SH also has these control registers:

pr
     procedure register (holds return address)

pc
     program counter

mach
macl
     high and low multiply accumulator registers

sr
     status register

gbr
     global base register

vbr
     vector base register (for interrupt vectors)

Addressing Modes
----------------

AS understands the following addressing modes for the SH. RN in the following refers to any of the numbered registers, but not the control registers.

RN
     Register direct

@RN
     Register indirect

@-RN
     Register indirect with pre-decrement

@RN+
     Register indirect with post-increment

@(DISP, RN)
     Register indirect with displacement

@(R0, RN)
     Register indexed

@(DISP, GBR)
     GBR offset

@(R0, GBR)
     GBR indexed

ADDR
@(DISP, PC)
     PC relative address (for branch or for addressing memory).  The AS implementation allows you to use the simpler form ADDR anywhere a PC relative address is called for; the alternate form is supported for compatibility with other assemblers.

#IMM
     Immediate data

Floating Point
==============

The SH family has no hardware floating point, but the .float directive generates IEEE floating-point numbers for compatibility with other development tools.

SH Machine Directives
=====================

AS has no machine-dependent directives for the SH.

Opcodes
=======

For detailed information on the SH machine instruction set, see SH-Microcomputer User's Manual (Hitachi Micro Systems, Inc.).

AS implements all the standard SH opcodes.  No additional pseudo-instructions are needed on this family.  Note, however, that because AS supports a simpler form of PC-relative addressing, you may simply write (for example)

     mov.l  bar,r0

where other assemblers might require an explicit displacement to bar from the program counter:

     mov.l  @(DISP, PC)