ARM Dependent Features
**********************

Options
=======

-mcpu=PROCESSOR[+EXTENSION...]
     This option specifies the target processor.  The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor.  The following processor names are recognized: arm1, arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620, arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, arm700i, arm710, arm710t, arm720, arm720t, arm740t, arm710c, arm7100, arm7500, arm7500fe, arm7t, arm7tdmi, arm8, arm810, strongarm, strongarm1, strongarm110, strongarm1100, strongarm1110, arm9, arm920, arm920t, arm922t, arm940t, arm9tdmi, arm9e, arm926e, arm926ejs, arm946e-r0, arm946e, arm966e-r0, arm966e, arm10t, arm10e, arm1020, arm1020t, arm1020e, arm1026ejs, arm1136js, arm1136jfs, ep9312 (ARM920 with Cirrus Maverick coprocessor), i80200 (Intel XScale processor) iwmmxt (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor) and xscale. The special name all may be used to allow the assembler to accept instructions valid for any ARM processor.

     In addition to the basic instruction set, the assembler can be told to accept various extension mnemonics that extend the processor using the co-processor instruction space.  For example, -mcpu=arm920+maverick is equivalent to specifying -mcpu=ep9312.  The following extensions are currently supported: +maverick +iwmmxt and +xscale.

-march=ARCHITECTURE[+EXTENSION...]
     This option specifies the target architecture.  The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture.  The following architecture names are recognized: armv1, armv2, armv2a, armv2s, armv3, armv3m, armv4, armv4xm, armv4t, armv4txm, armv5, armv5t, armv5txm, armv5te, armv5texp, armv6, armv6j, iwmmxt and xscale. If both -mcpu and -march are specified, the assembler will use the setting for -mcpu.

     The architecture option can be extended with the same instruction set extension options as the -mcpu option.

-mfpu=FLOATING-POINT-FORMAT

     This option specifies the floating point format to assemble for.  The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target floating point unit. The following format options are recognized: softfpa, fpe, fpe2, fpe3, fpa, fpa10, fpa11, arm7500fe, softvfp, softvfp+vfp, vfp, vfp10, vfp10-r0, vfp9, vfpxd, arm1020t, arm1020e, arm1136jfs and maverick.

     In addition to determining which instructions are assembled, this option also affects the way in which the .double assembler directive behaves when assembling little-endian code.

     The default is dependent on the processor selected.  For Architecture 5 or later, the default is to assembler for VFP instructions; for earlier architectures the default is to assemble for FPA instructions.

-mthumb
     This option specifies that the assembler should start assembling Thumb instructions; that is, it should behave as though the file starts with a .code 16 directive.

-mthumb-interwork
     This option specifies that the output generated by the assembler should be marked as supporting interworking.

-mapcs [26|32]
     This option specifies that the output generated by the assembler should be marked as supporting the indicated version of the Arm Procedure. Calling Standard.

-matpcs
     This option specifies that the output generated by the assembler should be marked as supporting the Arm/Thumb Procedure Calling Standard.  If enabled this option will cause the assembler to create an empty debugging section in the object file called .arm.atpcs.  Debuggers can use this to determine the ABI being used by.

-mapcs-float
     This indicates the floating point variant of the APCS should be used.  In this variant floating point arguments are passed in FP registers rather than integer registers.

-mapcs-reentrant
     This indicates that the reentrant variant of the APCS should be used. This variant supports position independent code.

-mfloat-abi=ABI
     This option specifies that the output generated by the assembler should be marked as using specified floating point ABI. The following values are recognized: soft, softfp and hard.

-EB
     This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.

-EL
     This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor.

-k
     This option specifies that the output of the assembler should be marked as position-independent code (PIC).

-moabi
     This indicates that the code should be assembled using the old ARM ELF conventions, based on a beta release release of the ARM-ELF specifications, rather than the default conventions which are based on the final release of the ARM-ELF specifications.

Syntax
======

Special Characters
------------------

The presence of a @ on a line indicates the start of a comment that extends to the end of the current line.  If a # appears as the first character of a line, the whole line is treated as a comment.

The ; character can be used instead of a newline to separate statements.

Either # or $ can be used to indicate immediate operands.

*TODO* Explain about /data modifier on symbols.

Register Names
--------------

*TODO* Explain about ARM register naming, and the predefined names.

Floating Point
==============

The ARM family uses IEEE floating-point numbers.

ARM Machine Directives
======================

.align EXPRESSION [, EXPRESSION]
     This is the generic .ALIGN directive.  For the ARM however if the first argument is zero (ie no alignment is needed) the assembler will behave as if the argument had been 2 (ie pad to the next four byte boundary).  This is for compatibility with ARM's own assembler.

NAME .req REGISTER NAME
     This creates an alias for REGISTER NAME called NAME.  For example:

                  foo .req r0

.unreq ALIAS-NAME
     This undefines a register alias which was previously defined using the req directive.  For example:

                  foo .req r0
                  .unreq foo

     An error occurs if the name is undefined.  Note - this pseudo op can be used to delete builtin in register name aliases (eg 'r0').  This should only be done if it is really necessary.

.code [16|32]
     This directive selects the instruction set being generated. The value 16 selects Thumb, with the value 32 selecting ARM.

.thumb
     This performs the same action as .CODE 16.

.arm
     This performs the same action as .CODE 32.

.force_thumb
     This directive forces the selection of Thumb instructions, even if the target processor does not support those instructions

.thumb_func
     This directive specifies that the following symbol is the name of a Thumb encoded function.  This information is necessary in order to allow the assembler and linker to generate correct code for interworking between Arm and Thumb instructions and should be used even if interworking is not going to be performed.  The presence of this directive also implies .thumb

.thumb_set
     This performs the equivalent of a .set directive in that it creates a symbol which is an alias for another symbol (possibly not yet defined).  This directive also has the added property in that it marks the aliased symbol as being a thumb function entry point, in the same way that the .thumb_func directive does.

.ltorg
     This directive causes the current contents of the literal pool to be dumped into the current section (which is assumed to be the .text section) at the current location (aligned to a word boundary). GAS maintains a separate literal pool for each section and each sub-section.  The .ltorg directive will only affect the literal pool of the current section and sub-section.  At the end of assembly all remaining, un-empty literal pools will automatically be dumped.

     Note - older versions of GAS would dump the current literal pool any time a section change occurred.  This is no longer done, since it prevents accurate control of the placement of literal pools.

.pool
     This is a synonym for .ltorg.

Opcodes
=======

AS implements all the standard ARM opcodes.  It also implements several pseudo opcodes, including several synthetic load instructions.

NOP

            nop

     This pseudo op will always evaluate to a legal ARM instruction that does nothing.  Currently it will evaluate to MOV r0, r0.

LDR

            ldr <register> , = <expression>

     If expression evaluates to a numeric constant then a MOV or MVN instruction will be used in place of the LDR instruction, if the constant can be generated by either of these instructions.  Otherwise the constant will be placed into the nearest literal pool (if it not already there) and a PC relative LDR instruction will be generated.

ADR

            adr <register> <label>

     This instruction will load the address of LABEL into the indicated register.  The instruction will evaluate to a PC relative ADD or SUB instruction depending upon where the label is located.  If the label is out of range, or if it is not defined in the same file (and section) as the ADR instruction, then an error will be generated.  This instruction will not make use of the literal pool.

ADRL

            adrl <register> <label>

     This instruction will load the address of LABEL into the indicated register.  The instruction will evaluate to one or two PC relative ADD or SUB instructions depending upon where the label is located.  If a second instruction is not needed a NOP instruction will be generated in its place, so that this instruction is always 8 bytes long.

     If the label is out of range, or if it is not defined in the same file (and section) as the ADRL instruction, then an error will be generated. This instruction will not make use of the literal pool.

For information on the ARM or Thumb instruction sets, see ARM Software Development Toolkit Reference Manual, Advanced RISC Machines Ltd.

Mapping Symbols
===============

The ARM ELF specification requires that special symbols be inserted into object files to mark certain features:

$a
     At the start of a region of code containing ARM instructions.

$t
     At the start of a region of code containing THUMB instructions.

$d
     At the start of a region of data.

The assembler will automatically insert these symbols for you - there is no need to code them yourself.  Support for tagging symbols ($b, $f, $p and $m) which is also mentioned in the current ARM ELF specification is not implemented.  This is because they have been dropped from the new EABI and so tools cannot rely upon their presence.