David Golombek
6.371 pset #1
2/21/98
I worked with Andrew Twyman and Jim Waldrop.
All equations within were supposed to be latexed, but I ran out of time,
sorry about the mess.
1A)
We took the given HSPICE model, ran it, and obtained a graph of the
current through the current meter vs the input voltage. We then created
another graph in which we plotted the square root of the above current
vs input voltage. This is from the saturation current formulat -- we're
looking for where current is 0, and thus V_gs = V_t. We obtained a
result of V_t = 0.5V.
1B)
We created another HSPICE model in which we attached 1V the source of
the nMOS device rather than 0V, and reran the above steps. We obtained
a V_t = 1.7V for this model. Then we plugged these two values into
the Body Effect equation
V_T1 = V_T0 + G(sqrt(2*phi_f + abs(V_sb)) - sqrt(abs(2*phi_f)))
We solve for G (Gamma) in terms of V_T1 = 1.7 and V_T0 = .5, and get
G = 2.4V. This is outside of normal Gamma ranges, but we're not
certain why -- it appears our V_T1 is higher than what we'd normally
expect, and this would cause the given result.
1C) The body effect is the effect that a chain of MOS devices have on
the width of the depletion layer. The chain of MOS devices increases
this width due to the higher V_sb, which results in a higher V_t.
David Golombek
6.371 pset #1
2/21/98
I combined parts A and B into the same descriptions, so I only
mention each device once.
2)
Device 1:
With V_IN at 0V, The device is in cutoff because V_gs = 0V. So V_DD
pulls up V_OUT and goes into steady state, ending with:
V_OH = 5V
With V_IN at 5V, V_GS > V_DS + V_T, and our V_DS is small, so the transitor
will be in the linear region. Our V_DS will equal V_OL, since they
are both measured at V_OUT. We're going to be in steady state, so there will
be no current through the ouptu, meaning a constant I through the resistor
(I = (V_DD-V_DS)/R) and the transistor (I = I_DS =
I_DS = (U_n * C_OX)(W/L)((V_GS-V_T)V_DS - (V_DS^2)/2))
We set these equal, and begin to solve for V_DS. We get the quadratic
(1/2)(V_DS^2) + (1+10000*U_n*C_OX*W/L)V_DS - 10000*U_n*C_OX*W/L*V_T*V_DD = 0
which can be solved to a pair of equations
4.915336 +- sqrt(22.829856)
which can be solved to the voltages
V_DS = .0137261V or 9.6933958V
of which 9.6V is bogus, so the solution is V_DS = 137mV, and so
V_OL = 137.2761mV
Device 2:
When V_IN is 0, so bottom nMOS device is in cutoff because V_gs < V_t.
V_OUT starts at 0, so top nMOS device starts in saturation, raising V_OUT.
There is nothing to lower V_OUT, so top nMOS device goes through linear, till
it reaches cutoff, when V_GS = V_T, so V_OUT = V_DD - V_T = 4.25
When V_IN = 5V, bottom FET will be in linear region because it's drain
will be small as load discharges (V_DS < V_GS - V_t). The top FET will
be in saturation since its V_DS > V_GS - V_t.
We know the current equations for the two systems, and so we set them
equal to find the steady state, and solve for V_DS of the top FET.
I_DS1 = I_DS2
after removing cancellations
.5*(V_GS1 - V_tn)^2 = (V_gs2 - V_tn)*V_DS2 - .5*V_DS2^2
since V_GS1 = V_DS1 and V_DS2 = 5-V_DS1, we can turn this into the
quadratic form of
V_DS1^2 - 1.5V_DS1 - 8.46875 = 0
with solutions
V_DS1 = 3.7552 or -2.2552
V_OL = 5 - V_DS1 = 1.244
Device 3:
When V_IN = 0V, this is a normal CMOS device, with nMOS device is
in cutoff (V_GS < V_t), and the pMOS devie is linear region, with
current flowing through it to charge the load all the way up to
V_OH = 5V
When V_IN = 5V, the nMOS device will be in its linear region because
V_GS = 5V, and V_DS < 4.25. The pMOS device will be in saturation
because V_DS > V_GS - abs(V_tp). Again by setting the currents equal
to each other, we can find V_DS for the nMOS device, which will be V_OL.
I_DSN = I_DSP
(V_GSN-V_TN)*V_DSN - .5*V_DSN^2 = .5 * (V_GSP - V_TP)
we know V_DSN - V_DSP = 5, V_GSN = 5, V_GSP = 5
so we can transform this to the quadratic
1.8292V_DSN^2 - 15.548*V_DSN + 8.446 = 0
with solution
V_DSN = V_OL = 0.583213
David Golombek
6.371 pset #1
2/21/98
3A) To find W_n/L_n:W_p/L_p, we need to look at B_p/B_n, because
B = W/L*U*C_OX
Switching occurs when both MOSFETS saturate, which is at
V_IN = V_DD + V_tp + V_tn*sqrt(B_p/B_n)
--------------------------------
1 + sqrt(B_n/B_p)
Solving for B_n/B_p, we get
B_n/B_p = ((V_DD - V_in + V_tp)/V_in - V_tn)^2
which we can turn into
W_n/L_n:W_p/L_p = U_p/U_n * ((V_DD - V_in + V_tp)/(V_in - V_tn))^2
Trying various V_in's we find:
V_in = 1.66, W_n/L_n:W_p/L_p = 2.0137
V_in = 2.5, W_n/L_n:W_p/L_p = 0.2371
V_in = 3.33, W_n/L_n:W_p/L_p = 0.0256
3B) see attached
3C) The thresholds from the HSPICE calculations are all within +-0.3V of
the hand calculations, a difference that can be explained by the
complexity of the model we are using. In this model, both transistors
are saturated and are pushing current in the same directions, an
unstable condition as noted in the book.
3D) This CMOS inverter can
1) Reach exactly 0V and 5V for V_OL and V_OH respectively.
2) Has no static power drain in either state.
It doesn't appear to have any disadvantages, except for possible
problems tuning the rise and fall times to avoid both devices
being in linear region at the same time.
3E) This is a non-regenerative buffer (doesn't pull value to more
stable voltages).
V_OH ~= V_IH - V_tn
V_OL ~= V_IL - V_tp
The bulk terminal of the devices are shorted to V_OUT, rather than GND and
VDD as usual. Thus the body effect will be higher than usual, which
will hurt the efficiency of the circuit.
David Golombek
6.371 pset #1
2/21/98
4A) Using minimum W/L = 1.8/1.2 as before
t_f = 2*C_L/(B_n*V_DD*(1-n)) * ((n-0.1)/(1-n) + .5*ln(19-20n))
where
n = V_tn/V_DD
Solving using the given parameters we get
t_f = 4.5247e-7
t_r = 2*C_L/(B_p*V_DD*(1-p)) * ((p-0.1)/(1-p) + .5*ln(19-20p))
where
p = V_tp/V_DD
Solving using the given parameters we get
t_r = 1.7334e-6
t_dr = t_r/2 = 8.666e-7
t_df = t_f/2 = 2.2623e-7
t_pd = (t_dr + t_df)/2 = 5.4646e-7
The rise and fall times are different because they heavily depend
upon B_p vs B_n, which in turn heavily depend upon the mobility of holes
vs electrons. We expect a switching threshold below 2.5V because
as B_n/B_p goes lower, V_switch goes higher, and as we saw in part
3, for B_n/B_p of 2.0137 we get V_switch = 1.66, and our
B_n/B_p = 3.6585
4B) Setting t_f to t_r and solving for B_p we get
B_p = B_n * (1-n)/(1-p) * ((p-0.1)/(1-p) + .5*ln(19-20p))
-------------------------------
((n-0.1)/(1-n) + .5*ln(19-20n))
B_p = 1.5738, so
W/L = 5.7464, a very large increase
PMOS is stronger than NMOS because it can do active pullup because
it's bulk is wired to a higher voltage, which powers each transition.
4C) The total energy dissipiation of the system is 2.5910pJ. See
attached graph.
4D) The period of oscillation is 1.68nS. See attached graph.
David Golombek
6.371 pset #1
2/21/98
5) These times were done with an input signal with 1nS rise and
fall times, we didn't test it with an idealized input signal.
Fall time = 3.67nS
90%(4.535V) at time 100.89nS
10%(0.500V) at time 104.56nS
Rise time = 14.22nS
10%(0.450V) at time 122.11nS
90%(4.550V) at time 136.33nS
T_pd,lh = 9nS
input to 10%(0.60V) at time 40.89nS
output to 90%(4.50V) at time 49.89nS
T_pd,hl = 3.67nS
input to 90%(4.40V) at time 60.89nS
output to 10%(0.50V) at time 64.56nS
Crossover point is at 2.68V.
Rise and fall times are different because of the differing characteristics
of the nMOS and pMOS devices used in the CMOS device.