
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x95
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|    1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  mainfsm.vhd
Options:    -o2 -ygs -fO -fP -v10 -dc372i -pCY7C372I-66JC mainfsm.vhd
======================================================================

vhdlfe V4 IR x95:  VHDL parser
Tue Mar  9 23:34:23 1999

Library 'work' => directory 'lc372i'
Linking '/u15c/warp4.3/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/u15c/warp4.3/lib/ieee/work'
Linking '/u15c/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/mod_genu.vif'.
mainfsm.vhd (line 42, col 25):  Note: Substituting module 'add_vi_us' for '+'.
mainfsm.vhd (line 43, col 25):  Note: Substituting module 'add_vi_us' for '+'.
mainfsm.vhd (line 44, col 25):  Note: Substituting module 'add_vi_us' for '+'.
mainfsm.vhd (line 172, col 26):  Note: Substituting module 'cmp_vv_us' for '>='.
mainfsm.vhd (line 180, col 28):  Note: Substituting module 'sub_vv_us' for '-'.

vhdlfe:  No errors.


tovif V4 IR x95:  High-level synthesis
Tue Mar  9 23:34:46 1999

Linking '/u15c/warp4.3/lib/common/work/cypress.vif'.
Linking '/u15c/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/mod_genu.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/mcompare.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/madd_sub.vif'.

tovif:  No errors.


topld V4 IR x96:  Synthesis and optimization
Tue Mar  9 23:35:53 1999

Linking '/u15c/warp4.3/lib/common/work/cypress.vif'.
Linking '/u15c/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/mod_genu.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/mcompare.vif'.
Linking '/u15c/warp4.3/lib/common/stdlogic/madd_sub.vif'.
State variable 'state' is represented by a Bit_vector (0 to 4).
State encoding (sequential) for 'state' is:
	startup :=	b"00000";
	normal_wait :=	b"00001";
	normal_go1 :=	b"00010";
	normal_go2 :=	b"00011";
	programming_wait :=	b"00100";
	programming_go1 :=	b"00101";
	programming_go2 :=	b"00110";
	display_wait :=	b"00111";
	display_go1 :=	b"01000";
	display_go2 :=	b"01001";
	selftest_wait :=	b"01010";
	selftest_cycle1 :=	b"01011";
	selftest_cycle2 :=	b"01100";
	selftest_cycle3 :=	b"01101";
	selftest_cycle4 :=	b"01110";
	selftest_cycle5 :=	b"01111";
	selftest_cycle6 :=	b"10000";
	selftest_error :=	b"10001";
	greset1 :=	b"10010";
	greset2 :=	b"10011";
	greset3 :=	b"10100";
	greset4 :=	b"10101";
Linking '/u15c/warp4.3/lib/lc370/stdlogic/c370.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------


Deleted 0 User equations/components.
Deleted 0 Synthesized equations/components.

------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 52 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

----------------------------------------------------------
Circuit simplification results:

	Expanded 32 signals.
	Turned 0 signals into soft nodes.
	Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 178 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN HEADER INFORMATION  (23:37:22)

Input File(s): mainfsm.pla
Device       : c372i
Package      : CY7C372I-66JC
ReportFile   : mainfsm.rpt

Program Controls:
                 None.

Signal Requests:
    GROUP DT-OPT ALL
    GROUP FAST_SLEW ALL

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (23:37:22)

Messages:
  Information: Process virtual 'MODULE_5_g1_a0_g0_u0_ci_2' ... expanded.
  Information: Process virtual 'MODULE_1_g1_a0_gx_u0_lti_0' ... expanded.
  Information: Process virtual 'io_0_FB' ... expanded.
  Information: Process virtual 'io_1_FB' ... expanded.
  Information: Process virtual 'io_2_FB' ... expanded.
  Information: Process virtual 'io_3_FB' ... expanded.
  Information: Process virtual 'stateSBV_4D' ... expanded.
  Information: Process virtual 'stateSBV_3D' ... expanded.
  Information: Process virtual 'stateSBV_2D' ... expanded.
  Information: Process virtual 'stateSBV_1D' ... expanded.
  Information: Process virtual 'stateSBV_0D' ... expanded.
  Information: Process virtual 'io_data_0D' ... expanded.
  Information: Process virtual 'io_data_1D' ... expanded.
  Information: Process virtual 'io_data_2D' ... expanded.
  Information: Process virtual 'io_data_3D' ... expanded.
  Information: Process virtual 'io_zD' ... expanded.
  Information: Process virtual 'n_oeD' ... expanded.
  Information: Process virtual 'n_weD' ... expanded.
  Information: Process virtual 'addr_0D' ... expanded.
  Information: Process virtual 'addr_1D' ... expanded.
  Information: Process virtual 'product_0D' ... expanded.
  Information: Process virtual 'product_1D' ... expanded.
  Information: Process virtual 'product_2D' ... expanded.
  Information: Process virtual 'product_3D' ... expanded.
  Information: Process virtual 'count_0D' ... expanded.
  Information: Process virtual 'count_1D' ... expanded.
  Information: Process virtual 'count_2D' ... expanded.
  Information: Process virtual 'count_3D' ... expanded.
  Information: Process virtual 'MODULE_5_g1_a0_g0_u0_c_0' ... expanded.
  Information: Process virtual 'MODULE_1_g1_a0_gx_u0_lt_2' ... expanded.
  Information: Process virtual 'stateSBV_4' ... converted to NODE.
  Information: Process virtual 'stateSBV_3' ... converted to NODE.
  Information: Process virtual 'stateSBV_2' ... converted to NODE.
  Information: Process virtual 'stateSBV_1' ... converted to NODE.
  Information: Process virtual 'stateSBV_0' ... converted to NODE.
  Information: Process virtual 'io_data_0' ... expanded.
  Information: Process virtual 'io_data_1' ... expanded.
  Information: Process virtual 'io_data_2' ... expanded.
  Information: Process virtual 'io_data_3' ... expanded.
  Information: Process virtual 'io_z' ... converted to NODE.
  Information: Generating both D & T register equations for signal stateSBV_4.D
  Information: Expanding XOR equation found on signal stateSBV_4.T
  Information: Generating both D & T register equations for signal stateSBV_3.D
  Information: Expanding XOR equation found on signal stateSBV_3.T
  Information: Generating both D & T register equations for signal stateSBV_2.D
  Information: Expanding XOR equation found on signal stateSBV_2.T
  Information: Generating both D & T register equations for signal stateSBV_1.D
  Information: Expanding XOR equation found on signal stateSBV_1.T
  Information: Generating both D & T register equations for signal stateSBV_0.D
  Information: Expanding XOR equation found on signal stateSBV_0.T
  Information: Generating both D & T register equations for signal io_z.D
  Information: Expanding XOR equation found on signal io_z.T
  Information: Generating both D & T register equations for signal n_oe.D
  Information: Expanding XOR equation found on signal n_oe.T
  Information: Generating both D & T register equations for signal n_we.D
  Information: Expanding XOR equation found on signal n_we.T
  Information: Generating both D & T register equations for signal addr_0.D
  Information: Expanding XOR equation found on signal addr_0.T
  Information: Generating both D & T register equations for signal addr_1.D
  Information: Expanding XOR equation found on signal addr_1.T
  Information: Generating both D & T register equations for signal product_0.D
  Information: Expanding XOR equation found on signal product_0.T
  Information: Generating both D & T register equations for signal product_1.D
  Information: Expanding XOR equation found on signal product_1.T
  Information: Generating both D & T register equations for signal product_2.D
  Information: Expanding XOR equation found on signal product_2.T
  Information: Generating both D & T register equations for signal product_3.D
  Information: Expanding XOR equation found on signal product_3.T
  Information: Generating both D & T register equations for signal count_0.D
  Information: Expanding XOR equation found on signal count_0.T
  Information: Generating both D & T register equations for signal count_1.D
  Information: Expanding XOR equation found on signal count_1.T
  Information: Generating both D & T register equations for signal count_2.D
  Information: Expanding XOR equation found on signal count_2.T
  Information: Generating both D & T register equations for signal count_3.D
  Information: Expanding XOR equation found on signal count_3.T
  Information: Generating both D & T register equations for signal io_0.D
  Information: Expanding XOR equation found on signal io_0.T
  Information: Generating both D & T register equations for signal io_1.D
  Information: Expanding XOR equation found on signal io_1.T
  Information: Generating both D & T register equations for signal io_2.D
  Information: Expanding XOR equation found on signal io_2.T
  Information: Generating both D & T register equations for signal io_3.D
  Information: Expanding XOR equation found on signal io_3.T
  Information: Optimizing logic without changing polarity for signals:
         stateSBV_4.T stateSBV_3.T stateSBV_2.T stateSBV_1.T stateSBV_0.T
         io_z.T n_oe.T n_we.T addr_0.T addr_1.T product_0.T product_1.T
         product_2.T product_3.T count_0.T count_1.T count_2.T count_3.T
         io_0.T io_1.T io_2.T io_3.T

  Information: Optimizing logic using best output polarity for signals:
         stateSBV_4.D stateSBV_3.D stateSBV_2.D stateSBV_1.D stateSBV_0.D
         io_z.D n_oe.D n_we.D addr_0.D addr_1.D product_0.D product_1.D
         product_2.D product_3.D count_0.D count_1.D count_2.D count_3.D
         MODULE_5_g1_a0_g0_u0_gs_g1_us0 MODULE_1_g1_a0_gx_u0_gne_0_c3_u1
         io_0.D io_1.D io_2.D io_3.D

  Information: Selected logic optimization OFF for signals:
         stateSBV_4.C stateSBV_3.C stateSBV_2.C stateSBV_1.C stateSBV_0.C
         io_z.C n_oe.C n_we.C addr_0.C addr_1.C product_0.C product_1.C
         product_2.C product_3.C count_0.C count_1.C count_2.C count_3.C
         io_0.C io_0.OE io_1.C io_1.OE io_2.C io_2.OE io_3.C io_3.OE



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     11/NOV/97    [v4.02 ] 4 IR x95

LOGIC MINIMIZATION         (23:37:38)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (23:38:03)

Messages:
  Information: Optimizing Banked Preset/Reset requirements.
  Information: Selecting T register equation as minimal for signal count_3
  Information: Sum-Splitting output logic for signal count_3.
  Information: Selecting T register equation as minimal for signal count_2
  Information: Sum-Splitting output logic for signal count_2.
  Information: Selecting T register equation as minimal for signal count_1
  Information: Sum-Splitting output logic for signal count_1.
  Information: Selecting T register equation as minimal for signal count_0
  Information: Sum-Splitting output logic for signal count_0.
  Information: Selecting T register equation as minimal for signal product_3
  Information: Selecting T register equation as minimal for signal product_2
  Information: Selecting T register equation as minimal for signal product_1
  Information: Selecting T register equation as minimal for signal product_0
  Information: Selecting D register equation as minimal for signal addr_1
  Information: Selecting D register equation as minimal for signal addr_0
  Information: Selecting D register equation as minimal for signal n_we
  Information: Selecting D register equation as minimal for signal n_oe
  Information: Selecting D register equation as minimal for signal io_z
  Information: Selecting T register equation as minimal for signal stateSBV_0
  Information: Selecting T register equation as minimal for signal stateSBV_1
  Information: Selecting T register equation as minimal for signal stateSBV_2
  Information: Selecting T register equation as minimal for signal stateSBV_3
  Information: Selecting D register equation as minimal for signal stateSBV_4
  Information: Sum-Splitting output logic for signal stateSBV_4.
  Information: Selecting D register equation as minimal for signal io_0
  Information: Selecting D register equation as minimal for signal io_1
  Information: Selecting D register equation as minimal for signal io_2
  Information: Selecting D register equation as minimal for signal io_3
  Information: Optimizing Banked Preset/Reset requirements.
  Information: Selecting D register equation as minimal for signal io_3
  Information: Selecting D register equation as minimal for signal io_2
  Information: Selecting D register equation as minimal for signal io_1
  Information: Selecting D register equation as minimal for signal io_0
  Information: Selecting D register equation as minimal for signal stateSBV_4
  Information: Selecting T register equation as minimal for signal stateSBV_3
  Information: Selecting T register equation as minimal for signal stateSBV_2
  Information: Selecting T register equation as minimal for signal stateSBV_1
  Information: Selecting T register equation as minimal for signal stateSBV_0
  Information: Selecting D register equation as minimal for signal io_z
  Information: Selecting D register equation as minimal for signal n_oe
  Information: Selecting D register equation as minimal for signal n_we
  Information: Selecting D register equation as minimal for signal addr_0
  Information: Selecting D register equation as minimal for signal addr_1
  Information: Selecting T register equation as minimal for signal product_0
  Information: Selecting T register equation as minimal for signal product_1
  Information: Selecting T register equation as minimal for signal product_2
  Information: Selecting T register equation as minimal for signal product_3
  Information: Selecting T register equation as minimal for signal count_0
  Information: Selecting T register equation as minimal for signal count_1
  Information: Selecting T register equation as minimal for signal count_2
  Information: Selecting T register equation as minimal for signal count_3
  Information: Optimizing logic without changing polarity for signals:
         count_3.T count_2.T count_1.T count_0.T product_3.T product_2.T
         product_1.T product_0.T addr_1.D addr_0.D n_we.D n_oe.D io_z.D
         stateSBV_0.T stateSBV_1.T stateSBV_2.T stateSBV_3.T stateSBV_4.D
         MODULE_5_g1_a0_g0_u0_gs_g1_us0 MODULE_1_g1_a0_gx_u0_gne_0_c3_u1
         io_0.D io_1.D io_2.D io_3.D

  Information: Optimizing logic using best output polarity for signals:
         S_11 S_10 S_9 S_8 S_7 S_6 S_5 S_4 S_3 S_2

  Information: Selected logic optimization OFF for signals:
         count_3.AP count_3.AR count_3.C count_2.AP count_2.AR count_2.C
         count_1.AP count_1.AR count_1.C count_0.AP count_0.AR count_0.C
         product_3.AP product_3.AR product_3.C product_2.AP product_2.AR
         product_2.C product_1.AP product_1.AR product_1.C product_0.AP
         product_0.AR product_0.C addr_1.AP addr_1.AR addr_1.C addr_0.AP
         addr_0.AR addr_0.C n_we.AP n_we.AR n_we.C n_oe.AP n_oe.AR n_oe.C
         io_z.AP io_z.AR io_z.C stateSBV_0.AP stateSBV_0.AR stateSBV_0.C
         stateSBV_1.AP stateSBV_1.AR stateSBV_1.C stateSBV_2.AP stateSBV_2.AR
         stateSBV_2.C stateSBV_3.AP stateSBV_3.AR stateSBV_3.C stateSBV_4.AP
         stateSBV_4.AR stateSBV_4.C io_0.AP io_0.AR io_0.C io_0.OE io_1.AP
         io_1.AR io_1.C io_1.OE io_2.AP io_2.AR io_2.C io_2.OE io_3.AP io_3.AR
         io_3.C io_3.OE



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     11/NOV/97    [v4.02 ] 4 IR x95

LOGIC MINIMIZATION         (23:38:08)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (23:38:29)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN EQUATIONS           (23:38:38)


    /stateSBV_4.D =
          S_11.CMB 
        + S_10.CMB 

    stateSBV_4.AP =
          GND

    stateSBV_4.AR =
          GND

    stateSBV_4.C =
          clk 

    stateSBV_3.T =
          /reset * /stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          /stateSBV_4.Q * /s_0 * /s_1 * button_2 * /button_1 * /button_0 
        + /reset * /stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          /stateSBV_4.Q * s_0 * s_1 * button_2 * /button_1 * /button_0 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * 
          /stateSBV_4.Q * button_2 * button_1 * button_0 
        + /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * stateSBV_3.Q * 
          button_2 * button_1 * /button_0 
        + /reset * /stateSBV_2.Q * stateSBV_4.Q * button_2 * button_1 * 
          button_0 
        + /reset * /stateSBV_0.Q * stateSBV_4.Q * button_2 * /button_1 * 
          /button_0 
        + /reset * stateSBV_0.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          /stateSBV_4.Q 
        + /count_0.Q * /reset * stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q 
        + /count_1.Q * /reset * stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q 
        + /reset * /stateSBV_0.Q * stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q 
        + stateSBV_3.Q * stateSBV_4.Q * button_2 * /button_0 
        + /stateSBV_1.Q * stateSBV_2.Q * stateSBV_3.Q * /stateSBV_4.Q 
        + /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q 
        + /reset * stateSBV_1.Q * stateSBV_4.Q 
        + reset * stateSBV_3.Q 

    stateSBV_3.AP =
          GND

    stateSBV_3.AR =
          GND

    stateSBV_3.C =
          clk 

    stateSBV_2.T =
          /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * /stateSBV_4.Q * /s_1 * button_2 * /button_1 * 
          /button_0 
        + /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * /stateSBV_3.Q * 
          /stateSBV_4.Q * button_2 * button_1 
        + /stateSBV_0.Q * stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * 
          button_2 * /button_0 
        + /stateSBV_0.Q * stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * 
          button_2 * button_1 
        + /stateSBV_0.Q * stateSBV_1.Q * stateSBV_2.Q * stateSBV_3.Q * 
          stateSBV_4.Q 
        + /reset * stateSBV_0.Q * /stateSBV_2.Q * stateSBV_3.Q * 
          stateSBV_4.Q 
        + /reset * stateSBV_1.Q * /stateSBV_2.Q * stateSBV_4.Q 
        + stateSBV_0.Q * stateSBV_2.Q * /stateSBV_3.Q * stateSBV_4.Q 
        + reset * stateSBV_2.Q 

    stateSBV_2.AP =
          GND

    stateSBV_2.AR =
          GND

    stateSBV_2.C =
          clk 

    stateSBV_1.T =
          /reset * /stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          /stateSBV_4.Q * s_0 * s_1 * button_2 * /button_1 * /button_0 
        + /reset * stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * button_2 * 
          /button_1 * /button_0 
        + /reset * stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * /stateSBV_4.Q 
        + stateSBV_1.Q * /stateSBV_2.Q * stateSBV_3.Q * /stateSBV_4.Q * 
          button_2 * button_1 
        + stateSBV_1.Q * stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q 
        + stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * stateSBV_4.Q 
        + reset * stateSBV_1.Q 

    stateSBV_1.AP =
          GND

    stateSBV_1.AR =
          GND

    stateSBV_1.C =
          clk 

    stateSBV_0.T =
          /reset * /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * /stateSBV_4.Q * button_2 * button_1 * button_0 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * 
          /stateSBV_3.Q * /stateSBV_4.Q * button_2 * button_1 * button_0 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * stateSBV_4.Q * button_2 * button_1 * button_0 
        + /reset * /stateSBV_0.Q * stateSBV_2.Q * stateSBV_3.Q * 
          stateSBV_4.Q * button_2 * button_1 * button_0 
        + count_1.Q * count_0.Q * stateSBV_0.Q * stateSBV_2.Q * 
          /stateSBV_3.Q * stateSBV_4.Q 
        + /reset * /stateSBV_0.Q * stateSBV_1.Q * stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q 
        + stateSBV_0.Q * /stateSBV_2.Q * /stateSBV_3.Q * button_2 * 
          button_1 * /button_0 
        + stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          button_2 * button_1 
        + stateSBV_0.Q * /stateSBV_2.Q * /stateSBV_3.Q * /stateSBV_4.Q 
        + reset * stateSBV_0.Q 

    stateSBV_0.AP =
          GND

    stateSBV_0.AR =
          GND

    stateSBV_0.C =
          clk 

    /io_z.D =
          /reset * stateSBV_0.Q * /stateSBV_3.Q * stateSBV_4.Q * /io_z.Q 
        + /reset * stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q 
        + /reset * stateSBV_1.Q * /stateSBV_2.Q * stateSBV_3.Q * 
          stateSBV_4.Q 
        + /reset * /stateSBV_1.Q * stateSBV_2.Q * /stateSBV_4.Q 
        + /reset * stateSBV_2.Q * /stateSBV_3.Q 

    io_z.AP =
          GND

    io_z.AR =
          GND

    io_z.C =
          clk 

    /n_oe.D =
          /reset * stateSBV_0.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q * /n_oe.Q 
        + /reset * /stateSBV_0.Q * stateSBV_1.Q * stateSBV_2.Q * 
          stateSBV_3.Q 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q 
        + /reset * /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q 

    n_oe.AP =
          GND

    n_oe.AR =
          GND

    n_oe.C =
          clk 

    /n_we.D =
          /reset * /stateSBV_0.Q * stateSBV_1.Q * stateSBV_2.Q * 
          /stateSBV_3.Q * /stateSBV_4.Q 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * 
          /stateSBV_3.Q * stateSBV_4.Q 
        + /reset * stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_4.Q * /n_we.Q 
        + /reset * stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_4.Q * /n_we.Q 
        + /reset * stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * /stateSBV_4.Q 
        + /reset * stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q 

    n_we.AP =
          GND

    n_we.AR =
          GND

    n_we.C =
          clk 

    addr_0.D =
          /reset * stateSBV_0.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q * addr_0.Q 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_4.Q * s_0 
        + /reset * stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * s_0 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_3.Q * s_0 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * s_0 
        + count_0.Q * /reset * stateSBV_1.Q * stateSBV_3.Q * stateSBV_4.Q 
        + count_0.Q * /reset * stateSBV_0.Q * /stateSBV_4.Q 
        + count_0.Q * /reset * stateSBV_1.Q * stateSBV_2.Q 
        + count_0.Q * /reset * stateSBV_0.Q * stateSBV_3.Q 
        + count_0.Q * /reset * stateSBV_0.Q * stateSBV_2.Q 

    addr_0.AP =
          GND

    addr_0.AR =
          GND

    addr_0.C =
          clk 

    addr_1.D =
          /reset * stateSBV_0.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q * addr_1.Q 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_4.Q * s_1 
        + /reset * stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * s_1 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_3.Q * s_1 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * s_1 
        + count_1.Q * /reset * stateSBV_1.Q * stateSBV_3.Q * stateSBV_4.Q 
        + count_1.Q * /reset * stateSBV_0.Q * /stateSBV_4.Q 
        + count_1.Q * /reset * stateSBV_1.Q * stateSBV_2.Q 
        + count_1.Q * /reset * stateSBV_0.Q * stateSBV_3.Q 
        + count_1.Q * /reset * stateSBV_0.Q * stateSBV_2.Q 

    addr_1.AP =
          GND

    addr_1.AR =
          GND

    addr_1.C =
          clk 

    product_0.T =
          /reset * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * /s_0 * /s_1 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * /product_0.Q 
        + /io_3 * /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * /s_0 * /s_1 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * /product_0.Q 
        + /io_3 * /reset * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * /s_0 * /s_1 * 
          /product_0.Q 
        + count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * s_1 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * product_0.Q 
        + /io_3 * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * s_1 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * product_0.Q 
        + count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * s_0 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * product_0.Q 
        + /io_3 * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * s_0 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * product_0.Q 
        + /io_3 * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * s_1 * product_0.Q 
        + /io_3 * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * s_0 * product_0.Q 
        + count_1.Q * count_0.Q * stateSBV_0.Q * /stateSBV_1.Q * 
          stateSBV_2.Q * /stateSBV_3.Q * stateSBV_4.Q * product_0.Q 
        + /reset * stateSBV_0.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q * /product_0.Q 
        + /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          /stateSBV_4.Q * product_0.Q 
        + reset * product_0.Q 

    product_0.AP =
          GND

    product_0.AR =
          GND

    product_0.C =
          clk 

    product_1.T =
          /reset * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * s_0 * /s_1 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * /product_1.Q 
        + /io_3 * /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * s_0 * /s_1 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * /product_1.Q 
        + /io_3 * /reset * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * s_0 * /s_1 * 
          /product_1.Q 
        + count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * s_1 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * product_1.Q 
        + /io_3 * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * s_1 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * product_1.Q 
        + count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * /s_0 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * product_1.Q 
        + /io_3 * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * /s_0 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * product_1.Q 
        + /io_3 * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * s_1 * product_1.Q 
        + /io_3 * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * /s_0 * product_1.Q 
        + count_1.Q * count_0.Q * stateSBV_0.Q * /stateSBV_1.Q * 
          stateSBV_2.Q * /stateSBV_3.Q * stateSBV_4.Q * product_1.Q 
        + /reset * stateSBV_0.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q * /product_1.Q 
        + /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          /stateSBV_4.Q * product_1.Q 
        + reset * product_1.Q 

    product_1.AP =
          GND

    product_1.AR =
          GND

    product_1.C =
          clk 

    product_2.T =
          /reset * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * /s_0 * s_1 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * /product_2.Q 
        + /io_3 * /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * /s_0 * s_1 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * /product_2.Q 
        + /io_3 * /reset * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * /s_0 * s_1 * 
          /product_2.Q 
        + count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * /s_1 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * product_2.Q 
        + /io_3 * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * /s_1 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * product_2.Q 
        + count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * s_0 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * product_2.Q 
        + /io_3 * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * s_0 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * product_2.Q 
        + /io_3 * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * /s_1 * product_2.Q 
        + /io_3 * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * s_0 * product_2.Q 
        + count_1.Q * count_0.Q * stateSBV_0.Q * /stateSBV_1.Q * 
          stateSBV_2.Q * /stateSBV_3.Q * stateSBV_4.Q * product_2.Q 
        + /reset * stateSBV_0.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q * /product_2.Q 
        + /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          /stateSBV_4.Q * product_2.Q 
        + reset * product_2.Q 

    product_2.AP =
          GND

    product_2.AR =
          GND

    product_2.C =
          clk 

    product_3.T =
          /reset * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * s_0 * s_1 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * /product_3.Q 
        + /io_3 * /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * s_0 * s_1 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * /product_3.Q 
        + /io_3 * /reset * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * s_0 * s_1 * 
          /product_3.Q 
        + count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * /s_1 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * product_3.Q 
        + /io_3 * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * /s_1 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * product_3.Q 
        + count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * /s_0 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * product_3.Q 
        + /io_3 * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * /s_0 * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * product_3.Q 
        + /io_3 * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * /s_1 * product_3.Q 
        + /io_3 * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * /s_0 * product_3.Q 
        + count_1.Q * count_0.Q * stateSBV_0.Q * /stateSBV_1.Q * 
          stateSBV_2.Q * /stateSBV_3.Q * stateSBV_4.Q * product_3.Q 
        + /reset * stateSBV_0.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q * /product_3.Q 
        + /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          /stateSBV_4.Q * product_3.Q 
        + reset * product_3.Q 

    product_3.AP =
          GND

    product_3.AR =
          GND

    product_3.C =
          clk 

    count_0.T =
          S_9.CMB 
        + S_8.CMB 

    count_0.AP =
          GND

    count_0.AR =
          GND

    count_0.C =
          clk 

    count_1.T =
          S_7.CMB 
        + S_6.CMB 

    count_1.AP =
          GND

    count_1.AR =
          GND

    count_1.C =
          clk 

    count_2.T =
          S_5.CMB 
        + S_4.CMB 

    count_2.AP =
          GND

    count_2.AR =
          GND

    count_2.C =
          clk 

    count_3.T =
          S_3.CMB 
        + S_2.CMB 

    count_3.AP =
          GND

    count_3.AR =
          GND

    count_3.C =
          clk 

    MODULE_5_g1_a0_g0_u0_gs_g1_us0 =
          /count_1.Q * /count_0.Q * io_0 
        + /count_0.Q * io_1 * io_0 
        + /count_1.Q * io_1 

    S_11 =
          stateSBV_1.Q * /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q 
        + stateSBV_0.Q * /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q 
        + stateSBV_2.Q * /stateSBV_3.Q * stateSBV_4.Q 
        + reset 

    S_10 =
          /io_3 * stateSBV_1.Q * stateSBV_3.Q * stateSBV_4.Q * /io_2 * 
          /io_1 * /io_0 * /count_2.Q 
        + io_3 * stateSBV_1.Q * stateSBV_3.Q * stateSBV_4.Q * io_2 * io_1 * 
          io_0 * count_2.Q 
        + count_1.Q * count_0.Q * stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * /stateSBV_3.Q * /stateSBV_4.Q * count_2.Q 
        + /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          /stateSBV_4.Q * s_0 
        + /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * stateSBV_3.Q * 
          /button_2 * /button_0 
        + /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * stateSBV_3.Q * 
          button_2 * button_0 
        + /count_3.Q * stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * /stateSBV_4.Q 
        + /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_3.Q * stateSBV_4.Q * 
          button_2 * /button_0 
        + /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_3.Q * /stateSBV_4.Q * 
          button_1 
        + /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * stateSBV_3.Q * 
          /stateSBV_4.Q 
        + /stateSBV_1.Q * stateSBV_2.Q * stateSBV_4.Q * button_2 * 
          /button_0 
        + /stateSBV_1.Q * stateSBV_2.Q * stateSBV_4.Q * button_2 * 
          button_1 
        + /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * stateSBV_3.Q * 
          button_1 
        + /stateSBV_1.Q * /stateSBV_3.Q * stateSBV_4.Q * button_2 * 
          button_1 
        + /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_3.Q * /stateSBV_4.Q * 
          button_0 
        + /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_3.Q * /stateSBV_4.Q * 
          /button_2 

    io_0.D =
          /reset * stateSBV_0.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q * io_0.Q 
        + count_0.Q * /reset * /stateSBV_1.Q * stateSBV_2.Q * stateSBV_3.Q * 
          /stateSBV_4.Q 
        + /reset * stateSBV_1.Q * /stateSBV_2.Q * stateSBV_3.Q * 
          stateSBV_4.Q * count_2.Q 
        + count_0.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          stateSBV_2.Q * /stateSBV_3.Q 
        + /reset * stateSBV_1.Q * stateSBV_2.Q * /stateSBV_3.Q * count_2.Q 

    io_0.AP =
          GND

    io_0.AR =
          GND

    io_0.C =
          clk 

    io_0.OE =
          /io_z.Q 

    io_1.D =
          /reset * stateSBV_1.Q * /stateSBV_2.Q * stateSBV_3.Q * 
          stateSBV_4.Q * count_2.Q 
        + /reset * stateSBV_0.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q * io_1.Q 
        + count_1.Q * /reset * /stateSBV_1.Q * stateSBV_2.Q * stateSBV_3.Q * 
          /stateSBV_4.Q 
        + count_1.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          stateSBV_2.Q * /stateSBV_3.Q 
        + /reset * stateSBV_1.Q * stateSBV_2.Q * /stateSBV_3.Q * count_2.Q 

    io_1.AP =
          GND

    io_1.AR =
          GND

    io_1.C =
          clk 

    io_1.OE =
          /io_z.Q 

    io_2.D =
          /reset * stateSBV_0.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q * io_2.Q 
        + /reset * /stateSBV_1.Q * stateSBV_2.Q * stateSBV_3.Q * 
          /stateSBV_4.Q * count_2.Q 
        + /reset * stateSBV_1.Q * /stateSBV_2.Q * stateSBV_3.Q * 
          stateSBV_4.Q * count_2.Q 
        + /reset * /stateSBV_0.Q * stateSBV_2.Q * /stateSBV_3.Q * 
          count_2.Q 

    io_2.AP =
          GND

    io_2.AR =
          GND

    io_2.C =
          clk 

    io_2.OE =
          /io_z.Q 

    S_9 =
          /count_0.Q * /reset * stateSBV_0.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * /stateSBV_4.Q 
        + /count_0.Q * /reset * stateSBV_0.Q * stateSBV_2.Q * stateSBV_4.Q 
        + count_0.Q * reset 

    S_8 =
          count_0.Q * /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * /stateSBV_4.Q * button_2 * /button_1 * /button_0 
        + count_0.Q * /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * /stateSBV_4.Q * button_2 * button_1 * button_0 
        + /reset * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * io_0 
        + /io_3 * /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * io_0 
        + /io_3 * /reset * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * io_0 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * 
          /stateSBV_3.Q * /stateSBV_4.Q * /button_2 * button_0 
        + count_0.Q * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * 
          stateSBV_3.Q * button_2 * button_1 * button_0 
        + count_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q * button_2 * button_1 * button_0 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * stateSBV_4.Q * /button_2 * button_0 
        + /count_0.Q * /reset * stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * stateSBV_4.Q * io_0 
        + count_0.Q * stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q * button_2 * /io_0 
        + count_0.Q * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * 
          /stateSBV_4.Q * button_1 * button_0 
        + count_0.Q * /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * stateSBV_4.Q * /io_0 
        + /reset * stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * 
          /stateSBV_3.Q * stateSBV_4.Q 
        + /reset * stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * /stateSBV_4.Q 
        + count_0.Q * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * 
          stateSBV_3.Q * /stateSBV_4.Q 

    S_7 =
          count_1.Q * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * 
          stateSBV_3.Q * button_2 * button_1 * button_0 
        + count_1.Q * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * 
          /stateSBV_4.Q * button_2 * button_1 * button_0 
        + count_0.Q * /reset * stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * /stateSBV_3.Q * /stateSBV_4.Q 
        + count_0.Q * /reset * stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * 
          /stateSBV_3.Q * stateSBV_4.Q 
        + /count_1.Q * /reset * stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * stateSBV_4.Q * io_1 
        + count_1.Q * stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q * button_2 * /io_1 
        + /count_1.Q * count_0.Q * /reset * stateSBV_0.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * /stateSBV_4.Q 
        + count_1.Q * /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * stateSBV_4.Q * /io_1 
        + count_1.Q * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * 
          stateSBV_3.Q * /stateSBV_4.Q 
        + /count_1.Q * count_0.Q * /reset * stateSBV_0.Q * stateSBV_2.Q * 
          stateSBV_4.Q 
        + count_1.Q * reset 

    S_6 =
          /count_0.Q * /reset * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * /io_1 * io_0 
        + /io_3 * /count_0.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * /io_1 * io_0 
        + /io_3 * /count_0.Q * /reset * count_3.Q * /stateSBV_0.Q * 
          /stateSBV_1.Q * /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * 
          /io_1 * io_0 
        + /reset * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * io_1 * /io_0 
        + /io_3 * /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * io_1 * /io_0 
        + /io_3 * /reset * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * io_1 * /io_0 
        + count_0.Q * /reset * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * io_1 
        + /io_3 * count_0.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * io_1 
        + /io_3 * count_0.Q * /reset * count_3.Q * /stateSBV_0.Q * 
          /stateSBV_1.Q * /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * 
          io_1 
        + count_1.Q * /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * /stateSBV_4.Q * button_2 * /button_1 * /button_0 
        + count_1.Q * /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * /stateSBV_4.Q * button_2 * button_1 * button_0 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * 
          /stateSBV_3.Q * /stateSBV_4.Q * /button_2 * button_1 * /button_0 
        + count_0.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          stateSBV_2.Q * /stateSBV_3.Q * /stateSBV_4.Q * /button_2 * 
          button_0 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * stateSBV_4.Q * /button_2 * button_1 * /button_0 
        + count_0.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * /stateSBV_3.Q * stateSBV_4.Q * /button_2 * 
          button_0 
        + count_1.Q * /stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q * button_2 * button_1 * button_0 

    S_5 =
          count_1.Q * count_0.Q * /reset * stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * /stateSBV_3.Q * /stateSBV_4.Q 
        + count_1.Q * count_0.Q * /reset * stateSBV_0.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * /stateSBV_4.Q * /count_2.Q 
        + /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * stateSBV_3.Q * 
          button_2 * button_1 * button_0 * count_2.Q 
        + /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * /stateSBV_4.Q * 
          button_2 * button_1 * button_0 * count_2.Q 
        + count_1.Q * count_0.Q * stateSBV_0.Q * /stateSBV_1.Q * 
          stateSBV_2.Q * /stateSBV_3.Q * stateSBV_4.Q * count_2.Q 
        + /stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * stateSBV_4.Q * 
          button_2 * button_1 * button_0 * count_2.Q 
        + /reset * stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q * io_2 * /count_2.Q 
        + /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q * /io_2 * count_2.Q 
        + stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * stateSBV_4.Q * 
          button_2 * /io_2 * count_2.Q 
        + /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * stateSBV_3.Q * 
          /stateSBV_4.Q * count_2.Q 
        + reset * count_2.Q 

    S_4 =
          count_1.Q * count_0.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          stateSBV_2.Q * /stateSBV_3.Q * /stateSBV_4.Q * /button_2 * 
          /button_1 * button_0 
        + count_1.Q * count_0.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * /stateSBV_3.Q * stateSBV_4.Q * /button_2 * 
          /button_1 * button_0 
        + /count_0.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          stateSBV_2.Q * /stateSBV_3.Q * /stateSBV_4.Q * /button_2 * 
          button_1 * button_0 
        + /count_0.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * /stateSBV_3.Q * stateSBV_4.Q * /button_2 * 
          button_1 * button_0 
        + count_1.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          stateSBV_2.Q * /stateSBV_3.Q * /stateSBV_4.Q * /button_2 * 
          button_1 * /button_0 
        + /count_1.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          stateSBV_2.Q * /stateSBV_3.Q * /stateSBV_4.Q * /button_2 * 
          button_1 * button_0 
        + /reset * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * io_2 * 
          /MODULE_5_g1_a0_g0_u0_gs_g1_us0.CMB 
        + /io_3 * /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * io_2 * 
          /MODULE_5_g1_a0_g0_u0_gs_g1_us0.CMB 
        + /io_3 * /reset * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * io_2 * 
          /MODULE_5_g1_a0_g0_u0_gs_g1_us0.CMB 
        + /reset * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * /io_2 * 
          MODULE_5_g1_a0_g0_u0_gs_g1_us0.CMB 
        + /io_3 * /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * /io_2 * 
          MODULE_5_g1_a0_g0_u0_gs_g1_us0.CMB 
        + /io_3 * /reset * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * /io_2 * 
          MODULE_5_g1_a0_g0_u0_gs_g1_us0.CMB 
        + count_1.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * /stateSBV_3.Q * stateSBV_4.Q * /button_2 * 
          button_1 * /button_0 
        + /count_1.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * /stateSBV_3.Q * stateSBV_4.Q * /button_2 * 
          button_1 * button_0 
        + /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * stateSBV_3.Q * 
          /stateSBV_4.Q * button_2 * /button_1 * /button_0 * count_2.Q 
        + /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * stateSBV_3.Q * 
          /stateSBV_4.Q * button_2 * button_1 * button_0 * count_2.Q 

    S_3 =
          count_1.Q * count_0.Q * /reset * /count_3.Q * stateSBV_0.Q * 
          /stateSBV_2.Q * /stateSBV_3.Q * /stateSBV_4.Q * count_2.Q 
        + /reset * /count_3.Q * stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * /stateSBV_4.Q * button_2 * /button_1 * /button_0 
        + count_3.Q * /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * /stateSBV_4.Q * /button_2 * /button_1 * button_0 
        + /io_3 * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * /count_2.Q * 
          MODULE_5_g1_a0_g0_u0_gs_g1_us0.CMB 
        + /io_3 * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * io_2 * 
          MODULE_5_g1_a0_g0_u0_gs_g1_us0.CMB 
        + count_3.Q * /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * /stateSBV_4.Q * button_2 * button_1 * button_0 
        + count_1.Q * count_0.Q * count_3.Q * stateSBV_0.Q * /stateSBV_1.Q * 
          stateSBV_2.Q * /stateSBV_3.Q * stateSBV_4.Q 
        + count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * 
          /stateSBV_4.Q * button_2 * button_1 * button_0 
        + count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * 
          stateSBV_3.Q * button_2 * button_1 * button_0 
        + count_3.Q * /stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q * button_2 * button_1 * button_0 
        + io_3 * /reset * /count_3.Q * stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * stateSBV_4.Q 
        + /io_3 * count_3.Q * stateSBV_1.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q * button_2 
        + /io_3 * count_3.Q * /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * stateSBV_4.Q 
        + count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * 
          stateSBV_3.Q * /stateSBV_4.Q 
        + reset * count_3.Q 

    S_2 =
          count_1.Q * count_0.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          stateSBV_2.Q * /stateSBV_3.Q * /stateSBV_4.Q * /button_2 * 
          button_1 * button_0 
        + count_1.Q * count_0.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          stateSBV_2.Q * /stateSBV_3.Q * /stateSBV_4.Q * /button_2 * 
          button_0 * count_2.Q 
        + count_1.Q * count_0.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * /stateSBV_3.Q * stateSBV_4.Q * /button_2 * 
          button_1 * button_0 
        + count_1.Q * count_0.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * /stateSBV_3.Q * stateSBV_4.Q * /button_2 * 
          button_0 * count_2.Q 
        + io_3 * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * /io_2 * 
          /MODULE_5_g1_a0_g0_u0_gs_g1_us0.CMB 
        + io_3 * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * count_2.Q * 
          /MODULE_5_g1_a0_g0_u0_gs_g1_us0.CMB 
        + io_3 * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * /io_2 * count_2.Q 
        + /io_3 * /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * /count_2.Q * 
          MODULE_5_g1_a0_g0_u0_gs_g1_us0.CMB 
        + /io_3 * /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * io_2 * 
          MODULE_5_g1_a0_g0_u0_gs_g1_us0.CMB 
        + /io_3 * /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          stateSBV_3.Q * stateSBV_4.Q * 
          /MODULE_1_g1_a0_gx_u0_gne_0_c3_u1.CMB * io_2 * /count_2.Q 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * 
          /stateSBV_3.Q * /stateSBV_4.Q * /button_2 * button_1 * button_0 * 
          count_2.Q 
        + count_1.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          stateSBV_2.Q * /stateSBV_3.Q * /stateSBV_4.Q * /button_2 * 
          button_1 * count_2.Q 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * stateSBV_4.Q * /button_2 * button_1 * button_0 * 
          count_2.Q 
        + count_1.Q * /reset * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * /stateSBV_3.Q * stateSBV_4.Q * /button_2 * 
          button_1 * count_2.Q 
        + count_1.Q * count_0.Q * count_3.Q * stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * /stateSBV_3.Q * /stateSBV_4.Q * count_2.Q 
        + /io_3 * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          /stateSBV_2.Q * stateSBV_3.Q * stateSBV_4.Q * io_2 * /count_2.Q 

    MODULE_1_g1_a0_gx_u0_gne_0_c3_u1 =
          /count_1.Q * /count_0.Q * io_0 * /count_2.Q 
        + /count_1.Q * /count_0.Q * io_2 * io_0 
        + /count_0.Q * io_1 * io_0 * /count_2.Q 
        + /count_0.Q * io_2 * io_1 * io_0 
        + /count_1.Q * io_1 * /count_2.Q 
        + /count_1.Q * io_2 * io_1 
        + io_2 * /count_2.Q 

    io_3.D =
          /reset * stateSBV_0.Q * /stateSBV_2.Q * /stateSBV_3.Q * 
          stateSBV_4.Q * io_3.Q 
        + /reset * count_3.Q * /stateSBV_1.Q * stateSBV_2.Q * stateSBV_3.Q * 
          /stateSBV_4.Q 
        + /reset * stateSBV_1.Q * /stateSBV_2.Q * stateSBV_3.Q * 
          stateSBV_4.Q * count_2.Q 
        + /reset * count_3.Q * /stateSBV_0.Q * /stateSBV_1.Q * 
          stateSBV_2.Q * /stateSBV_3.Q 
        + /reset * stateSBV_1.Q * stateSBV_2.Q * /stateSBV_3.Q * count_2.Q 

    io_3.AP =
          GND

    io_3.AR =
          GND

    io_3.C =
          clk 

    io_3.OE =
          /io_z.Q 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN RULE CHECK          (23:38:45)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

PARTITION LOGIC            (23:38:50)

Messages:
  Information: Checking design is strictly SYNCHRONOUS.
  Information: Initializing Logic Block structures.
  Information: Checking for duplicate NODE logic.
  Information: Forming input seeds.
  Information: Forming input seeds.
  Information: Assigning fixed logic to Logic Blocks.
  Information: Processing banked global preset, reset and output enable.
  Information: Separating output logic set to GND/VCC.
  Information: Validating Logic Block's with pre-placed signals.
  Information: Separating input register logic.
  Information: Assigning initializing equations to empty Logic Blocks.
  Information: Separating output combinatorial logic.
  Information: Separating disjoint output logic.
  Information: Separating output node logic.
  Information: Assigning floating outputs to Logic Blocks.
  Information: Assigning floating outputs to Logic Blocks.
  Information: Compacting Logic Block interconnect.
  .+............................................
  Information: Separating disjoint output logic.
  Information: Separating output node logic.
  Information: Assigning floating outputs to Logic Blocks.
  Information: Assigning floating inputs to Logic Blocks.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (23:39:14)

Messages:
  Information: Fitting signals to Logic Block A.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block B.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block C.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ..+..............................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ..+................+..............................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block D.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ..+................+..............................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Routing signals to Logic Blocks.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

LOGIC BLOCK A PLACEMENT   (23:39:16)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(S_8)
XXXXXXXXXXXXXXXX................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2 |[i/p]
..........++++++++++++++++......................................................
| 3 |UNUSED
..............++++++++++++++++..................................................
| 4 |[i/p]
..................++++++++++++++++..............................................
| 5 |(MODULE_5_g1_a0_g0_u0_gs_g1_us0)
......................XXX+++++++++++++..........................................
| 6 |(MODULE_1_g1_a0_gx_u0_gne_0_c3_u1)
..........................XXXX++XX++X+++++......................................
| 7 |(S_7)
..............................XX++XX++XXXXX+XX..................................
| 8 |(S_11)
..................................+++++++++X++X+XX..............................
| 9 |(S_9)
......................................+++++++++X++XX++..........................
|10 |UNUSED
..........................................++++++++++++++++......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12 |UNUSED
..................................................++++++++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14 |UNUSED
..........................................................++++++++++++++++......
|15 |(S_5)
................................................................XXXXXXXXXXX+++++
________________________________________________________________________________

Total count of outputs placed        =  7 
Total count of unique Product Terms  =  55 
Total Product Terms to be assigned   =  55 
Max Product Terms used / available   =  55 /  80   = 68.76 %


Control Signals for Logic Block A
---------------------------------
CLK pin  13 : <not used>
CLK pin  35 : <not used>
PRESET      : <not used>
RESET       : <not used>
OE 0        : <not used>
OE 1        : <not used>
OE 2        : <not used>
OE 3        : <not used>



                              Logic Block A
                 ____________________________________________
                 |   |= >io_3                           |   |                 
                 |   |= >stateSBV_1.Q                   |   |                 
                 |   |= >io_1                           |   |                 
                 |   |> not used:48                     |   |                 
                 |   |> not used:49                     |  2|= (S_8)          
                 |   |> not used:50                     |   |                 
                 |   |= >io_0             not used:202 *|   |                 
                 |   |= >stateSBV_0.Q                   |   |                 
                 |   |= >io_2                           |  3|= s_0            
                 |   |= >count_0.Q                      |   |                 
                 |   |= >stateSBV_2.Q     not used:204 *|   |                 
                 |   |= >stateSBV_4.Q                   |   |                 
                 |   |= >reset                          |  4|= reset          
                 |   |= >MODULE_1_g1..                  |   |                 
                 |   |= >stateSBV_3.Q   (MODULE_5_g1_a0_g0_u0_gs_g1_us0) =|   |                 
                 |   |> not used:60                     |   |                 
                 |   |> not used:61                     |  5|= (MODULE_1_g1_a0_gx_u0_gne_0_c3_u1) 
                 |   |= >button_2                       |   |                 
                 |   |= >button_1                (S_7) =|   |                 
                 |   |> not used:64                     |   |                 
                 |   |> not used:65                     |  6|= (S_11)         
                 |   |= >count_1.Q                      |   |                 
                 |   |= >count_2.Q               (S_9) =|   |                 
                 |   |> not used:68                     |   |                 
                 |   |> not used:69                     |  7|* not used       
                 |   |> not used:70                     |   |                 
                 |   |> not used:71       not used:212 *|   |                 
                 |   |> not used:72                     |   |                 
                 |   |= >button_0                       |  8|* not used       
                 |   |> not used:74                     |   |                 
                 |   |> not used:75       not used:214 *|   |                 
                 |   |> not used:76                     |   |                 
                 |   |> not used:77                     |  9|* not used       
                 |   |= >count_3.Q                      |   |                 
                 |   |> not used:79              (S_5) =|   |                 
                 |   |> not used:80                     |   |                 
                 |   |> not used:81                     |   |                 
                 |   |> not used:82                     |   |                 
                 |   |> not used:83                     |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    5  |    8  |
                 | Buried Macrocells  |    4  |    8  |
                 | PIM Input Connects |   18  |   36  |
                 ______________________________________
                                          27  /   52   = 51  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

LOGIC BLOCK B PLACEMENT   (23:39:21)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |n_we
XXXXXX++++++++++................................................................
| 1 |(S_3)
......XXXXXXXXXXXXX+XX..........................................................
| 2 |io_3
..........+++++++++X++XXXX......................................................
| 3 |UNUSED
..............++++++++++++++++..................................................
| 4 |UNUSED
..................++++++++++++++++..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6 |io_2
..........................XXXX++++++++++++......................................
| 7 |(S_10)
..............................XXXXXXXXXXXXXXXX..................................
| 8 |count_3
..................................++++++++++++++XX..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10 |io_1
..........................................++++XX++XX+++X++......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12 |io_0
..................................................XX++X+XX++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14 |(io_z)
..........................................................XXXXX+++++++++++......
|15 |(S_4)
................................................................XXXXXXXXXXXXXXXX
________________________________________________________________________________

Total count of outputs placed        =  10 
Total count of unique Product Terms  =  74 
Total Product Terms to be assigned   =  79 
Max Product Terms used / available   =  77 /  80   = 96.26 %


Control Signals for Logic Block B
---------------------------------
CLK pin  13 : clk
CLK pin  35 : <not used>
PRESET      : GND
RESET       : GND
OE 0        : /io_z.Q 
OE 1        : <not used>
OE 2        : /io_z.Q 
OE 3        : <not used>



                              Logic Block B
                 ____________________________________________
                 |   |= >stateSBV_4.Q                   |   |                 
                 |   |= >reset                          |   |                 
                 |   |= >button_2                       |   |                 
                 |   |= >io_1                           |   |                 
                 |   |= >S_3.CMB                        | 14|= n_we           
                 |   |= >count_3.Q                      |   |                 
                 |   |= >io_3.Q                  (S_3) =|   |                 
                 |   |= >io_0                           |   |                 
                 |   |= >io_3                           | 15|= io_3           
                 |   |= >S_2.CMB                        |   |                 
                 |   |= >io_z.Q           not used:220 *|   |                 
                 |   |= >MODULE_1_g1..                  |   |                 
                 |   |> not used:96                     | 16|* not used       
                 |   |= >count_1.Q                      |   |                 
                 |   |> not used:98       not used:222 *|   |                 
                 |   |= >io_0.Q                         |   |                 
                 |   |= >MODULE_5_g1..                  | 17|= io_2           
                 |   |= >stateSBV_2.Q                   |   |                 
                 |   |> not used:102            (S_10) =|   |                 
                 |   |> not used:103                    |   |                 
                 |   |> not used:104                    | 18|= count_3        
                 |   |= >stateSBV_1.Q                   |   |                 
                 |   |= >button_1         not used:226 *|   |                 
                 |   |> not used:107                    |   |                 
                 |   |= >io_1.Q                         | 19|= io_1           
                 |   |= >s_0                            |   |                 
                 |   |= >io_2.Q           not used:228 *|   |                 
                 |   |= >stateSBV_3.Q                   |   |                 
                 |   |> not used:112                    | 20|= io_0           
                 |   |= >count_2.Q                      |   |                 
                 |   |> not used:114      not used:230 *|   |                 
                 |   |= >button_0                       |   |                 
                 |   |> not used:116                    | 21|= (io_z)         
                 |   |> not used:117                    |   |                 
                 |   |= >stateSBV_0.Q            (S_4) =|   |                 
                 |   |> not used:119                    |   |                 
                 |   |= >count_0.Q                      |   |                 
                 |   |= >n_we.Q                         |   |                 
                 |   |= >io_2                           |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    7  |    8  |
                 | Buried Macrocells  |    3  |    8  |
                 | PIM Input Connects |   28  |   36  |
                 ______________________________________
                                          38  /   52   = 73  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

LOGIC BLOCK C PLACEMENT   (23:39:27)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |addr_0
XXXXXXXXXX++++++................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2 |addr_1
..........XXXX++XX++XX++XX......................................................
| 3 |(stateSBV_0)
..............XX++XX++XX++XXXX..................................................
| 4 |count_0
..................++++++++++++XX++..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6 |count_2
..........................++++++XX++++++++......................................
| 7 |UNUSED
..............................++++++++++++++++..................................
| 8 |n_oe
..................................XXXX++++++++++++..............................
| 9 |(stateSBV_3)
......................................XXXXXXXXXXXXX+XX..........................
|10 |UNUSED
..........................................++++++++++++++++......................
|11 |(stateSBV_2)
..............................................+++++X++XXXXXXXX..................
|12 |UNUSED
..................................................++++++++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14 |count_1
..........................................................++++XX++++++++++......
|15 |(S_2)
................................................................XXXXXXXXXXXXXXXX
________________________________________________________________________________

Total count of outputs placed        =  10 
Total count of unique Product Terms  =  80 
Total Product Terms to be assigned   =  80 
Max Product Terms used / available   =  80 /  80   = 100.0  %


Control Signals for Logic Block C
---------------------------------
CLK pin  13 : clk
CLK pin  35 : <not used>
PRESET      : GND
RESET       : GND
OE 0        : <not used>
OE 1        : <not used>
OE 2        : <not used>
OE 3        : <not used>



                              Logic Block C
                 ____________________________________________
                 |   |= >S_6.CMB                        |   |                 
                 |   |= >s_1                            |   |                 
                 |   |= >button_2                       |   |                 
                 |   |= >n_oe.Q                         |   |                 
                 |   |= >S_9.CMB                        | 24|= addr_0         
                 |   |= >count_3.Q                      |   |                 
                 |   |= >S_8.CMB          not used:234 *|   |                 
                 |   |= >count_0.Q                      |   |                 
                 |   |= >io_3                           | 25|= addr_1         
                 |   |= >stateSBV_2.Q                   |   |                 
                 |   |> not used:133      (stateSBV_0) =|   |                 
                 |   |= >s_0                            |   |                 
                 |   |= >addr_0.Q                       | 26|= count_0        
                 |   |= >count_1.Q                      |   |                 
                 |   |> not used:137      not used:238 *|   |                 
                 |   |= >reset                          |   |                 
                 |   |= >MODULE_5_g1..                  | 27|= count_2        
                 |   |= >button_0                       |   |                 
                 |   |= >stateSBV_4.Q     not used:240 *|   |                 
                 |   |> not used:142                    |   |                 
                 |   |> not used:143                    | 28|= n_oe           
                 |   |= >stateSBV_1.Q                   |   |                 
                 |   |= >button_1         (stateSBV_3) =|   |                 
                 |   |= >MODULE_1_g1..                  |   |                 
                 |   |= >S_5.CMB                        | 29|* not used       
                 |   |= >S_7.CMB                        |   |                 
                 |   |> not used:149      (stateSBV_2) =|   |                 
                 |   |= >stateSBV_3.Q                   |   |                 
                 |   |> not used:151                    | 30|* not used       
                 |   |= >count_2.Q                      |   |                 
                 |   |= >S_4.CMB          not used:246 *|   |                 
                 |   |> not used:154                    |   |                 
                 |   |= >addr_1.Q                       | 31|= count_1        
                 |   |> not used:156                    |   |                 
                 |   |= >stateSBV_0.Q            (S_2) =|   |                 
                 |   |> not used:158                    |   |                 
                 |   |> not used:159                    |   |                 
                 |   |> not used:160                    |   |                 
                 |   |= >io_2                           |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    6  |    8  |
                 | Buried Macrocells  |    4  |    8  |
                 | PIM Input Connects |   28  |   36  |
                 ______________________________________
                                          38  /   52   = 73  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

LOGIC BLOCK D PLACEMENT   (23:39:33)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |product_1
XXXXXXXXXXX+XX++................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2 |product_0
..........+X++XXXXXXXXXXXX......................................................
| 3 |UNUSED
..............++++++++++++++++..................................................
| 4 |(stateSBV_1)
..................++++++++XXXXX+XX..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6 |UNUSED
..........................++++++++++++++++......................................
| 7 |UNUSED
..............................++++++++++++++++..................................
| 8 |product_2
..................................XXXXXXXXXXXXX+++..............................
| 9 |(stateSBV_4)
......................................++++++++++XX++++..........................
|10 |UNUSED
..........................................++++++++++++++++......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12 |product_3
..................................................XXXXXXXXXXXXX+++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14 |UNUSED
..........................................................++++++++++++++++......
|15 |(S_6)
................................................................XXXXXXXXXXXXXXXX
________________________________________________________________________________

Total count of outputs placed        =  7 
Total count of unique Product Terms  =  77 
Total Product Terms to be assigned   =  77 
Max Product Terms used / available   =  77 /  80   = 96.26 %


Control Signals for Logic Block D
---------------------------------
CLK pin  13 : clk
CLK pin  35 : <not used>
PRESET      : GND
RESET       : GND
OE 0        : <not used>
OE 1        : <not used>
OE 2        : <not used>
OE 3        : <not used>



                              Logic Block D
                 ____________________________________________
                 |   |= >io_3                           |   |                 
                 |   |= >MODULE_1_g1..                  |   |                 
                 |   |= >io_1                           |   |                 
                 |   |> not used:165                    |   |                 
                 |   |= >product_3.Q                    | 36|= product_1      
                 |   |= >S_11.CMB                       |   |                 
                 |   |= >io_0             not used:250 *|   |                 
                 |   |= >stateSBV_0.Q                   |   |                 
                 |   |= >s_0                            | 37|= product_0      
                 |   |= >S_10.CMB                       |   |                 
                 |   |= >product_0.Q      not used:252 *|   |                 
                 |   |= >s_1                            |   |                 
                 |   |= >button_2                       | 38|= (stateSBV_1)   
                 |   |= >button_1                       |   |                 
                 |   |= >stateSBV_3.Q     not used:254 *|   |                 
                 |   |> not used:177                    |   |                 
                 |   |= >stateSBV_4.Q                   | 39|* not used       
                 |   |= >count_0.Q                      |   |                 
                 |   |= >stateSBV_2.Q     not used:256 *|   |                 
                 |   |= >stateSBV_1.Q                   |   |                 
                 |   |> not used:182                    | 40|= product_2      
                 |   |= >count_1.Q                      |   |                 
                 |   |= >count_3.Q        (stateSBV_4) =|   |                 
                 |   |> not used:185                    |   |                 
                 |   |> not used:186                    | 41|* not used       
                 |   |= >product_1.Q                    |   |                 
                 |   |= >reset            not used:260 *|   |                 
                 |   |> not used:189                    |   |                 
                 |   |= >button_0                       | 42|= product_3      
                 |   |> not used:191                    |   |                 
                 |   |> not used:192      not used:262 *|   |                 
                 |   |> not used:193                    |   |                 
                 |   |= >product_2.Q                    | 43|* not used       
                 |   |> not used:195                    |   |                 
                 |   |> not used:196             (S_6) =|   |                 
                 |   |> not used:197                    |   |                 
                 |   |> not used:198                    |   |                 
                 |   |> not used:199                    |   |                 
                 |   |> not used:200                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    5  |    8  |
                 | Buried Macrocells  |    2  |    8  |
                 | PIM Input Connects |   24  |   36  |
                 ______________________________________
                                          31  /   52   = 59  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (23:39:38)


Device:  c372i
Package: CY7C372I-66JC

                  1  :  GND
                  2  :  (S_8)
                  3  :  s_0
                  4  :  reset
                  5  :  (MODULE_1_g1_a0_gx_u0_gne_0_c3_u1)
                  6  :  (S_11)
                  7  :  Not Used
                  8  :  Not Used
                  9  :  Not Used
                 10  :  button_0
                 11  :  VPP
                 12  :  GND
                 13  :  clk
                 14  :  n_we
                 15  :  io_3
                 16  :  Not Used
                 17  :  io_2
                 18  :  count_3
                 19  :  io_1
                 20  :  io_0
                 21  :  (io_z)
                 22  :  VCC
                 23  :  GND
                 24  :  addr_0
                 25  :  addr_1
                 26  :  count_0
                 27  :  count_2
                 28  :  n_oe
                 29  :  Not Used
                 30  :  Not Used
                 31  :  count_1
                 32  :  button_1
                 33  :  button_2
                 34  :  GND
                 35  :  s_1
                 36  :  product_1
                 37  :  product_0
                 38  :  (stateSBV_1)
                 39  :  Not Used
                 40  :  product_2
                 41  :  Not Used
                 42  :  product_3
                 43  :  Not Used
                 44  :  VCC


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    3  |    3  |
                 | Clock/Inputs       |    2  |    2  |
                 | I/O Macrocells     |   23  |   32  |
                 | Buried Macrocells  |   13  |   32  |
                 | PIM Input Connects |   98  |  156  |
                 ______________________________________
                                         139  /  225   = 61  %



                                      Required     Max (Available)
          CLOCK/LATCH ENABLE signals     1            2
          Input REG/LATCH signals        0           36
          Input PIN signals              4            4
          Input PINs using I/O cells     2            2
          Output PIN signals            21           30


          Total PIN signals             28           37
          Macrocells Used               34           64
          Unique Product Terms         284          320



----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

PRESET/RESET AND OUTPUT ENABLE COMBINATIONS

PRESET: NONE-COMBINATORIAL
RESET : NONE-COMBINATORIAL
Total unique inputs =  20 
count of combinatorial equations =  12 
==>OE: GND or VCC
   count of OE equations =  12 


PRESET: GND
RESET : GND
Used by Logic Blocks: BCD
Total unique inputs =  40 
count of registered equations =  22 
==>OE: GND or VCC
   count of OE equations =  18 
==>OE: /io_z.Q 
   Used by Logic Blocks: B
   count of OE equations =  4 

----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

TIMING PATH ANALYSIS       (23:39:39) using Package: CY7C372I-66JC

Messages:

----------------------------------------------------------------------------
Signal Name | Delay Type  |   tmax   | Path Description
----------------------------------------------------------------------------
reg::n_we[14]
inp::reset
              tS              10.0 ns    1 pass
inp::stateSBV_0.Q
              tSCS            15.0 ns    1 pass
out::n_we
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::io_3[15]
inp::reset
              tS              10.0 ns    1 pass
inp::stateSBV_0.Q
              tSCS            15.0 ns    1 pass
out::io_3
              tCO             10.0 ns  
inp::io_z.Q
              tER             28.0 ns    1 pass
----------------------------------------------------------------------------
reg::io_2[17]
inp::reset
              tS              10.0 ns    1 pass
inp::stateSBV_0.Q
              tSCS            15.0 ns    1 pass
out::io_2
              tCO             10.0 ns  
inp::io_z.Q
              tER             28.0 ns    1 pass
----------------------------------------------------------------------------
reg::count_3[18]
inp::io_0
---->MODULE_5_g1_a0_g0_u0_gs_g1_us0
---->S_3
              tS              40.0 ns    3 passes
inp::count_1.Q
---->MODULE_5_g1_a0_g0_u0_gs_g1_us0
---->S_3
              tSCS            45.0 ns    3 passes
out::count_3
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::io_1[19]
inp::reset
              tS              10.0 ns    1 pass
inp::stateSBV_1.Q
              tSCS            15.0 ns    1 pass
out::io_1
              tCO             10.0 ns  
inp::io_z.Q
              tER             28.0 ns    1 pass
----------------------------------------------------------------------------
reg::io_0[20]
inp::reset
              tS              10.0 ns    1 pass
inp::stateSBV_0.Q
              tSCS            15.0 ns    1 pass
out::io_0
              tCO             10.0 ns  
inp::io_z.Q
              tER             28.0 ns    1 pass
----------------------------------------------------------------------------
reg::(io_z)[21]
inp::reset
              tS              10.0 ns    1 pass
inp::stateSBV_0.Q
              tSCS            15.0 ns    1 pass
out::io_z
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::addr_0[24]
inp::reset
              tS              10.0 ns    1 pass
inp::stateSBV_0.Q
              tSCS            15.0 ns    1 pass
out::addr_0
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::addr_1[25]
inp::reset
              tS              10.0 ns    1 pass
inp::stateSBV_0.Q
              tSCS            15.0 ns    1 pass
out::addr_1
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::count_0[26]
inp::io_0
---->MODULE_1_g1_a0_gx_u0_gne_0_c3_u1
---->S_8
              tS              40.0 ns    3 passes
inp::count_1.Q
---->MODULE_1_g1_a0_gx_u0_gne_0_c3_u1
---->S_8
              tSCS            45.0 ns    3 passes
out::count_0
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::count_2[27]
inp::io_0
---->MODULE_1_g1_a0_gx_u0_gne_0_c3_u1
---->S_4
              tS              40.0 ns    3 passes
inp::count_1.Q
---->MODULE_1_g1_a0_gx_u0_gne_0_c3_u1
---->S_4
              tSCS            45.0 ns    3 passes
out::count_2
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::n_oe[28]
inp::reset
              tS              10.0 ns    1 pass
inp::stateSBV_0.Q
              tSCS            15.0 ns    1 pass
out::n_oe
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::count_1[31]
inp::io_0
---->MODULE_1_g1_a0_gx_u0_gne_0_c3_u1
---->S_6
              tS              40.0 ns    3 passes
inp::count_1.Q
---->MODULE_1_g1_a0_gx_u0_gne_0_c3_u1
---->S_6
              tSCS            45.0 ns    3 passes
out::count_1
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::product_1[36]
inp::io_0
---->MODULE_1_g1_a0_gx_u0_gne_0_c3_u1
              tS              25.0 ns    2 passes
inp::count_1.Q
---->MODULE_1_g1_a0_gx_u0_gne_0_c3_u1
              tSCS            30.0 ns    2 passes
out::product_1
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::product_0[37]
inp::io_0
---->MODULE_1_g1_a0_gx_u0_gne_0_c3_u1
              tS              25.0 ns    2 passes
inp::count_1.Q
---->MODULE_1_g1_a0_gx_u0_gne_0_c3_u1
              tSCS            30.0 ns    2 passes
out::product_0
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::(stateSBV_1)[38]
inp::reset
              tS              10.0 ns    1 pass
inp::stateSBV_1.Q
              tSCS            15.0 ns    1 pass
out::stateSBV_1
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::product_2[40]
inp::io_0
---->MODULE_1_g1_a0_gx_u0_gne_0_c3_u1
              tS              25.0 ns    2 passes
inp::count_1.Q
---->MODULE_1_g1_a0_gx_u0_gne_0_c3_u1
              tSCS            30.0 ns    2 passes
out::product_2
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::product_3[42]
inp::io_0
---->MODULE_1_g1_a0_gx_u0_gne_0_c3_u1
              tS              25.0 ns    2 passes
inp::count_1.Q
---->MODULE_1_g1_a0_gx_u0_gne_0_c3_u1
              tSCS            30.0 ns    2 passes
out::product_3
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::(stateSBV_0)[236]
inp::reset
              tS              10.0 ns    1 pass
inp::stateSBV_0.Q
              tSCS            15.0 ns    1 pass
out::stateSBV_0
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::(stateSBV_3)[242]
inp::reset
              tS              10.0 ns    1 pass
inp::stateSBV_1.Q
              tSCS            15.0 ns    1 pass
out::stateSBV_3
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::(stateSBV_2)[244]
inp::reset
              tS              10.0 ns    1 pass
inp::stateSBV_0.Q
              tSCS            15.0 ns    1 pass
out::stateSBV_2
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::(stateSBV_4)[258]
inp::reset
---->S_11
              tS              25.0 ns    2 passes
inp::stateSBV_1.Q
---->S_11
              tSCS            30.0 ns    2 passes
out::stateSBV_4
              tCO             10.0 ns  
----------------------------------------------------------------------------

Worst Case Path Summary
-----------------------

                     tS = 40.0 ns for count_3.T
                   tSCS = 45.0 ns for count_3.T
                    tCO = 10.0 ns for n_we.C
                    tER = 28.0 ns for io_3.OE



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

JEDEC ASSEMBLE             (23:39:40)

Messages:
  Information: Processing JEDEC for Logic Block 1.
  Information: Processing JEDEC for Logic Block 2.
  Information: Processing JEDEC for Logic Block 3.
  Information: Processing JEDEC for Logic Block 4.
  Information: JEDEC output file 'mainfsm.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 23:39:52
