
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x95
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|    1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  sync.vhd
Options:    -o2 -ygs -fP -v10 -dc20v8 -pPALCE20V8-7PC sync.vhd
======================================================================

vhdlfe V4 IR x95:  VHDL parser
Tue Mar  9 23:08:30 1999

Library 'work' => directory 'lc20v8'
Linking '/u15c/warp4.3/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/u15c/warp4.3/lib/ieee/work'
Linking '/u15c/warp4.3/lib/ieee/work/stdlogic.vif'.

vhdlfe:  No errors.


tovif V4 IR x95:  High-level synthesis
Tue Mar  9 23:08:37 1999

Linking '/u15c/warp4.3/lib/common/work/cypress.vif'.
Linking '/u15c/warp4.3/lib/ieee/work/stdlogic.vif'.

tovif:  No errors.


topld V4 IR x96:  Synthesis and optimization
Tue Mar  9 23:08:44 1999

Linking '/u15c/warp4.3/lib/common/work/cypress.vif'.
Linking '/u15c/warp4.3/lib/ieee/work/stdlogic.vif'.
State variable 'state' is represented by a Bit_vector (0 to 3).
State encoding (sequential) for 'state' is:
	waiting :=	b"0000";
	go1 :=	b"0001";
	go2 :=	b"0010";
	nickel1 :=	b"0011";
	nickel2 :=	b"0100";
	dime1 :=	b"0101";
	dime2 :=	b"0110";
	quarter1 :=	b"0111";
	quarter2 :=	b"1000";
	lreset1 :=	b"1001";
	lreset2 :=	b"1010";
	greset1 :=	b"1011";
	greset2 :=	b"1100";

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------



------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 0 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

----------------------------------------------------------
Circuit simplification results:

	Expanded 0 signals.
	Turned 0 signals into soft nodes.
	Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 22 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN HEADER INFORMATION  (23:08:54)

Input File(s): sync.pla
Device       : c20v8
Package      : PALCE20V8-7PC
ReportFile   : sync.rpt

Program Controls:
                 None.

Signal Requests:
    GROUP FAST_SLEW ALL

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (23:08:55)

Messages:
  Information: Process virtual 'stateSBV_3D' ... expanded.
  Information: Process virtual 'stateSBV_2D' ... expanded.
  Information: Process virtual 'stateSBV_1D' ... expanded.
  Information: Process virtual 'stateSBV_0D' ... expanded.
  Information: Process virtual 'button_0D' ... expanded.
  Information: Process virtual 'button_1D' ... expanded.
  Information: Process virtual 'button_2D' ... expanded.
  Information: Process virtual 'stateSBV_3' ... converted to NODE.
  Information: Process virtual 'stateSBV_2' ... converted to NODE.
  Information: Process virtual 'stateSBV_1' ... converted to NODE.
  Information: Process virtual 'stateSBV_0' ... converted to NODE.
  Information: Optimizing logic using best output polarity for signals:
         stateSBV_3.D stateSBV_2.D stateSBV_1.D stateSBV_0.D button_0.D
         button_1.D button_2.D

  Information: Selected logic optimization OFF for signals:
         stateSBV_3.C stateSBV_2.C stateSBV_1.C stateSBV_0.C button_0.C
         button_1.C button_2.C



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     11/NOV/97    [v4.02 ] 4 IR x95

LOGIC MINIMIZATION         (23:08:57)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (23:08:59)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN EQUATIONS           (23:09:02)


    button_2.D =
          /reset * /stateSBV_1.Q * /stateSBV_2.Q * stateSBV_3.Q 
        + /reset * stateSBV_0.Q * stateSBV_3.Q 
        + reset * button_2.Q 

    button_2.C =
          clk 

    button_1.D =
          /reset * stateSBV_0.Q * stateSBV_3.Q 
        + /reset * stateSBV_1.Q * stateSBV_3.Q 
        + reset * button_1.Q 

    button_1.C =
          clk 

    button_0.D =
          /reset * stateSBV_2.Q * stateSBV_3.Q 
        + reset * button_0.Q 

    button_0.C =
          clk 

    stateSBV_0.D =
          /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * /go * /nickel * /dime * /quarter * greset 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * /go * /nickel * /dime * /quarter * lreset 
        + /reset * stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * quarter 
        + /reset * stateSBV_1.Q * stateSBV_2.Q * stateSBV_3.Q 
        + /reset * stateSBV_0.Q * stateSBV_1.Q * greset 
        + /reset * stateSBV_0.Q * stateSBV_2.Q * lreset 
        + /reset * stateSBV_0.Q * stateSBV_3.Q 

    stateSBV_0.C =
          clk 

    stateSBV_1.D =
          /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * /go * /nickel * quarter 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * /go * /nickel * dime 
        + /reset * stateSBV_1.Q * stateSBV_2.Q * /stateSBV_3.Q * dime 
        + /reset * /stateSBV_0.Q * stateSBV_1.Q * /stateSBV_2.Q * nickel 
        + /reset * stateSBV_0.Q * stateSBV_1.Q * greset 
        + /reset * /stateSBV_1.Q * stateSBV_2.Q * stateSBV_3.Q 
        + /reset * stateSBV_1.Q * /stateSBV_2.Q * stateSBV_3.Q 

    stateSBV_1.C =
          clk 

    stateSBV_2.D =
          /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * /go * 
          /dime * /lreset * greset 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * /go * 
          /dime * quarter 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * stateSBV_2.Q * 
          /stateSBV_3.Q * go 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * /go * 
          nickel 
        + /reset * stateSBV_1.Q * stateSBV_2.Q * /stateSBV_3.Q * dime 
        + /reset * stateSBV_0.Q * stateSBV_2.Q * /stateSBV_3.Q * lreset 
        + /reset * /stateSBV_2.Q * stateSBV_3.Q 

    stateSBV_2.C =
          clk 

    stateSBV_3.D =
          /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * greset 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * lreset 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * quarter 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * dime 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * nickel 
        + /reset * /stateSBV_0.Q * /stateSBV_1.Q * /stateSBV_2.Q * 
          /stateSBV_3.Q * go 

    stateSBV_3.C =
          clk 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN RULE CHECK          (23:09:02)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (23:09:03)

Messages:
  Information: Checking for duplicate NODE logic.
                 None.


                                 C20V8C
                 __________________________________________
            clk =| 1|                                  |24|* not used       
         greset =| 2|                                  |23|* not used       
         lreset =| 3|                                  |22|* not used       
        quarter =| 4|                                  |21|= button_0       
           dime =| 5|                                  |20|= button_2       
         nickel =| 6|                                  |19|= button_1       
             go =| 7|                                  |18|= (stateSBV_3)   
          reset =| 8|                                  |17|= (stateSBV_0)   
       not used *| 9|                                  |16|= (stateSBV_1)   
       not used *|10|                                  |15|= (stateSBV_2)   
       not used *|11|                                  |14|* not used       
       not used *|12|                                  |13|* Reserved       
                 __________________________________________


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

RESOURCE ALLOCATION        (23:09:03)

  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    7  |   12  |
                 | Clock/Inputs       |    1  |    1  |
                 | Enable/Inputs      |    0  |    1  |
                 | Output Macrocells  |    7  |    8  |
                 ______________________________________
                                          15  /   22   = 68  %


  Information: Output Logic Product Term Utilization.

                  Node#  Output Signal Name  Used   Max
                 ________________________________________
                 | 15  |  stateSBV_2      |   7  |   8  |
                 | 16  |  stateSBV_1      |   7  |   8  |
                 | 17  |  stateSBV_0      |   7  |   8  |
                 | 18  |  stateSBV_3      |   6  |   8  |
                 | 19  |  button_1        |   3  |   8  |
                 | 20  |  button_2        |   3  |   8  |
                 | 21  |  button_0        |   2  |   8  |
                 | 22  |  Unused          |   0  |   8  |
                 ________________________________________
                                             35  /  64   = 54  %


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

JEDEC ASSEMBLE             (23:09:03)

Messages:
  Information: Output file 'sync.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 23:09:04
