
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x95
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|    1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  accum.vhd
Options:    -e10 -w100 -o2 -yga -fP -v1 -dc22v10 -pPALCE22V10-25PC/PI accum.vhd
======================================================================

vhdlfe V4 IR x95:  VHDL parser
Mon Mar 29 18:27:46 1999

Library 'work' => directory 'lc22v10'
Linking '/fs/u15c/hpwarp4.3/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/fs/u15c/hpwarp4.3/lib/ieee/work'
Linking '/fs/u15c/hpwarp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/mod_genu.vif'.
accum.vhd (line 25, col 36):  Note: Substituting module 'add_vv_us' for '+'.
accum.vhd (line 25, col 50):  Note: Substituting module 'add_vv_us' for '+'.

vhdlfe:  No errors.


tovif V4 IR x95:  High-level synthesis
Mon Mar 29 18:27:53 1999

Linking '/fs/u15c/hpwarp4.3/lib/common/work/cypress.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/mod_genu.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/madd_sub.vif'.

tovif:  No errors.


topld V4 IR x96:  Synthesis and optimization
Mon Mar 29 18:28:05 1999

Linking '/fs/u15c/hpwarp4.3/lib/common/work/cypress.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/mod_genu.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/common/stdlogic/madd_sub.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/lc22v10/stdlogic/c22v10.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------
    User names
	sum_4


Deleted 1 User equation or component.
Deleted 1 Synthesized equation or component.

------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 27 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------
Note:  Virtual signal MODIN3_3 with ( cost: 72 or cost_inv: 12)  > 30 or with size: 12 > 58 has been made a (soft) node.
Note:  Virtual signal MODIN3_2 with ( cost: 64 or cost_inv: 4)  > 30 or with size: 4 > 58 has been made a (soft) node.
Note:  Virtual signal MODIN3_1 with ( cost: 48 or cost_inv: 6)  > 30 or with size: 6 > 58 has been made a (soft) node.

----------------------------------------------------------
Circuit simplification results:

	Expanded 6 signals.
	Turned 3 signals into soft nodes.
	Maximum expansion cost was set at 1.
----------------------------------------------------------
Created 75 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN HEADER INFORMATION  (18:28:13)

Input File(s): accum.pla
Device       : C22V10
Package      : PALCE22V10-25PC/PI
ReportFile   : accum.rpt

Program Controls:
                 None.

Signal Requests:
    GROUP FAST_SLEW ALL
    GROUP SOFT MODIN3_1 MODIN3_2 MODIN3_3 

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (18:28:13)

Messages:
  Information: Process virtual 'MODIN3_1' ... converted to NODE.
 ... converted to NODE.
 ... converted to NODE.
  Information: Process virtual 'MODULE_2_g1_a0_g0_u0_ci_2' ... expanded.
  Information: Process virtual 'MODULE_1_g1_a0_g0_u0_ci_2' ... expanded.
  Information: Process virtual 'reg_0D' ... expanded.
  Information: Process virtual 'reg_1D' ... expanded.
  Information: Process virtual 'reg_2D' ... expanded.
  Information: Process virtual 'reg_3D' ... expanded.
  Information: Process virtual 'MODULE_2_g1_a0_g0_u0_c_0' ... expanded.
  Information: Process virtual 'MODULE_1_g1_a0_g0_u0_c_0' ... expanded.
  Information: Optimizing logic using best output polarity for signals:
         reg_3.D reg_2.D reg_1.D reg_0.D MODIN3_2 MODIN3_3
         MODULE_2_g1_a0_g0_u0_ga_g1_ua0 MODIN3_1
         MODULE_1_g1_a0_g0_u0_ga_g1_ua0

  Information: Selected logic optimization OFF for signals:
         reg_3.C reg_2.C reg_1.C reg_0.C



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     11/NOV/97    [v4.02 ] 4 IR x95

LOGIC MINIMIZATION         (18:28:14)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (18:28:15)

Messages:
  Information: Optimizing Banked Preset/Reset requirements.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN EQUATIONS           (18:28:15)


    reg_3.D =
          MODULE_2_g1_a0_g0_u0_ga_g1_ua0 * /clr * ld * /MODIN3_3 * 
          MODIN3_2 
        + /clr * ld * MODIN3_3 * /MODIN3_2 
        + /MODULE_2_g1_a0_g0_u0_ga_g1_ua0 * /clr * ld * MODIN3_3 
        + reg_3.Q * /clr * /ld 

    reg_3.AR =
          GND

    reg_3.SP =
          GND

    reg_3.C =
          clk 

    reg_2.D =
          MODULE_2_g1_a0_g0_u0_ga_g1_ua0 * /clr * ld * /MODIN3_2 
        + /MODULE_2_g1_a0_g0_u0_ga_g1_ua0 * /clr * ld * MODIN3_2 
        + reg_2.Q * /clr * /ld 

    reg_2.AR =
          GND

    reg_2.SP =
          GND

    reg_2.C =
          clk 

    reg_1.D =
          input_0 * /reg_0.Q * carry_in * /MODIN3_1 * /clr * ld 
        + /input_0 * reg_0.Q * carry_in * /MODIN3_1 * /clr * ld 
        + /input_0 * /reg_0.Q * MODIN3_1 * /clr * ld 
        + input_0 * reg_0.Q * MODIN3_1 * /clr * ld 
        + /carry_in * MODIN3_1 * /clr * ld 
        + reg_1.Q * /clr * /ld 

    reg_1.AR =
          GND

    reg_1.SP =
          GND

    reg_1.C =
          clk 

    reg_0.D =
          input_0 * /reg_0.Q * /carry_in * /clr * ld 
        + /input_0 * /reg_0.Q * carry_in * /clr * ld 
        + /input_0 * reg_0.Q * /carry_in * /clr 
        + input_0 * reg_0.Q * carry_in * /clr 
        + reg_0.Q * /clr * /ld 

    reg_0.AR =
          GND

    reg_0.SP =
          GND

    reg_0.C =
          clk 

    MODULE_1_g1_a0_g0_u0_ga_g1_ua0 =
          input_0 * reg_1.Q * reg_0.Q 
        + input_0 * reg_0.Q * input_1 
        + reg_1.Q * input_1 

    MODIN3_2 =
          /reg_2.Q * input_2 * /MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + reg_2.Q * /input_2 * /MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + /reg_2.Q * /input_2 * MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + reg_2.Q * input_2 * MODULE_1_g1_a0_g0_u0_ga_g1_ua0 

    MODIN3_3 =
          /reg_3.Q * /reg_2.Q * input_3 * /MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + reg_3.Q * /reg_2.Q * /input_3 * /MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + /reg_3.Q * input_3 * /input_2 * /MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + reg_3.Q * /input_3 * /input_2 * /MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + /reg_3.Q * reg_2.Q * /input_3 * MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + reg_3.Q * reg_2.Q * input_3 * MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + /reg_3.Q * /input_3 * input_2 * MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + reg_3.Q * input_3 * input_2 * MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + /reg_3.Q * /reg_2.Q * input_3 * /input_2 
        + reg_3.Q * /reg_2.Q * /input_3 * /input_2 
        + /reg_3.Q * reg_2.Q * /input_3 * input_2 
        + reg_3.Q * reg_2.Q * input_3 * input_2 

    MODULE_2_g1_a0_g0_u0_ga_g1_ua0 =
          input_0 * /reg_0.Q * carry_in * MODIN3_1 
        + /input_0 * reg_0.Q * carry_in * MODIN3_1 

    MODIN3_1 =
          input_0 * /reg_1.Q * reg_0.Q * /input_1 
        + input_0 * reg_1.Q * reg_0.Q * input_1 
        + /reg_1.Q * /reg_0.Q * input_1 
        + reg_1.Q * /reg_0.Q * /input_1 
        + /input_0 * /reg_1.Q * input_1 
        + /input_0 * reg_1.Q * /input_1 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN RULE CHECK          (18:28:16)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (18:28:16)

Messages:
  Information: Checking for duplicate NODE logic.
                 None.


                                 C22V10
                 __________________________________________
            clk =| 1|                                  |24|* not used       
            clr =| 2|                                  |23|= (MODIN3_2)     
             ld =| 3|                                  |22|= (MODULE_2_g1.. 
       carry_in =| 4|                                  |21|* not used       
        input_0 =| 5|                                  |20|= reg_0          
        input_1 =| 6|                                  |19|= reg_1          
        input_2 =| 7|                                  |18|= reg_2          
        input_3 =| 8|                                  |17|= reg_3          
       not used *| 9|                                  |16|= (MODIN3_3)     
       not used *|10|                                  |15|= (MODULE_1_g1.. 
       not used *|11|                                  |14|= (MODIN3_1)     
       not used *|12|                                  |13|* not used       
                 __________________________________________


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

RESOURCE ALLOCATION        (18:28:16)

  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    7  |   11  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |    9  |   10  |
                 ______________________________________
                                          17  /   22   = 77  %


  Information: Output Logic Product Term Utilization.

                  Node#  Output Signal Name  Used   Max
                 ________________________________________
                 | 14  |  MODIN3_1        |   6  |   8  |
                 | 15  |  MODULE_1_g1_..  |   3  |  10  |
                 | 16  |  MODIN3_3        |  12  |  12  |
                 | 17  |  reg_3           |   4  |  14  |
                 | 18  |  reg_2           |   3  |  16  |
                 | 19  |  reg_1           |   6  |  16  |
                 | 20  |  reg_0           |   5  |  14  |
                 | 21  |  Unused          |   0  |  12  |
                 | 22  |  MODULE_2_g1_..  |   2  |  10  |
                 | 23  |  MODIN3_2        |   4  |   8  |
                 | 25  |  Unused          |   0  |   1  |
                 ________________________________________
                                             45  / 121   = 37  %


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

JEDEC ASSEMBLE             (18:28:16)

Messages:
  Information: Output file 'accum.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 18:28:16
