
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x95
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|    1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  alogic.vhd
Options:    -o2 -ygs -fP -v10 -dc22v10 -pPALCE22V10-25PC/PI alogic.vhd
======================================================================

vhdlfe V4 IR x95:  VHDL parser
Mon Mar 29 18:26:23 1999

Library 'work' => directory 'lc22v10'
Linking '/fs/u15c/hpwarp4.3/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/fs/u15c/hpwarp4.3/lib/ieee/work'
Linking '/fs/u15c/hpwarp4.3/lib/ieee/work/stdlogic.vif'.

vhdlfe:  No errors.


tovif V4 IR x95:  High-level synthesis
Mon Mar 29 18:26:25 1999

Linking '/fs/u15c/hpwarp4.3/lib/common/work/cypress.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/ieee/work/stdlogic.vif'.

tovif:  No errors.


topld V4 IR x96:  Synthesis and optimization
Mon Mar 29 18:26:28 1999

Linking '/fs/u15c/hpwarp4.3/lib/common/work/cypress.vif'.
Linking '/fs/u15c/hpwarp4.3/lib/ieee/work/stdlogic.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------



------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 0 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

----------------------------------------------------------
Circuit simplification results:

	Expanded 0 signals.
	Turned 0 signals into soft nodes.
	Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 28 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN HEADER INFORMATION  (18:26:31)

Input File(s): alogic.pla
Device       : C22V10
Package      : PALCE22V10-25PC/PI
ReportFile   : alogic.rpt

Program Controls:
                 None.

Signal Requests:
    GROUP FAST_SLEW ALL

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (18:26:31)

Messages:
  Information: Process virtual 'dac_n_ceD' ... expanded.
  Information: Process virtual 'accum_clrD' ... expanded.
  Information: Process virtual 'accum_ldD' ... expanded.
  Information: Process virtual 'ram_n_oeD' ... expanded.
  Information: Process virtual 'ram_n_weD' ... expanded.
  Information: Process virtual 'su_shiftbufD' ... expanded.
  Information: Process virtual 'su_swapbuffD' ... expanded.
  Information: Process virtual 'su_clearshiftD' ... expanded.
  Information: Process virtual 'su_countD' ... expanded.
  Information: Process virtual 'adc_rwD' ... expanded.
  Information: Optimizing logic using best output polarity for signals:
         adc_rw.D su_count.D su_clearshift.D su_swapbuff.D su_shiftbuf.D
         ram_n_we.D ram_n_oe.D accum_ld.D accum_clr.D dac_n_ce.D

  Information: Selected logic optimization OFF for signals:
         adc_rw.C su_count.C su_clearshift.C su_swapbuff.C su_shiftbuf.C
         ram_n_we.C ram_n_oe.C accum_ld.C accum_clr.C dac_n_ce.C



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     11/NOV/97    [v4.02 ] 4 IR x95

LOGIC MINIMIZATION         (18:26:32)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (18:26:32)

Messages:
  Information: Optimizing Banked Preset/Reset requirements.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN EQUATIONS           (18:26:33)


    adc_rw.D =
          n_reset * assert_in * level * /value_3 * /value_2 * /value_1 * 
          value_0 
        + n_reset * /value_0 * adc_rw.Q 
        + n_reset * value_1 * adc_rw.Q 
        + n_reset * value_2 * adc_rw.Q 
        + n_reset * value_3 * adc_rw.Q 
        + n_reset * /assert_in * adc_rw.Q 

    adc_rw.AR =
          GND

    adc_rw.SP =
          GND

    adc_rw.C =
          clk 

    su_count.D =
          n_reset * assert_in * level * /value_3 * /value_2 * value_1 * 
          /value_0 
        + n_reset * value_0 * su_count.Q 
        + n_reset * /value_1 * su_count.Q 
        + n_reset * value_2 * su_count.Q 
        + n_reset * value_3 * su_count.Q 
        + n_reset * /assert_in * su_count.Q 

    su_count.AR =
          GND

    su_count.SP =
          GND

    su_count.C =
          clk 

    su_clearshift.D =
          n_reset * assert_in * level * /value_3 * value_2 * /value_1 * 
          /value_0 
        + n_reset * value_0 * su_clearshift.Q 
        + n_reset * value_1 * su_clearshift.Q 
        + n_reset * /value_2 * su_clearshift.Q 
        + n_reset * value_3 * su_clearshift.Q 
        + n_reset * /assert_in * su_clearshift.Q 

    su_clearshift.AR =
          GND

    su_clearshift.SP =
          GND

    su_clearshift.C =
          clk 

    su_swapbuff.D =
          n_reset * assert_in * level * /value_3 * value_2 * /value_1 * 
          value_0 
        + n_reset * /value_0 * su_swapbuff.Q 
        + n_reset * value_1 * su_swapbuff.Q 
        + n_reset * /value_2 * su_swapbuff.Q 
        + n_reset * value_3 * su_swapbuff.Q 
        + n_reset * /assert_in * su_swapbuff.Q 

    su_swapbuff.AR =
          GND

    su_swapbuff.SP =
          GND

    su_swapbuff.C =
          clk 

    su_shiftbuf.D =
          n_reset * assert_in * level * /value_3 * value_2 * value_1 * 
          /value_0 
        + n_reset * value_0 * su_shiftbuf.Q 
        + n_reset * /value_1 * su_shiftbuf.Q 
        + n_reset * /value_2 * su_shiftbuf.Q 
        + n_reset * value_3 * su_shiftbuf.Q 
        + n_reset * /assert_in * su_shiftbuf.Q 

    su_shiftbuf.AR =
          GND

    su_shiftbuf.SP =
          GND

    su_shiftbuf.C =
          clk 

    /ram_n_we.D =
          n_reset * assert_in * /level * /value_3 * value_2 * value_1 * 
          value_0 
        + n_reset * /value_0 * /ram_n_we.Q 
        + n_reset * /value_1 * /ram_n_we.Q 
        + n_reset * /value_2 * /ram_n_we.Q 
        + n_reset * value_3 * /ram_n_we.Q 
        + n_reset * /assert_in * /ram_n_we.Q 

    ram_n_we.AR =
          GND

    ram_n_we.SP =
          GND

    ram_n_we.C =
          clk 

    /ram_n_oe.D =
          n_reset * assert_in * /level * value_3 * /value_2 * /value_1 * 
          /value_0 
        + n_reset * value_0 * /ram_n_oe.Q 
        + n_reset * value_1 * /ram_n_oe.Q 
        + n_reset * value_2 * /ram_n_oe.Q 
        + n_reset * /value_3 * /ram_n_oe.Q 
        + n_reset * /assert_in * /ram_n_oe.Q 

    ram_n_oe.AR =
          GND

    ram_n_oe.SP =
          GND

    ram_n_oe.C =
          clk 

    accum_ld.D =
          n_reset * assert_in * level * value_3 * /value_2 * /value_1 * 
          value_0 
        + n_reset * /value_0 * accum_ld.Q 
        + n_reset * value_1 * accum_ld.Q 
        + n_reset * value_2 * accum_ld.Q 
        + n_reset * /value_3 * accum_ld.Q 
        + n_reset * /assert_in * accum_ld.Q 

    accum_ld.AR =
          GND

    accum_ld.SP =
          GND

    accum_ld.C =
          clk 

    accum_clr.D =
          n_reset * assert_in * level * value_3 * /value_2 * value_1 * 
          /value_0 
        + n_reset * value_0 * accum_clr.Q 
        + n_reset * /value_1 * accum_clr.Q 
        + n_reset * value_2 * accum_clr.Q 
        + n_reset * /value_3 * accum_clr.Q 
        + n_reset * /assert_in * accum_clr.Q 

    accum_clr.AR =
          GND

    accum_clr.SP =
          GND

    accum_clr.C =
          clk 

    /dac_n_ce.D =
          n_reset * assert_in * /level * value_3 * /value_2 * value_1 * 
          value_0 
        + n_reset * /value_0 * /dac_n_ce.Q 
        + n_reset * /value_1 * /dac_n_ce.Q 
        + n_reset * value_2 * /dac_n_ce.Q 
        + n_reset * /value_3 * /dac_n_ce.Q 
        + n_reset * /assert_in * /dac_n_ce.Q 

    dac_n_ce.AR =
          GND

    dac_n_ce.SP =
          GND

    dac_n_ce.C =
          clk 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN RULE CHECK          (18:26:34)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (18:26:34)

Messages:
  Information: All signals pre-placed in user design.


                                 C22V10
                 __________________________________________
            clk =| 1|                                  |24|* not used       
        n_reset =| 2|                                  |23|= dac_n_ce       
       not used *| 3|                                  |22|= accum_clr      
        value_0 =| 4|                                  |21|= accum_ld       
        value_1 =| 5|                                  |20|= ram_n_oe       
        value_2 =| 6|                                  |19|= ram_n_we       
        value_3 =| 7|                                  |18|= su_shiftbuf    
       not used *| 8|                                  |17|= su_swapbuff    
          level =| 9|                                  |16|= su_clearshift  
      assert_in =|10|                                  |15|= su_count       
       not used *|11|                                  |14|= adc_rw         
       not used *|12|                                  |13|* not used       
                 __________________________________________


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
  Information: Checking for duplicate NODE logic.
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

RESOURCE ALLOCATION        (18:26:34)

  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    7  |   11  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |   10  |   10  |
                 ______________________________________
                                          18  /   22   = 81  %


  Information: Output Logic Product Term Utilization.

                  Node#  Output Signal Name  Used   Max
                 ________________________________________
                 | 14  |  adc_rw          |   6  |   8  |
                 | 15  |  su_count        |   6  |  10  |
                 | 16  |  su_clearshift   |   6  |  12  |
                 | 17  |  su_swapbuff     |   6  |  14  |
                 | 18  |  su_shiftbuf     |   6  |  16  |
                 | 19  |  ram_n_we        |   6  |  16  |
                 | 20  |  ram_n_oe        |   6  |  14  |
                 | 21  |  accum_ld        |   6  |  12  |
                 | 22  |  accum_clr       |   6  |  10  |
                 | 23  |  dac_n_ce        |   6  |   8  |
                 | 25  |  Unused          |   0  |   1  |
                 ________________________________________
                                             60  / 121   = 49  %


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

JEDEC ASSEMBLE             (18:26:34)

Messages:
  Information: Output file 'alogic.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 18:26:34
