
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x95
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|    1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  sync.vhd
Options:    -m -e10 -w100 -o2 -ygs -fP -v10 -dc20v8 -pPALCE20V8-7PC sync.vhd
======================================================================

vhdlfe V4 IR x95:  VHDL parser
Mon Mar 29 03:19:12 1999

Library 'work' => directory 'lc20v8'
Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/mit/6.111/warp4.3/lib/ieee/work'
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.

vhdlfe:  No errors.


tovif V4 IR x95:  High-level synthesis
Mon Mar 29 03:19:13 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.

tovif:  No errors.


topld V4 IR x96:  Synthesis and optimization
Mon Mar 29 03:19:13 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------



------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 4 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

----------------------------------------------------------
Circuit simplification results:

	Expanded 0 signals.
	Turned 0 signals into soft nodes.
	Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 27 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN HEADER INFORMATION  (03:19:13)

Input File(s): sync.pla
Device       : c20v8
Package      : PALCE20V8-7PC
ReportFile   : sync.rpt

Program Controls:
                 None.

Signal Requests:
    GROUP FAST_SLEW ALL

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (03:19:13)

Messages:
  Information: Process virtual 'pitchffD' ... expanded.
  Information: Process virtual 'sampclkD' ... expanded.
  Information: Process virtual 'pitchdownD' ... expanded.
  Information: Process virtual 'pitchupD' ... expanded.
  Information: Process virtual 'pitchff' ... converted to NODE.
  Information: Process virtual 'last_pitchclk' ... converted to NODE.
  Information: Optimizing logic using best output polarity for signals:
         sampclk.D pitchdown.D pitchup.D pitchff.D

  Information: Selected logic optimization OFF for signals:
         sampclk.C passorig.D passorig.C shift.D shift.C pitchdown.C pitchup.C
         n_reset.D n_reset.C pitchff.C last_pitchclk.D last_pitchclk.C



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     11/NOV/97    [v4.02 ] 4 IR x95

LOGIC MINIMIZATION         (03:19:13)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (03:19:13)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN EQUATIONS           (03:19:13)


    sampclk.D =
          sampsel * sampclk_fast 
        + /sampsel * sampclk_slow 

    sampclk.C =
          clk 

    passorig.D =
          passorig_in 

    passorig.C =
          clk 

    shift.D =
          shift_in 

    shift.C =
          clk 

    pitchdown.D =
          pitchclk * /last_pitchclk.Q * pitchff.Q * pitchdown_in 
        + pitchclk * /pitchsel * /last_pitchclk.Q * pitchdown_in 

    pitchdown.C =
          clk 

    pitchup.D =
          pitchup_in * pitchclk * /last_pitchclk.Q * pitchff.Q 
        + pitchup_in * pitchclk * /pitchsel * /last_pitchclk.Q 

    pitchup.C =
          clk 

    n_reset.D =
          n_reset_in 

    n_reset.C =
          clk 

    last_pitchclk.D =
          pitchclk 

    last_pitchclk.C =
          clk 

    pitchff.D =
          pitchclk * /last_pitchclk.Q * /pitchff.Q 
        + last_pitchclk.Q * pitchff.Q 
        + /pitchclk * pitchff.Q 

    pitchff.C =
          clk 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN RULE CHECK          (03:19:13)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (03:19:13)

Messages:
  Information: Checking for duplicate NODE logic.
                 None.


                                 C20V8C
                 __________________________________________
            clk =| 1|                                  |24|* not used       
     n_reset_in =| 2|                                  |23|* not used       
     pitchup_in =| 3|                                  |22|= n_reset        
   pitchdown_in =| 4|                                  |21|= pitchup        
       shift_in =| 5|                                  |20|= pitchdown      
    passorig_in =| 6|                                  |19|= shift          
        sampsel =| 7|                                  |18|= passorig       
   sampclk_fast =| 8|                                  |17|= (last_pitchc.. 
   sampclk_slow =| 9|                                  |16|= (pitchff)      
       pitchclk =|10|                                  |15|= sampclk        
       pitchsel =|11|                                  |14|* not used       
       not used *|12|                                  |13|* Reserved       
                 __________________________________________


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

RESOURCE ALLOCATION        (03:19:13)

  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |   10  |   12  |
                 | Clock/Inputs       |    1  |    1  |
                 | Enable/Inputs      |    0  |    1  |
                 | Output Macrocells  |    8  |    8  |
                 ______________________________________
                                          19  /   22   = 86  %


  Information: Output Logic Product Term Utilization.

                  Node#  Output Signal Name  Used   Max
                 ________________________________________
                 | 15  |  sampclk         |   2  |   8  |
                 | 16  |  pitchff         |   3  |   8  |
                 | 17  |  last_pitchclk   |   1  |   8  |
                 | 18  |  passorig        |   1  |   8  |
                 | 19  |  shift           |   1  |   8  |
                 | 20  |  pitchdown       |   2  |   8  |
                 | 21  |  pitchup         |   2  |   8  |
                 | 22  |  n_reset         |   1  |   8  |
                 ________________________________________
                                             13  /  64   = 20  %


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

JEDEC ASSEMBLE             (03:19:13)

Messages:
  Information: Output file 'sync.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 03:19:14
