
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x95
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|    1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  fulladd.vhd
Options:    -o2 -ygs -fP -v10 -dc20v8 -pPALCE20V8-7JC fulladd.vhd
======================================================================

vhdlfe V4 IR x95:  VHDL parser
Tue Feb  9 19:55:59 1999

Library 'work' => directory 'lc20v8'
Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/mit/6.111/warp4.3/lib/ieee/work'
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.

vhdlfe:  No errors.


tovif V4 IR x95:  High-level synthesis
Tue Feb  9 19:55:59 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.

tovif:  No errors.


topld V4 IR x96:  Synthesis and optimization
Tue Feb  9 19:56:14 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/lc16v8/stdlogic/c16v8.vif'.
Linking '/afs/athena.mit.edu/user/g/o/golem/doc/6.111-spring99/lc20v8/halfadd.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------



------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 0 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

----------------------------------------------------------
Circuit simplification results:

	Expanded 3 signals.
	Turned 0 signals into soft nodes.
	Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 8 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN HEADER INFORMATION  (19:56:29)

Input File(s): fulladd.pla
Device       : c20v8
Package      : PALCE20V8-7JC
ReportFile   : fulladd.rpt

Program Controls:
                 None.

Signal Requests:
    GROUP FAST_SLEW ALL

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (19:56:29)

Messages:
  Information: Optimizing logic using best output polarity for signals:
         outc sumout



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     11/NOV/97    [v4.02 ] 4 IR x95

LOGIC MINIMIZATION         (19:56:34)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (19:56:37)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN EQUATIONS           (19:56:41)


    sumout =
          ina * /inb * /inc 
        + /ina * inb * /inc 
        + /ina * /inb * inc 
        + ina * inb * inc 

    outc =
          inb * inc 
        + ina * inc 
        + ina * inb 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN RULE CHECK          (19:56:42)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (19:56:42)

Messages:
  Information: Checking for duplicate NODE logic.
                 None.

Device:  C20V8A
Package: PALCE20V8-7JC

                  2  :  inc
                  3  :  inb
                  4  :  ina
                  5  :  Not Used
                  6  :  Not Used
                  7  :  Not Used
                  9  :  Not Used
                 10  :  Not Used
                 11  :  Not Used
                 12  :  Not Used
                 13  :  Not Used
                 12  :  GND
                 16  :  Not Used
                 17  :  Not Used
                 18  :  outc
                 19  :  Not Used
                 20  :  Not Used
                 21  :  Not Used
                 23  :  Not Used
                 24  :  Not Used
                 25  :  Not Used
                 26  :  sumout
                 27  :  Not Used
                 24  :  VCC


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

RESOURCE ALLOCATION        (19:56:42)

  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    3  |   14  |
                 | Output Macrocells  |    2  |    2  |
                 | I/O Macrocells     |    0  |    6  |
                 ______________________________________
                                           5  /   22   = 22  %


  Information: Output Logic Product Term Utilization.

                  Node#  Output Signal Name  Used   Max
                 ________________________________________
                 | 15  |  outc            |   3  |   7  |
                 | 16  |  Unused          |   0  |   7  |
                 | 17  |  Unused          |   0  |   7  |
                 | 18  |  Unused          |   0  |   7  |
                 | 19  |  Unused          |   0  |   7  |
                 | 20  |  Unused          |   0  |   7  |
                 | 21  |  Unused          |   0  |   7  |
                 | 22  |  sumout          |   4  |   7  |
                 ________________________________________
                                              7  /  56   = 12  %


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

JEDEC ASSEMBLE             (19:56:42)

Messages:
  Information: Output file 'fulladd.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 19:56:43
