
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x95
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|    1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  absdiff_addlo.vhd
Options:    -m -e10 -w100 -o2 -yga -fP -v10 -dc22v10 -pPALCE22V10-25PC/PI absdiff_addlo.vhd
======================================================================

vhdlfe V4 IR x95:  VHDL parser
Sun Apr 25 23:31:42 1999

Library 'work' => directory 'lc22v10'
Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/mit/6.111/warp4.3/lib/ieee/work'
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
absdiff_addlo.vhd (line 19, col 29):  Note: Substituting module 'add_vv_us' for '+'.

vhdlfe:  No errors.


tovif V4 IR x95:  High-level synthesis
Sun Apr 25 23:31:43 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/madd_sub.vif'.

tovif:  No errors.


topld V4 IR x96:  Synthesis and optimization
Sun Apr 25 23:31:44 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/madd_sub.vif'.
Linking '/mit/6.111/warp4.3/lib/lc22v10/stdlogic/c22v10.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------


Deleted 0 User equations/components.
Deleted 0 Synthesized equations/components.

------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 35 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

----------------------------------------------------------
Circuit simplification results:

	Expanded 0 signals.
	Turned 0 signals into soft nodes.
	Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 64 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN HEADER INFORMATION  (23:31:45)

Input File(s): absdiff_addlo.pla
Device       : C22V10
Package      : PALCE22V10-25PC/PI
ReportFile   : absdiff_addlo.rpt

Program Controls:
                 None.

Signal Requests:
    GROUP FAST_SLEW ALL
    GROUP FLOAT carry_out 

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (23:31:45)

Messages:
  Information: Process virtual 'MODULE_1_g1_a0_g0_u0_c_4' ... expanded.
  Information: Process virtual 'MODULE_1_g1_a0_g0_u0_ci_2' ... expanded.
  Information: Process virtual 'MODULE_1_g1_a0_g0_u0_ci_6' ... expanded.
  Information: Process virtual 'MODULE_1_g1_a0_g0_u0_ci_4' ... expanded.
  Information: Process virtual 'MODULE_1_g1_a0_g0_u0_c_0' ... expanded.
  Information: Optimizing logic using best output polarity for signals:
         carry_out c_0 c_1 c_2 c_3 c_4 c_5 MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3
         MODULE_1_g1_a0_g0_u0_ga_g1_ua0



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     11/NOV/97    [v4.02 ] 4 IR x95

LOGIC MINIMIZATION         (23:31:45)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (23:31:45)

Messages:
  Information: Optimizing Banked Preset/Reset requirements.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN EQUATIONS           (23:31:45)


    c_5 =
          a_5 * /b_5 * /b_4 * /MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3 
        + /a_5 * b_5 * /b_4 * /MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3 
        + a_5 * /a_4 * /b_5 * /MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3 
        + /a_5 * /a_4 * b_5 * /MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3 
        + /a_5 * /b_5 * b_4 * MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3 
        + a_5 * b_5 * b_4 * MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3 
        + /a_5 * a_4 * /b_5 * MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3 
        + a_5 * a_4 * b_5 * MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3 
        + a_5 * /a_4 * /b_5 * /b_4 
        + /a_5 * /a_4 * b_5 * /b_4 
        + /a_5 * a_4 * /b_5 * b_4 
        + a_5 * a_4 * b_5 * b_4 

    c_4 =
          a_4 * /b_4 * /MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3 
        + /a_4 * b_4 * /MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3 
        + /a_4 * /b_4 * MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3 
        + a_4 * b_4 * MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3 

    c_3 =
          a_3 * /b_3 * /b_2 * /MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + /a_3 * b_3 * /b_2 * /MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + a_3 * /a_2 * /b_3 * /MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + /a_3 * /a_2 * b_3 * /MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + /a_3 * /b_3 * b_2 * MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + a_3 * b_3 * b_2 * MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + /a_3 * a_2 * /b_3 * MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + a_3 * a_2 * b_3 * MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + a_3 * /a_2 * /b_3 * /b_2 
        + /a_3 * /a_2 * b_3 * /b_2 
        + /a_3 * a_2 * /b_3 * b_2 
        + a_3 * a_2 * b_3 * b_2 

    c_2 =
          a_2 * /b_2 * /MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + /a_2 * b_2 * /MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + /a_2 * /b_2 * MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + a_2 * b_2 * MODULE_1_g1_a0_g0_u0_ga_g1_ua0 

    c_1 =
          /a_1 * a_0 * /b_1 * b_0 
        + a_1 * a_0 * b_1 * b_0 
        + a_1 * /b_1 * /b_0 
        + /a_1 * b_1 * /b_0 
        + a_1 * /a_0 * /b_1 
        + /a_1 * /a_0 * b_1 

    c_0 =
          a_0 * /b_0 
        + /a_0 * b_0 

    carry_out =
          b_5 * b_4 * MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3 
        + a_5 * b_4 * MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3 
        + a_4 * b_5 * MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3 
        + a_5 * a_4 * MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3 
        + a_4 * b_5 * b_4 
        + a_5 * a_4 * b_4 
        + a_5 * b_5 

    MODULE_1_g1_a0_g0_u0_ga_g1_ua0 =
          a_0 * b_1 * b_0 
        + a_1 * a_0 * b_0 
        + a_1 * b_1 

    MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3 =
          b_3 * b_2 * MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + a_3 * b_2 * MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + a_2 * b_3 * MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + a_3 * a_2 * MODULE_1_g1_a0_g0_u0_ga_g1_ua0 
        + a_2 * b_3 * b_2 
        + a_3 * a_2 * b_2 
        + a_3 * b_3 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN RULE CHECK          (23:31:45)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (23:31:45)

Messages:
  Information: Checking for duplicate NODE logic.
                 None.


                                 C22V10
                 __________________________________________
            b_0 =| 1|                                  |24|* not used       
            b_1 =| 2|                                  |23|= (MODULE_1_g1.. 
            a_0 =| 3|                                  |22|= c_2            
            a_1 =| 4|                                  |21|= c_5            
            b_2 =| 5|                                  |20|= (MODULE_1_g1.. 
            b_3 =| 6|                                  |19|* not used       
            a_2 =| 7|                                  |18|= c_0            
            a_3 =| 8|                                  |17|= c_4            
            b_4 =| 9|                                  |16|= c_3            
            b_5 =|10|                                  |15|= c_1            
            a_4 =|11|                                  |14|= carry_out      
       not used *|12|                                  |13|= a_5            
                 __________________________________________


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

RESOURCE ALLOCATION        (23:31:45)

  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |   11  |   11  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |    9  |   10  |
                 ______________________________________
                                          21  /   22   = 95  %


  Information: Output Logic Product Term Utilization.

                  Node#  Output Signal Name  Used   Max
                 ________________________________________
                 | 14  |  carry_out       |   7  |   8  |
                 | 15  |  c_1             |   6  |  10  |
                 | 16  |  c_3             |  12  |  12  |
                 | 17  |  c_4             |   4  |  14  |
                 | 18  |  c_0             |   2  |  16  |
                 | 19  |  Unused          |   0  |  16  |
                 | 20  |  MODULE_1_g1_..  |   3  |  14  |
                 | 21  |  c_5             |  12  |  12  |
                 | 22  |  c_2             |   4  |  10  |
                 | 23  |  MODULE_1_g1_..  |   7  |   8  |
                 | 25  |  Unused          |   0  |   1  |
                 ________________________________________
                                             57  / 121   = 47  %


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

JEDEC ASSEMBLE             (23:31:45)

Messages:
  Information: Output file 'absdiff_addlo.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 23:31:45
