
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x95
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|    1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  absdiff_final.vhd
Options:    -m -e10 -w100 -o2 -yga -fP -v10 -dc22v10 -pPALCE22V10-25PC/PI absdiff_final.vhd
======================================================================

vhdlfe V4 IR x95:  VHDL parser
Mon Apr 26 02:32:50 1999

Library 'work' => directory 'lc22v10'
Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/mit/6.111/warp4.3/lib/ieee/work'
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
absdiff_final.vhd (line 28, col 28):  Note: Substituting module 'add_vi_us' for '+'.

vhdlfe:  No errors.


tovif V4 IR x95:  High-level synthesis
Mon Apr 26 02:32:50 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.

tovif:  No errors.


topld V4 IR x96:  Synthesis and optimization
Mon Apr 26 02:32:51 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
Linking '/mit/6.111/warp4.3/lib/lc22v10/stdlogic/c22v10.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------



------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 8 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

----------------------------------------------------------
Circuit simplification results:

	Expanded 16 signals.
	Turned 0 signals into soft nodes.
	Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 52 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN HEADER INFORMATION  (02:32:52)

Input File(s): absdiff_final.pla
Device       : C22V10
Package      : PALCE22V10-25PC/PI
ReportFile   : absdiff_final.rpt

Program Controls:
                 None.

Signal Requests:
    GROUP FAST_SLEW ALL

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (02:32:52)

Messages:
  Information: Process virtual 'out_val_0D' ... expanded.
  Information: Process virtual 'out_val_1D' ... expanded.
  Information: Process virtual 'out_val_2D' ... expanded.
  Information: Process virtual 'out_val_3D' ... expanded.
  Information: Process virtual 'out_val_4D' ... expanded.
  Information: Process virtual 'out_val_5D' ... expanded.
  Information: Process virtual 'out_val_6D' ... expanded.
  Information: Process virtual 'out_val_7D' ... expanded.
  Information: Optimizing logic using best output polarity for signals:
         out_val_7.D out_val_6.D out_val_5.D out_val_4.D out_val_3.D
         out_val_2.D out_val_1.D out_val_0.D

  Information: Selected logic optimization OFF for signals:
         out_val_7.C out_val_6.C out_val_5.C out_val_4.C out_val_3.C
         out_val_2.C out_val_1.C out_val_0.C



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     11/NOV/97    [v4.02 ] 4 IR x95

LOGIC MINIMIZATION         (02:32:52)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (02:32:52)

Messages:
  Information: Optimizing Banked Preset/Reset requirements.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN EQUATIONS           (02:32:53)


    out_val_7.D =
          /n_lden * cblank * /in_val_7 * in_val_6 * in_val_5 * in_val_4 * 
          in_val_3 * in_val_2 * in_val_1 * in_val_0 
        + /n_lden * cblank * sel * in_val_7 * /in_val_0 
        + /n_lden * cblank * sel * in_val_7 * /in_val_1 
        + /n_lden * cblank * sel * in_val_7 * /in_val_2 
        + /n_lden * cblank * sel * in_val_7 * /in_val_3 
        + /n_lden * cblank * sel * in_val_7 * /in_val_4 
        + /n_lden * cblank * sel * in_val_7 * /in_val_5 
        + /n_lden * cblank * sel * in_val_7 * /in_val_6 
        + /n_lden * cblank * /sel * /in_val_7 
        + n_lden * cblank * out_val_7.Q 

    out_val_7.AR =
          GND

    out_val_7.SP =
          GND

    out_val_7.C =
          clk 

    out_val_6.D =
          /n_lden * cblank * /in_val_6 * in_val_5 * in_val_4 * in_val_3 * 
          in_val_2 * in_val_1 * in_val_0 
        + /n_lden * cblank * sel * in_val_6 * /in_val_0 
        + /n_lden * cblank * sel * in_val_6 * /in_val_1 
        + /n_lden * cblank * sel * in_val_6 * /in_val_2 
        + /n_lden * cblank * sel * in_val_6 * /in_val_3 
        + /n_lden * cblank * sel * in_val_6 * /in_val_4 
        + /n_lden * cblank * sel * in_val_6 * /in_val_5 
        + /n_lden * cblank * /sel * /in_val_6 
        + n_lden * cblank * out_val_6.Q 

    out_val_6.AR =
          GND

    out_val_6.SP =
          GND

    out_val_6.C =
          clk 

    out_val_5.D =
          /n_lden * cblank * /in_val_5 * in_val_4 * in_val_3 * in_val_2 * 
          in_val_1 * in_val_0 
        + /n_lden * cblank * sel * in_val_5 * /in_val_0 
        + /n_lden * cblank * sel * in_val_5 * /in_val_1 
        + /n_lden * cblank * sel * in_val_5 * /in_val_2 
        + /n_lden * cblank * sel * in_val_5 * /in_val_3 
        + /n_lden * cblank * sel * in_val_5 * /in_val_4 
        + /n_lden * cblank * /sel * /in_val_5 
        + n_lden * cblank * out_val_5.Q 

    out_val_5.AR =
          GND

    out_val_5.SP =
          GND

    out_val_5.C =
          clk 

    out_val_4.D =
          /n_lden * cblank * /in_val_4 * in_val_3 * in_val_2 * in_val_1 * 
          in_val_0 
        + /n_lden * cblank * sel * in_val_4 * /in_val_0 
        + /n_lden * cblank * sel * in_val_4 * /in_val_1 
        + /n_lden * cblank * sel * in_val_4 * /in_val_2 
        + /n_lden * cblank * sel * in_val_4 * /in_val_3 
        + /n_lden * cblank * /sel * /in_val_4 
        + n_lden * cblank * out_val_4.Q 

    out_val_4.AR =
          GND

    out_val_4.SP =
          GND

    out_val_4.C =
          clk 

    out_val_3.D =
          /n_lden * cblank * /in_val_3 * in_val_2 * in_val_1 * in_val_0 
        + /n_lden * cblank * sel * in_val_3 * /in_val_0 
        + /n_lden * cblank * sel * in_val_3 * /in_val_1 
        + /n_lden * cblank * sel * in_val_3 * /in_val_2 
        + /n_lden * cblank * /sel * /in_val_3 
        + n_lden * cblank * out_val_3.Q 

    out_val_3.AR =
          GND

    out_val_3.SP =
          GND

    out_val_3.C =
          clk 

    out_val_2.D =
          /n_lden * cblank * /in_val_2 * in_val_1 * in_val_0 
        + /n_lden * cblank * sel * in_val_2 * /in_val_0 
        + /n_lden * cblank * sel * in_val_2 * /in_val_1 
        + /n_lden * cblank * /sel * /in_val_2 
        + n_lden * cblank * out_val_2.Q 

    out_val_2.AR =
          GND

    out_val_2.SP =
          GND

    out_val_2.C =
          clk 

    out_val_1.D =
          /n_lden * cblank * sel * in_val_1 * /in_val_0 
        + /n_lden * cblank * /in_val_1 * in_val_0 
        + /n_lden * cblank * /sel * /in_val_1 
        + n_lden * cblank * out_val_1.Q 

    out_val_1.AR =
          GND

    out_val_1.SP =
          GND

    out_val_1.C =
          clk 

    out_val_0.D =
          n_lden * cblank * out_val_0.Q 
        + /n_lden * cblank * /in_val_0 

    out_val_0.AR =
          GND

    out_val_0.SP =
          GND

    out_val_0.C =
          clk 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN RULE CHECK          (02:32:53)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (02:32:53)

Messages:
  Information: All signals pre-placed in user design.


                                 C22V10
                 __________________________________________
            clk =| 1|                                  |24|* not used       
         cblank =| 2|                                  |23|* not used       
       in_val_0 =| 3|                                  |22|= out_val_0      
       in_val_1 =| 4|                                  |21|= out_val_1      
       in_val_2 =| 5|                                  |20|= out_val_2      
       in_val_3 =| 6|                                  |19|= out_val_3      
       in_val_4 =| 7|                                  |18|= out_val_4      
       in_val_5 =| 8|                                  |17|= out_val_5      
       in_val_6 =| 9|                                  |16|= out_val_6      
       in_val_7 =|10|                                  |15|= out_val_7      
            sel =|11|                                  |14|* not used       
       not used *|12|                                  |13|= n_lden         
                 __________________________________________


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
  Information: Checking for duplicate NODE logic.
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

RESOURCE ALLOCATION        (02:32:53)

  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |   11  |   11  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |    8  |   10  |
                 ______________________________________
                                          20  /   22   = 90  %


  Information: Output Logic Product Term Utilization.

                  Node#  Output Signal Name  Used   Max
                 ________________________________________
                 | 14  |  Unused          |   0  |   8  |
                 | 15  |  out_val_7       |  10  |  10  |
                 | 16  |  out_val_6       |   9  |  12  |
                 | 17  |  out_val_5       |   8  |  14  |
                 | 18  |  out_val_4       |   7  |  16  |
                 | 19  |  out_val_3       |   6  |  16  |
                 | 20  |  out_val_2       |   5  |  14  |
                 | 21  |  out_val_1       |   4  |  12  |
                 | 22  |  out_val_0       |   2  |  10  |
                 | 23  |  Unused          |   0  |   8  |
                 | 25  |  Unused          |   0  |   1  |
                 ________________________________________
                                             51  / 121   = 42  %


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

JEDEC ASSEMBLE             (02:32:53)

Messages:
  Information: Output file 'absdiff_final.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 02:32:53
