
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x95
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|    1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  absdiff_invertff.vhd
Options:    -m -o2 -ygs -fP -v10 -dc20v8 -pPALCE20V8-25PC absdiff_invertff.vhd
======================================================================

vhdlfe V4 IR x95:  VHDL parser
Mon Apr 26 02:22:00 1999

Library 'work' => directory 'lc20v8'
Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/mit/6.111/warp4.3/lib/ieee/work'
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.

vhdlfe:  No errors.


tovif V4 IR x95:  High-level synthesis
Mon Apr 26 02:22:00 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.

tovif:  No errors.


topld V4 IR x96:  Synthesis and optimization
Mon Apr 26 02:22:00 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------



------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 0 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

----------------------------------------------------------
Circuit simplification results:

	Expanded 0 signals.
	Turned 0 signals into soft nodes.
	Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 26 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN HEADER INFORMATION  (02:22:01)

Input File(s): absdiff_invertff.pla
Device       : c20v8
Package      : PALCE20V8-25PC
ReportFile   : absdiff_invertff.rpt

Program Controls:
                 None.

Signal Requests:
    GROUP FAST_SLEW ALL

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (02:22:01)

Messages:
  Information: Process virtual 'output_0D' ... expanded.
  Information: Process virtual 'output_1D' ... expanded.
  Information: Process virtual 'output_2D' ... expanded.
  Information: Process virtual 'output_3D' ... expanded.
  Information: Process virtual 'output_4D' ... expanded.
  Information: Process virtual 'output_5D' ... expanded.
  Information: Process virtual 'output_6D' ... expanded.
  Information: Process virtual 'output_7D' ... expanded.
  Information: Optimizing logic using best output polarity for signals:
         output_7.D output_6.D output_5.D output_4.D output_3.D output_2.D
         output_1.D output_0.D

  Information: Selected logic optimization OFF for signals:
         output_7.C output_6.C output_5.C output_4.C output_3.C output_2.C
         output_1.C output_0.C



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     11/NOV/97    [v4.02 ] 4 IR x95

LOGIC MINIMIZATION         (02:22:01)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (02:22:01)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN EQUATIONS           (02:22:01)


    output_7.D =
          n_lden * output_7.Q 
        + /n_lden * /input_7 

    output_7.C =
          clk 

    output_6.D =
          n_lden * output_6.Q 
        + /n_lden * /input_6 

    output_6.C =
          clk 

    output_5.D =
          n_lden * output_5.Q 
        + /n_lden * /input_5 

    output_5.C =
          clk 

    output_4.D =
          n_lden * output_4.Q 
        + /n_lden * /input_4 

    output_4.C =
          clk 

    output_3.D =
          n_lden * output_3.Q 
        + /n_lden * /input_3 

    output_3.C =
          clk 

    output_2.D =
          n_lden * output_2.Q 
        + /n_lden * /input_2 

    output_2.C =
          clk 

    output_1.D =
          n_lden * output_1.Q 
        + /n_lden * /input_1 

    output_1.C =
          clk 

    output_0.D =
          n_lden * output_0.Q 
        + /n_lden * /input_0 

    output_0.C =
          clk 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN RULE CHECK          (02:22:01)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (02:22:01)

Messages:
  Information: Checking for duplicate NODE logic.
                 None.


                                 C20V8C
                 __________________________________________
            clk =| 1|                                  |24|* not used       
         n_lden =| 2|                                  |23|* not used       
        input_0 =| 3|                                  |22|= output_0       
        input_1 =| 4|                                  |21|= output_1       
        input_2 =| 5|                                  |20|= output_2       
        input_3 =| 6|                                  |19|= output_3       
        input_4 =| 7|                                  |18|= output_4       
        input_5 =| 8|                                  |17|= output_5       
        input_6 =| 9|                                  |16|= output_6       
        input_7 =|10|                                  |15|= output_7       
       not used *|11|                                  |14|* not used       
       not used *|12|                                  |13|* Reserved       
                 __________________________________________


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

RESOURCE ALLOCATION        (02:22:01)

  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    9  |   12  |
                 | Clock/Inputs       |    1  |    1  |
                 | Enable/Inputs      |    0  |    1  |
                 | Output Macrocells  |    8  |    8  |
                 ______________________________________
                                          18  /   22   = 81  %


  Information: Output Logic Product Term Utilization.

                  Node#  Output Signal Name  Used   Max
                 ________________________________________
                 | 15  |  output_7        |   2  |   8  |
                 | 16  |  output_6        |   2  |   8  |
                 | 17  |  output_5        |   2  |   8  |
                 | 18  |  output_4        |   2  |   8  |
                 | 19  |  output_3        |   2  |   8  |
                 | 20  |  output_2        |   2  |   8  |
                 | 21  |  output_1        |   2  |   8  |
                 | 22  |  output_0        |   2  |   8  |
                 ________________________________________
                                             16  /  64   = 25  %


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

JEDEC ASSEMBLE             (02:22:01)

Messages:
  Information: Output file 'absdiff_invertff.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 02:22:01
