
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x95
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|    1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  bucket.vhd
Options:    -o2 -ygs -fO -fP -v10 -dc372i -pCY7C372I-66JC bucket.vhd
======================================================================

vhdlfe V4 IR x95:  VHDL parser
Sun May  9 01:58:08 1999

Library 'work' => directory 'lc372i'
Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/mit/6.111/warp4.3/lib/ieee/work'
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.

vhdlfe:  No errors.


tovif V4 IR x95:  High-level synthesis
Sun May  9 01:58:19 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
bucket.vhd (line 31, col 6):  Warning: (W460) 'sram_n_we' unassigned in arch. 'bucketarch' of 'bucket'.
bucket.vhd (line 31, col 6):  Warning: (W460) 'sram_n_oe' unassigned in arch. 'bucketarch' of 'bucket'.

tovif:  No errors.  2 warnings.


topld V4 IR x96:  Synthesis and optimization
Sun May  9 01:58:28 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------



------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 13 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

----------------------------------------------------------
Circuit simplification results:

	Expanded 0 signals.
	Turned 0 signals into soft nodes.
	Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 43 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN HEADER INFORMATION  (01:58:36)

Input File(s): bucket.pla
Device       : c372i
Package      : CY7C372I-66JC
ReportFile   : bucket.rpt

Program Controls:
                 None.

Signal Requests:
    GROUP DT-OPT ALL
    GROUP FAST_SLEW ALL

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (01:58:36)

Messages:
  Information: Generating both D & T register equations for signal sram_data_0.D
  Information: Expanding XOR equation found on signal sram_data_0.T
  Information: Generating both D & T register equations for signal sram_data_1.D
  Information: Expanding XOR equation found on signal sram_data_1.T
  Information: Generating both D & T register equations for signal sram_data_2.D
  Information: Expanding XOR equation found on signal sram_data_2.T
  Information: Generating both D & T register equations for signal sram_data_3.D
  Information: Expanding XOR equation found on signal sram_data_3.T
  Information: Generating both D & T register equations for signal sram_addr_low_0.D
  Information: Expanding XOR equation found on signal sram_addr_low_0.T
  Information: Generating both D & T register equations for signal sram_addr_low_1.D
  Information: Expanding XOR equation found on signal sram_addr_low_1.T
  Information: Generating both D & T register equations for signal sram_addr_low_2.D
  Information: Expanding XOR equation found on signal sram_addr_low_2.T
  Information: Generating both D & T register equations for signal sram_addr_low_3.D
  Information: Expanding XOR equation found on signal sram_addr_low_3.T
  Information: Generating both D & T register equations for signal sram_addr_low_4.D
  Information: Expanding XOR equation found on signal sram_addr_low_4.T
  Information: Generating both D & T register equations for signal sram_addr_low_5.D
  Information: Expanding XOR equation found on signal sram_addr_low_5.T
  Information: Optimizing logic without changing polarity for signals:
         sram_data_0.T sram_data_1.T sram_data_2.T sram_data_3.T
         sram_addr_low_0.T sram_addr_low_1.T sram_addr_low_2.T
         sram_addr_low_3.T sram_addr_low_4.T sram_addr_low_5.T

  Information: Selected logic optimization OFF for signals:
         sram_data_0.D sram_data_0.C sram_data_1.D sram_data_1.C sram_data_2.D
         sram_data_2.C sram_data_3.D sram_data_3.C sram_addr_low_0.D
         sram_addr_low_0.C sram_addr_low_1.D sram_addr_low_1.C
         sram_addr_low_2.D sram_addr_low_2.C sram_addr_low_3.D
         sram_addr_low_3.C sram_addr_low_4.D sram_addr_low_4.C
         sram_addr_low_5.D sram_addr_low_5.C



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     11/NOV/97    [v4.02 ] 4 IR x95

LOGIC MINIMIZATION         (01:58:39)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (01:58:41)

Messages:
  Information: Optimizing Banked Preset/Reset requirements.
  Information: Selecting D register equation as minimal for signal sram_addr_low_5
  Information: Selecting D register equation as minimal for signal sram_addr_low_4
  Information: Selecting D register equation as minimal for signal sram_addr_low_3
  Information: Selecting D register equation as minimal for signal sram_addr_low_2
  Information: Selecting D register equation as minimal for signal sram_addr_low_1
  Information: Selecting D register equation as minimal for signal sram_addr_low_0
  Information: Selecting D register equation as minimal for signal sram_data_3
  Information: Selecting D register equation as minimal for signal sram_data_2
  Information: Selecting D register equation as minimal for signal sram_data_1
  Information: Selecting D register equation as minimal for signal sram_data_0


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN EQUATIONS           (01:58:46)


    sram_addr_low_5.D =
          coladdr_in_7 

    sram_addr_low_5.AP =
          GND

    sram_addr_low_5.AR =
          GND

    sram_addr_low_5.C =
          clk 

    sram_addr_low_4.D =
          coladdr_in_6 

    sram_addr_low_4.AP =
          GND

    sram_addr_low_4.AR =
          GND

    sram_addr_low_4.C =
          clk 

    sram_addr_low_3.D =
          coladdr_in_5 

    sram_addr_low_3.AP =
          GND

    sram_addr_low_3.AR =
          GND

    sram_addr_low_3.C =
          clk 

    sram_addr_low_2.D =
          coladdr_in_4 

    sram_addr_low_2.AP =
          GND

    sram_addr_low_2.AR =
          GND

    sram_addr_low_2.C =
          clk 

    sram_addr_low_1.D =
          coladdr_in_3 

    sram_addr_low_1.AP =
          GND

    sram_addr_low_1.AR =
          GND

    sram_addr_low_1.C =
          clk 

    sram_addr_low_0.D =
          coladdr_in_2 

    sram_addr_low_0.AP =
          GND

    sram_addr_low_0.AR =
          GND

    sram_addr_low_0.C =
          clk 

    sram_data_3.D =
          diff_3 

    sram_data_3.AP =
          GND

    sram_data_3.AR =
          GND

    sram_data_3.C =
          /clk 

    sram_data_2.D =
          diff_2 

    sram_data_2.AP =
          GND

    sram_data_2.AR =
          GND

    sram_data_2.C =
          /clk 

    sram_data_1.D =
          diff_1 

    sram_data_1.AP =
          GND

    sram_data_1.AR =
          GND

    sram_data_1.C =
          /clk 

    sram_data_0.D =
          diff_0 

    sram_data_0.AP =
          GND

    sram_data_0.AR =
          GND

    sram_data_0.C =
          /clk 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN RULE CHECK          (01:58:46)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

PARTITION LOGIC            (01:58:47)

Messages:
  Information: Checking design is strictly SYNCHRONOUS.
  Information: Initializing Logic Block structures.
  Information: Checking for duplicate NODE logic.
  Information: Forming input seeds.
  Information: Forming input seeds.
  Information: Assigning fixed logic to Logic Blocks.
  Information: Processing banked global preset, reset and output enable.
  Information: Separating output logic set to GND/VCC.
  Information: Validating Logic Block's with pre-placed signals.
  Information: Assigning floating outputs to Logic Blocks.
  Information: Separating input register logic.
  Information: Assigning initializing equations to empty Logic Blocks.
  Information: Separating output combinatorial logic.
  Information: Separating disjoint output logic.
  Information: Separating output node logic.
  Information: Compacting Logic Block interconnect.
  ..........
  Information: Assigning floating inputs to Logic Blocks.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (01:58:48)

Messages:
  Information: Fitting signals to Logic Block A.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block B.
  Information: Fitting signals to Logic Block C.
  Information: Fitting signals to Logic Block D.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Routing signals to Logic Blocks.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

LOGIC BLOCK A PLACEMENT   (01:58:48)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |sram_addr_low_0
++X+++++++++++++................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2 |UNUSED
..........++++++++++++++++......................................................
| 3 |UNUSED
..............++++++++++++++++..................................................
| 4 |sram_addr_low_3
..................X+++++++++++++++..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6 |sram_addr_low_5
..........................X+++++++++++++++......................................
| 7 |UNUSED
..............................++++++++++++++++..................................
| 8 |sram_addr_low_1
..................................X+++++++++++++++..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10 |sram_addr_low_4
..........................................X+++++++++++++++......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12 |sram_addr_low_2
..................................................X+++++++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14 |UNUSED
..........................................................++++++++++++++++......
|15 |UNUSED
................................................................++++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  6 
Total count of unique Product Terms  =  6 
Total Product Terms to be assigned   =  6 
Max Product Terms used / available   =   6 /  80   = 7.51 %


Control Signals for Logic Block A
---------------------------------
CLK pin  13 : clk
CLK pin  35 : <not used>
PRESET      : GND
RESET       : GND
OE 0        : <not used>
OE 1        : <not used>
OE 2        : <not used>
OE 3        : <not used>



                              Logic Block A
                 ____________________________________________
                 |   |= >coladdr_in_6                   |   |                 
                 |   |> not used:46                     |   |                 
                 |   |> not used:47                     |   |                 
                 |   |> not used:48                     |   |                 
                 |   |> not used:49                     |  2|= sram_addr_low_0 
                 |   |> not used:50                     |   |                 
                 |   |> not used:51       not used:202 *|   |                 
                 |   |> not used:52                     |   |                 
                 |   |= >coladdr_in_2                   |  3|* not used       
                 |   |= >coladdr_in_5                   |   |                 
                 |   |> not used:55       not used:204 *|   |                 
                 |   |= >coladdr_in_4                   |   |                 
                 |   |= >coladdr_in_3                   |  4|= sram_addr_low_3 
                 |   |> not used:58                     |   |                 
                 |   |> not used:59       not used:206 *|   |                 
                 |   |> not used:60                     |   |                 
                 |   |> not used:61                     |  5|= sram_addr_low_5 
                 |   |> not used:62                     |   |                 
                 |   |> not used:63       not used:208 *|   |                 
                 |   |> not used:64                     |   |                 
                 |   |> not used:65                     |  6|= sram_addr_low_1 
                 |   |> not used:66                     |   |                 
                 |   |> not used:67       not used:210 *|   |                 
                 |   |> not used:68                     |   |                 
                 |   |> not used:69                     |  7|= sram_addr_low_4 
                 |   |= >coladdr_in_7                   |   |                 
                 |   |> not used:71       not used:212 *|   |                 
                 |   |> not used:72                     |   |                 
                 |   |> not used:73                     |  8|= sram_addr_low_2 
                 |   |> not used:74                     |   |                 
                 |   |> not used:75       not used:214 *|   |                 
                 |   |> not used:76                     |   |                 
                 |   |> not used:77                     |  9|* not used       
                 |   |> not used:78                     |   |                 
                 |   |> not used:79       not used:216 *|   |                 
                 |   |> not used:80                     |   |                 
                 |   |> not used:81                     |   |                 
                 |   |> not used:82                     |   |                 
                 |   |> not used:83                     |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    6  |    8  |
                 | Buried Macrocells  |    0  |    8  |
                 | PIM Input Connects |    6  |   36  |
                 ______________________________________
                                          12  /   52   = 23  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

LOGIC BLOCK B PLACEMENT   (01:58:48)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |[i/p]
++++++++++++++++................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2 |[i/p]
..........++++++++++++++++......................................................
| 3 |UNUSED
..............++++++++++++++++..................................................
| 4 |[i/p]
..................++++++++++++++++..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6 |UNUSED
..........................++++++++++++++++......................................
| 7 |UNUSED
..............................++++++++++++++++..................................
| 8 |UNUSED
..................................++++++++++++++++..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10 |UNUSED
..........................................++++++++++++++++......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12 |UNUSED
..................................................++++++++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14 |UNUSED
..........................................................++++++++++++++++......
|15 |UNUSED
................................................................++++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  0 
Total count of unique Product Terms  =  0 
Total Product Terms to be assigned   =  0 
Max Product Terms used / available   =   0 /  80   = 0.0  %


Control Signals for Logic Block B
---------------------------------
CLK pin  13 : <not used>
CLK pin  35 : <not used>
PRESET      : <not used>
RESET       : <not used>
OE 0        : <not used>
OE 1        : <not used>
OE 2        : <not used>
OE 3        : <not used>



                              Logic Block B
                 ____________________________________________
                 |   |> not used:84                     |   |                 
                 |   |> not used:85                     |   |                 
                 |   |> not used:86                     |   |                 
                 |   |> not used:87                     |   |                 
                 |   |> not used:88                     | 14|= coladdr_in_5   
                 |   |> not used:89                     |   |                 
                 |   |> not used:90       not used:218 *|   |                 
                 |   |> not used:91                     |   |                 
                 |   |> not used:92                     | 15|= coladdr_in_7   
                 |   |> not used:93                     |   |                 
                 |   |> not used:94       not used:220 *|   |                 
                 |   |> not used:95                     |   |                 
                 |   |> not used:96                     | 16|= diff_3         
                 |   |> not used:97                     |   |                 
                 |   |> not used:98       not used:222 *|   |                 
                 |   |> not used:99                     |   |                 
                 |   |> not used:100                    | 17|* not used       
                 |   |> not used:101                    |   |                 
                 |   |> not used:102      not used:224 *|   |                 
                 |   |> not used:103                    |   |                 
                 |   |> not used:104                    | 18|* not used       
                 |   |> not used:105                    |   |                 
                 |   |> not used:106      not used:226 *|   |                 
                 |   |> not used:107                    |   |                 
                 |   |> not used:108                    | 19|* not used       
                 |   |> not used:109                    |   |                 
                 |   |> not used:110      not used:228 *|   |                 
                 |   |> not used:111                    |   |                 
                 |   |> not used:112                    | 20|* not used       
                 |   |> not used:113                    |   |                 
                 |   |> not used:114      not used:230 *|   |                 
                 |   |> not used:115                    |   |                 
                 |   |> not used:116                    | 21|* not used       
                 |   |> not used:117                    |   |                 
                 |   |> not used:118      not used:232 *|   |                 
                 |   |> not used:119                    |   |                 
                 |   |> not used:120                    |   |                 
                 |   |> not used:121                    |   |                 
                 |   |> not used:122                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    3  |    8  |
                 | Buried Macrocells  |    0  |    8  |
                 | PIM Input Connects |    0  |   36  |
                 ______________________________________
                                           3  /   52   = 5   %


----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

LOGIC BLOCK C PLACEMENT   (01:58:48)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |[i/p]
++++++++++++++++................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2 |[i/p]
..........++++++++++++++++......................................................
| 3 |UNUSED
..............++++++++++++++++..................................................
| 4 |[i/p]
..................++++++++++++++++..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6 |UNUSED
..........................++++++++++++++++......................................
| 7 |UNUSED
..............................++++++++++++++++..................................
| 8 |UNUSED
..................................++++++++++++++++..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10 |UNUSED
..........................................++++++++++++++++......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12 |UNUSED
..................................................++++++++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14 |UNUSED
..........................................................++++++++++++++++......
|15 |UNUSED
................................................................++++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  0 
Total count of unique Product Terms  =  0 
Total Product Terms to be assigned   =  0 
Max Product Terms used / available   =   0 /  80   = 0.0  %


Control Signals for Logic Block C
---------------------------------
CLK pin  13 : <not used>
CLK pin  35 : <not used>
PRESET      : <not used>
RESET       : <not used>
OE 0        : <not used>
OE 1        : <not used>
OE 2        : <not used>
OE 3        : <not used>



                              Logic Block C
                 ____________________________________________
                 |   |> not used:123                    |   |                 
                 |   |> not used:124                    |   |                 
                 |   |> not used:125                    |   |                 
                 |   |> not used:126                    |   |                 
                 |   |> not used:127                    | 24|= coladdr_in_6   
                 |   |> not used:128                    |   |                 
                 |   |> not used:129      not used:234 *|   |                 
                 |   |> not used:130                    |   |                 
                 |   |> not used:131                    | 25|= diff_2         
                 |   |> not used:132                    |   |                 
                 |   |> not used:133      not used:236 *|   |                 
                 |   |> not used:134                    |   |                 
                 |   |> not used:135                    | 26|= coladdr_in_2   
                 |   |> not used:136                    |   |                 
                 |   |> not used:137      not used:238 *|   |                 
                 |   |> not used:138                    |   |                 
                 |   |> not used:139                    | 27|* not used       
                 |   |> not used:140                    |   |                 
                 |   |> not used:141      not used:240 *|   |                 
                 |   |> not used:142                    |   |                 
                 |   |> not used:143                    | 28|* not used       
                 |   |> not used:144                    |   |                 
                 |   |> not used:145      not used:242 *|   |                 
                 |   |> not used:146                    |   |                 
                 |   |> not used:147                    | 29|* not used       
                 |   |> not used:148                    |   |                 
                 |   |> not used:149      not used:244 *|   |                 
                 |   |> not used:150                    |   |                 
                 |   |> not used:151                    | 30|* not used       
                 |   |> not used:152                    |   |                 
                 |   |> not used:153      not used:246 *|   |                 
                 |   |> not used:154                    |   |                 
                 |   |> not used:155                    | 31|* not used       
                 |   |> not used:156                    |   |                 
                 |   |> not used:157      not used:248 *|   |                 
                 |   |> not used:158                    |   |                 
                 |   |> not used:159                    |   |                 
                 |   |> not used:160                    |   |                 
                 |   |> not used:161                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    3  |    8  |
                 | Buried Macrocells  |    0  |    8  |
                 | PIM Input Connects |    0  |   36  |
                 ______________________________________
                                           3  /   52   = 5   %


----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

LOGIC BLOCK D PLACEMENT   (01:58:49)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |sram_data_0
++X+++++++++++++................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2 |UNUSED
..........++++++++++++++++......................................................
| 3 |UNUSED
..............++++++++++++++++..................................................
| 4 |UNUSED
..................++++++++++++++++..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6 |sram_data_3
..........................X+++++++++++++++......................................
| 7 |UNUSED
..............................++++++++++++++++..................................
| 8 |sram_data_1
..................................X+++++++++++++++..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10 |sram_data_2
..........................................X+++++++++++++++......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12 |UNUSED
..................................................++++++++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14 |UNUSED
..........................................................++++++++++++++++......
|15 |UNUSED
................................................................++++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  4 
Total count of unique Product Terms  =  4 
Total Product Terms to be assigned   =  4 
Max Product Terms used / available   =   4 /  80   = 5.1  %


Control Signals for Logic Block D
---------------------------------
CLK pin  13 : /clk
CLK pin  35 : <not used>
PRESET      : GND
RESET       : GND
OE 0        : <not used>
OE 1        : <not used>
OE 2        : <not used>
OE 3        : <not used>



                              Logic Block D
                 ____________________________________________
                 |   |= >diff_0                         |   |                 
                 |   |> not used:163                    |   |                 
                 |   |> not used:164                    |   |                 
                 |   |> not used:165                    |   |                 
                 |   |= >diff_2                         | 36|= sram_data_0    
                 |   |> not used:167                    |   |                 
                 |   |> not used:168      not used:250 *|   |                 
                 |   |> not used:169                    |   |                 
                 |   |> not used:170                    | 37|* not used       
                 |   |> not used:171                    |   |                 
                 |   |> not used:172      not used:252 *|   |                 
                 |   |> not used:173                    |   |                 
                 |   |> not used:174                    | 38|* not used       
                 |   |= >diff_1                         |   |                 
                 |   |> not used:176      not used:254 *|   |                 
                 |   |= >diff_3                         |   |                 
                 |   |> not used:178                    | 39|= sram_data_3    
                 |   |> not used:179                    |   |                 
                 |   |> not used:180      not used:256 *|   |                 
                 |   |> not used:181                    |   |                 
                 |   |> not used:182                    | 40|= sram_data_1    
                 |   |> not used:183                    |   |                 
                 |   |> not used:184      not used:258 *|   |                 
                 |   |> not used:185                    |   |                 
                 |   |> not used:186                    | 41|= sram_data_2    
                 |   |> not used:187                    |   |                 
                 |   |> not used:188      not used:260 *|   |                 
                 |   |> not used:189                    |   |                 
                 |   |> not used:190                    | 42|* not used       
                 |   |> not used:191                    |   |                 
                 |   |> not used:192      not used:262 *|   |                 
                 |   |> not used:193                    |   |                 
                 |   |> not used:194                    | 43|* not used       
                 |   |> not used:195                    |   |                 
                 |   |> not used:196      not used:264 *|   |                 
                 |   |> not used:197                    |   |                 
                 |   |> not used:198                    |   |                 
                 |   |> not used:199                    |   |                 
                 |   |> not used:200                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    4  |    8  |
                 | Buried Macrocells  |    0  |    8  |
                 | PIM Input Connects |    4  |   36  |
                 ______________________________________
                                           8  /   52   = 15  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (01:58:49)


Device:  c372i
Package: CY7C372I-66JC

                  1  :  GND
                  2  :  sram_addr_low_0
                  3  :  Not Used
                  4  :  sram_addr_low_3
                  5  :  sram_addr_low_5
                  6  :  sram_addr_low_1
                  7  :  sram_addr_low_4
                  8  :  sram_addr_low_2
                  9  :  Not Used
                 10  :  diff_0
                 11  :  VPP
                 12  :  GND
                 13  :  clk
                 14  :  coladdr_in_5
                 15  :  coladdr_in_7
                 16  :  diff_3
                 17  :  Not Used
                 18  :  Not Used
                 19  :  Not Used
                 20  :  Not Used
                 21  :  Not Used
                 22  :  VCC
                 23  :  GND
                 24  :  coladdr_in_6
                 25  :  diff_2
                 26  :  coladdr_in_2
                 27  :  Not Used
                 28  :  Not Used
                 29  :  Not Used
                 30  :  Not Used
                 31  :  Not Used
                 32  :  diff_1
                 33  :  coladdr_in_3
                 34  :  GND
                 35  :  coladdr_in_4
                 36  :  sram_data_0
                 37  :  Not Used
                 38  :  Not Used
                 39  :  sram_data_3
                 40  :  sram_data_1
                 41  :  sram_data_2
                 42  :  Not Used
                 43  :  Not Used
                 44  :  VCC


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    3  |    3  |
                 | Clock/Inputs       |    2  |    2  |
                 | I/O Macrocells     |   16  |   32  |
                 | Buried Macrocells  |    0  |   32  |
                 | PIM Input Connects |   10  |  156  |
                 ______________________________________
                                          31  /  225   = 13  %



                                      Required     Max (Available)
          CLOCK/LATCH ENABLE signals     1            2
          Input REG/LATCH signals        0           36
          Input PIN signals              4            4
          Input PINs using I/O cells     6            6
          Output PIN signals            10           26


          Total PIN signals             21           37
          Macrocells Used               10           64
          Unique Product Terms          10          320



----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

PRESET/RESET AND OUTPUT ENABLE COMBINATIONS

PRESET: GND
RESET : GND
Used by Logic Blocks: AD
Total unique inputs =  10 
count of registered equations =  10 
==>OE: GND or VCC
   count of OE equations =  10 

----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

TIMING PATH ANALYSIS       (01:58:49) using Package: CY7C372I-66JC

Messages:

----------------------------------------------------------------------------
Signal Name | Delay Type  |   tmax   | Path Description
----------------------------------------------------------------------------
reg::sram_addr_low_0[2]
inp::coladdr_in_2
              tS              10.0 ns    1 pass
out::sram_addr_low_0
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::sram_addr_low_3[4]
inp::coladdr_in_5
              tS              10.0 ns    1 pass
out::sram_addr_low_3
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::sram_addr_low_5[5]
inp::coladdr_in_7
              tS              10.0 ns    1 pass
out::sram_addr_low_5
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::sram_addr_low_1[6]
inp::coladdr_in_3
              tS              10.0 ns    1 pass
out::sram_addr_low_1
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::sram_addr_low_4[7]
inp::coladdr_in_6
              tS              10.0 ns    1 pass
out::sram_addr_low_4
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::sram_addr_low_2[8]
inp::coladdr_in_4
              tS              10.0 ns    1 pass
out::sram_addr_low_2
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::sram_data_0[36]
inp::diff_0
              tS              10.0 ns    1 pass
out::sram_data_0
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::sram_data_3[39]
inp::diff_3
              tS              10.0 ns    1 pass
out::sram_data_3
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::sram_data_1[40]
inp::diff_1
              tS              10.0 ns    1 pass
out::sram_data_1
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::sram_data_2[41]
inp::diff_2
              tS              10.0 ns    1 pass
out::sram_data_2
              tCO             10.0 ns  
----------------------------------------------------------------------------

Worst Case Path Summary
-----------------------

                     tS = 10.0 ns for sram_addr_low_0.D
                    tCO = 10.0 ns for sram_addr_low_0.C



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

JEDEC ASSEMBLE             (01:58:49)

Messages:
  Information: Processing JEDEC for Logic Block 1.
  Information: Processing JEDEC for Logic Block 2.
  Information: Processing JEDEC for Logic Block 3.
  Information: Processing JEDEC for Logic Block 4.
  Information: JEDEC output file 'bucket.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 01:58:50
