
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x95
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|    1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  compare.vhd
Options:    -e10 -w100 -o1 -yga -fP -v0 -dc20v8 -pPALCE20V8-7PC compare.vhd
======================================================================

vhdlfe V4 IR x95:  VHDL parser
Tue May 11 01:59:42 1999

Library 'work' => directory 'lc20v8'
Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/mit/6.111/warp4.3/lib/ieee/work'
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.

vhdlfe:  No errors.


tovif V4 IR x95:  High-level synthesis
Tue May 11 01:59:43 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.

tovif:  No errors.


topld V4 IR x96:  Synthesis and optimization
Tue May 11 01:59:43 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------



------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 0 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------
Skipping virtual substitution
----------------------------------------------------------
Created 19 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN HEADER INFORMATION  (01:59:44)

Input File(s): compare.pla
Device       : c20v8
Package      : PALCE20V8-7PC
ReportFile   : compare.rpt

Program Controls:
                 None.

Signal Requests:
    GROUP FAST_SLEW ALL

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (01:59:44)

Messages:
  Information: Optimizing logic using best output polarity for signals:
         upper lower

  Information: Selected logic optimization OFF for signals:
         dout



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     11/NOV/97    [v4.02 ] 4 IR x95

LOGIC MINIMIZATION         (01:59:44)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (01:59:45)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN EQUATIONS           (01:59:45)


    dout =
          lower * upper 

    /upper =
          din1_4 * /din2_4 
        + /din1_4 * din2_4 
        + din1_5 * /din2_5 
        + /din1_5 * din2_5 
        + din1_6 * /din2_6 
        + /din1_6 * din2_6 
        + din1_7 * /din2_7 
        + /din1_7 * din2_7 

    /lower =
          din1_0 * /din2_0 
        + /din1_0 * din2_0 
        + din1_1 * /din2_1 
        + /din1_1 * din2_1 
        + din1_2 * /din2_2 
        + /din1_2 * din2_2 
        + din1_3 * /din2_3 
        + /din1_3 * din2_3 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN RULE CHECK          (01:59:45)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (01:59:45)

Messages:
  Information: Checking for duplicate NODE logic.
                 None.


                                 C20V8B
                 __________________________________________
         din2_0 =| 1|                                  |24|* not used       
         din2_1 =| 2|                                  |23|* not used       
         din2_2 =| 3|                                  |22|= dout           
         din2_3 =| 4|                                  |21|= lower          
         din2_4 =| 5|                                  |20|= upper          
         din2_5 =| 6|                                  |19|* not used       
         din2_6 =| 7|                                  |18|* not used       
         din2_7 =| 8|                                  |17|= din1_7         
         din1_0 =| 9|                                  |16|= din1_6         
         din1_1 =|10|                                  |15|= din1_5         
         din1_2 =|11|                                  |14|= din1_4         
       not used *|12|                                  |13|= din1_3         
                 __________________________________________


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

RESOURCE ALLOCATION        (01:59:45)

  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |   13  |   14  |
                 | Output Macrocells  |    0  |    2  |
                 | I/O Macrocells     |    6  |    6  |
                 ______________________________________
                                          19  /   22   = 86  %


  Information: Output Logic Product Term Utilization.

                  Node#  Output Signal Name  Used   Max
                 ________________________________________
                 | 15  |  Used As Input   |   0  |   8  |
                 | 16  |  Used As Input   |   0  |   8  |
                 | 17  |  Used As Input   |   0  |   8  |
                 | 18  |  Unused          |   0  |   8  |
                 | 19  |  Unused          |   0  |   8  |
                 | 20  |  upper           |   8  |   8  |
                 | 21  |  lower           |   8  |   8  |
                 | 22  |  dout            |   1  |   8  |
                 ________________________________________
                                             17  /  64   = 26  %


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

JEDEC ASSEMBLE             (01:59:45)

Messages:
  Information: Output file 'compare.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 01:59:45
