
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x95
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|    1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  count9_row.vhd
Options:    -m -o2 -ygs -fP -v10 -dc22v10 -pPALCE22V10-25PC/PI count9_row.vhd
======================================================================

vhdlfe V4 IR x95:  VHDL parser
Mon May  3 23:01:07 1999

Library 'work' => directory 'lc22v10'
Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/mit/6.111/warp4.3/lib/ieee/work'
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
count9_row.vhd (line 39, col 24):  Note: Substituting module 'add_vi_us' for '+'.
count9_row.vhd (line 44, col 26):  Note: Substituting module 'cmp_vi_us' for '='.

vhdlfe:  No errors.


tovif V4 IR x95:  High-level synthesis
Mon May  3 23:01:07 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.

tovif:  No errors.


topld V4 IR x96:  Synthesis and optimization
Mon May  3 23:01:09 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
Linking '/mit/6.111/warp4.3/lib/lc22v10/stdlogic/c22v10.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------



------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 43 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

----------------------------------------------------------
Circuit simplification results:

	Expanded 23 signals.
	Turned 0 signals into soft nodes.
	Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 99 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN HEADER INFORMATION  (23:01:11)

Input File(s): count9_row.pla
Device       : C22V10
Package      : PALCE22V10-25PC/PI
ReportFile   : count9_row.rpt

Program Controls:
                 None.

Signal Requests:
    GROUP FAST_SLEW ALL

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (23:01:11)

Messages:
  Information: Process virtual 'count_0D' ... expanded.
  Information: Process virtual 'count_1D' ... expanded.
  Information: Process virtual 'count_2D' ... expanded.
  Information: Process virtual 'count_3D' ... expanded.
  Information: Process virtual 'count_4D' ... expanded.
  Information: Process virtual 'count_5D' ... expanded.
  Information: Process virtual 'count_6D' ... expanded.
  Information: Process virtual 'count_7D' ... expanded.
  Information: Process virtual 'n_fullD' ... expanded.
  Information: Process virtual 'count_0' ... expanded.
  Information: Process virtual 'count_1' ... expanded.
  Information: Process virtual 'count_2' ... expanded.
  Information: Process virtual 'count_3' ... expanded.
  Information: Process virtual 'count_4' ... expanded.
  Information: Process virtual 'count_5' ... expanded.
  Information: Process virtual 'count_6' ... expanded.
  Information: Process virtual 'count_7' ... expanded.
  Information: Optimizing logic using best output polarity for signals:
         n_full.D cnt_out_8.D cnt_out_7.D cnt_out_6.D cnt_out_5.D cnt_out_4.D
         cnt_out_3.D cnt_out_2.D cnt_out_1.D

  Information: Selected logic optimization OFF for signals:
         n_full.C cnt_out_8.C cnt_out_8.OE cnt_out_7.C cnt_out_7.OE
         cnt_out_6.C cnt_out_6.OE cnt_out_5.C cnt_out_5.OE cnt_out_4.C
         cnt_out_4.OE cnt_out_3.C cnt_out_3.OE cnt_out_2.C cnt_out_2.OE
         cnt_out_1.C cnt_out_1.OE cnt_out_0 cnt_out_0.OE



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     11/NOV/97    [v4.02 ] 4 IR x95

LOGIC MINIMIZATION         (23:01:12)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (23:01:12)

Messages:
  Information: Optimizing Banked Preset/Reset requirements.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN EQUATIONS           (23:01:12)


    /n_full.D =
          n_clr * /cnt_out_1.Q * cnt_out_2.Q * /cnt_out_3.Q * cnt_out_4.Q * 
          cnt_out_5.Q * cnt_out_6.Q * cnt_out_7.Q * cnt_out_8.Q 
        + n_clr * /n_full.Q 

    n_full.AR =
          GND

    n_full.SP =
          GND

    n_full.C =
          clk 

    cnt_out_8.D =
          n_clr * /n_cnten * cnt_out_1.Q * cnt_out_2.Q * cnt_out_3.Q * 
          cnt_out_4.Q * cnt_out_5.Q * cnt_out_6.Q * cnt_out_7.Q * 
          /cnt_out_8.Q 
        + n_clr * /cnt_out_7.Q * cnt_out_8.Q 
        + n_clr * /cnt_out_6.Q * cnt_out_8.Q 
        + n_clr * /cnt_out_5.Q * cnt_out_8.Q 
        + n_clr * /cnt_out_4.Q * cnt_out_8.Q 
        + n_clr * /cnt_out_3.Q * cnt_out_8.Q 
        + n_clr * /cnt_out_2.Q * cnt_out_8.Q 
        + n_clr * /cnt_out_1.Q * cnt_out_8.Q 
        + n_clr * n_cnten * cnt_out_8.Q 

    cnt_out_8.AR =
          GND

    cnt_out_8.SP =
          GND

    cnt_out_8.C =
          clk 

    cnt_out_8.OE =
          /n_oe 

    cnt_out_7.D =
          n_clr * /n_cnten * cnt_out_1.Q * cnt_out_2.Q * cnt_out_3.Q * 
          cnt_out_4.Q * cnt_out_5.Q * cnt_out_6.Q * /cnt_out_7.Q 
        + n_clr * /cnt_out_6.Q * cnt_out_7.Q 
        + n_clr * /cnt_out_5.Q * cnt_out_7.Q 
        + n_clr * /cnt_out_4.Q * cnt_out_7.Q 
        + n_clr * /cnt_out_3.Q * cnt_out_7.Q 
        + n_clr * /cnt_out_2.Q * cnt_out_7.Q 
        + n_clr * /cnt_out_1.Q * cnt_out_7.Q 
        + n_clr * n_cnten * cnt_out_7.Q 

    cnt_out_7.AR =
          GND

    cnt_out_7.SP =
          GND

    cnt_out_7.C =
          clk 

    cnt_out_7.OE =
          /n_oe 

    cnt_out_6.D =
          n_clr * /n_cnten * cnt_out_1.Q * cnt_out_2.Q * cnt_out_3.Q * 
          cnt_out_4.Q * cnt_out_5.Q * /cnt_out_6.Q 
        + n_clr * /cnt_out_5.Q * cnt_out_6.Q 
        + n_clr * /cnt_out_4.Q * cnt_out_6.Q 
        + n_clr * /cnt_out_3.Q * cnt_out_6.Q 
        + n_clr * /cnt_out_2.Q * cnt_out_6.Q 
        + n_clr * /cnt_out_1.Q * cnt_out_6.Q 
        + n_clr * n_cnten * cnt_out_6.Q 

    cnt_out_6.AR =
          GND

    cnt_out_6.SP =
          GND

    cnt_out_6.C =
          clk 

    cnt_out_6.OE =
          /n_oe 

    cnt_out_5.D =
          n_clr * /n_cnten * cnt_out_1.Q * cnt_out_2.Q * cnt_out_3.Q * 
          cnt_out_4.Q * /cnt_out_5.Q 
        + n_clr * /cnt_out_4.Q * cnt_out_5.Q 
        + n_clr * /cnt_out_3.Q * cnt_out_5.Q 
        + n_clr * /cnt_out_2.Q * cnt_out_5.Q 
        + n_clr * /cnt_out_1.Q * cnt_out_5.Q 
        + n_clr * n_cnten * cnt_out_5.Q 

    cnt_out_5.AR =
          GND

    cnt_out_5.SP =
          GND

    cnt_out_5.C =
          clk 

    cnt_out_5.OE =
          /n_oe 

    cnt_out_4.D =
          n_clr * /n_cnten * cnt_out_1.Q * cnt_out_2.Q * cnt_out_3.Q * 
          /cnt_out_4.Q 
        + n_clr * /cnt_out_3.Q * cnt_out_4.Q 
        + n_clr * /cnt_out_2.Q * cnt_out_4.Q 
        + n_clr * /cnt_out_1.Q * cnt_out_4.Q 
        + n_clr * n_cnten * cnt_out_4.Q 

    cnt_out_4.AR =
          GND

    cnt_out_4.SP =
          GND

    cnt_out_4.C =
          clk 

    cnt_out_4.OE =
          /n_oe 

    cnt_out_3.D =
          n_clr * /n_cnten * cnt_out_1.Q * cnt_out_2.Q * /cnt_out_3.Q 
        + n_clr * /cnt_out_2.Q * cnt_out_3.Q 
        + n_clr * /cnt_out_1.Q * cnt_out_3.Q 
        + n_clr * n_cnten * cnt_out_3.Q 

    cnt_out_3.AR =
          GND

    cnt_out_3.SP =
          GND

    cnt_out_3.C =
          clk 

    cnt_out_3.OE =
          /n_oe 

    cnt_out_2.D =
          n_clr * /n_cnten * cnt_out_1.Q * /cnt_out_2.Q 
        + n_clr * /cnt_out_1.Q * cnt_out_2.Q 
        + n_clr * n_cnten * cnt_out_2.Q 

    cnt_out_2.AR =
          GND

    cnt_out_2.SP =
          GND

    cnt_out_2.C =
          clk 

    cnt_out_2.OE =
          /n_oe 

    cnt_out_1.D =
          n_clr * /n_cnten * /cnt_out_1.Q 
        + n_clr * n_cnten * cnt_out_1.Q 

    cnt_out_1.AR =
          GND

    cnt_out_1.SP =
          GND

    cnt_out_1.C =
          clk 

    cnt_out_1.OE =
          /n_oe 

    cnt_out_0 =
          oddeven 

    cnt_out_0.OE =
          /n_oe 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN RULE CHECK          (23:01:12)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (23:01:12)

Messages:
  Information: All signals pre-placed in user design.


                                 C22V10
                 __________________________________________
            clk =| 1|                                  |24|* not used       
          n_clr =| 2|                                  |23|= cnt_out_0      
        n_cnten =| 3|                                  |22|= cnt_out_1      
           n_oe =| 4|                                  |21|= cnt_out_2      
       not used *| 5|                                  |20|= cnt_out_3      
       not used *| 6|                                  |19|= cnt_out_4      
       not used *| 7|                                  |18|= cnt_out_5      
       not used *| 8|                                  |17|= cnt_out_6      
       not used *| 9|                                  |16|= cnt_out_7      
       not used *|10|                                  |15|= cnt_out_8      
        oddeven =|11|                                  |14|= n_full         
       not used *|12|                                  |13|* not used       
                 __________________________________________


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
  Information: Checking for duplicate NODE logic.
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

RESOURCE ALLOCATION        (23:01:12)

  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    4  |   11  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |   10  |   10  |
                 ______________________________________
                                          15  /   22   = 68  %


  Information: Output Logic Product Term Utilization.

                  Node#  Output Signal Name  Used   Max
                 ________________________________________
                 | 14  |  n_full          |   2  |   8  |
                 | 15  |  cnt_out_8       |   9  |  10  |
                 | 16  |  cnt_out_7       |   8  |  12  |
                 | 17  |  cnt_out_6       |   7  |  14  |
                 | 18  |  cnt_out_5       |   6  |  16  |
                 | 19  |  cnt_out_4       |   5  |  16  |
                 | 20  |  cnt_out_3       |   4  |  14  |
                 | 21  |  cnt_out_2       |   3  |  12  |
                 | 22  |  cnt_out_1       |   2  |  10  |
                 | 23  |  cnt_out_0       |   1  |   8  |
                 | 25  |  Unused          |   0  |   1  |
                 ________________________________________
                                             47  / 121   = 38  %


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

JEDEC ASSEMBLE             (23:01:12)

Messages:
  Information: Output file 'count9_row.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 23:01:12
