
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x95
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|    1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  diffctl.vhd
Options:    -m -o2 -ygs -fP -v10 -dc20v8 -pPALCE20V8-25PC diffctl.vhd
======================================================================

vhdlfe V4 IR x95:  VHDL parser
Mon May  3 23:03:03 1999

Library 'work' => directory 'lc20v8'
Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/mit/6.111/warp4.3/lib/ieee/work'
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
diffctl.vhd (line 44, col 44):  Note: Substituting module 'cmp_vv_us' for '/='.
diffctl.vhd (line 45, col 24):  Note: Substituting module 'add_vi_us' for '+'.
diffctl.vhd (line 48, col 42):  Note: Substituting module 'cmp_vv_us' for '/='.

vhdlfe:  No errors.


tovif V4 IR x95:  High-level synthesis
Mon May  3 23:03:04 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.

tovif:  No errors.


topld V4 IR x96:  Synthesis and optimization
Mon May  3 23:03:05 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
Linking '/mit/6.111/warp4.3/lib/lc16v8/stdlogic/c16v8.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------



------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 6 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

----------------------------------------------------------
Circuit simplification results:

	Expanded 7 signals.
	Turned 0 signals into soft nodes.
	Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 32 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN HEADER INFORMATION  (23:03:07)

Input File(s): diffctl.pla
Device       : c20v8
Package      : PALCE20V8-25PC
ReportFile   : diffctl.rpt

Program Controls:
                 None.

Signal Requests:
    GROUP FAST_SLEW ALL

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (23:03:07)

Messages:
  Information: Process virtual 'count_0D' ... expanded.
  Information: Process virtual 'count_1D' ... expanded.
  Information: Process virtual 'cycle_0D' ... expanded.
  Information: Process virtual 'cycle_1D' ... expanded.
  Information: Process virtual 'cycle_2D' ... expanded.
  Information: Process virtual 'cycle_3D' ... expanded.
  Information: Process virtual 'dram_n_rasD' ... expanded.
  Information: Optimizing logic using best output polarity for signals:
         count_1.D count_0.D cycle_3.D cycle_2.D cycle_1.D cycle_0.D
         dram_n_ras.D

  Information: Selected logic optimization OFF for signals:
         count_1.C count_0.C cycle_3.C cycle_2.C cycle_1.C cycle_0.C
         dram_n_ras.C



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     11/NOV/97    [v4.02 ] 4 IR x95

LOGIC MINIMIZATION         (23:03:07)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (23:03:07)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN EQUATIONS           (23:03:07)


    count_1.D =
          count_1.Q * /count_0.Q * hdrive 
        + /count_1.Q * count_0.Q * hdrive 

    count_1.C =
          clk 

    /count_0.D =
          /cblank * /count_1.Q * hdrive 
        + count_0.Q * hdrive 

    count_0.C =
          clk 

    /cycle_3.D =
          cblank * count_1.Q * count_0.Q * row_n_full * col_n_full 

    cycle_3.C =
          clk 

    /cycle_2.D =
          cblank * count_1.Q * /count_0.Q * row_n_full * col_n_full 

    cycle_2.C =
          clk 

    /cycle_1.D =
          cblank * /count_1.Q * count_0.Q * row_n_full * col_n_full 

    cycle_1.C =
          clk 

    /cycle_0.D =
          cblank * /count_1.Q * /count_0.Q * row_n_full * col_n_full 

    cycle_0.C =
          clk 

    dram_n_ras.D =
          /cblank * count_0.Q 
        + /cblank * count_1.Q 

    dram_n_ras.C =
          clk 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN RULE CHECK          (23:03:07)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (23:03:07)

Messages:
  Information: All signals pre-placed in user design.


                                 C20V8C
                 __________________________________________
            clk =| 1|                                  |24|* not used       
         hdrive =| 2|                                  |23|* not used       
         cblank =| 3|                                  |22|= dram_n_ras     
       not used *| 4|                                  |21|= cycle_0        
       not used *| 5|                                  |20|= cycle_1        
       not used *| 6|                                  |19|= cycle_2        
       not used *| 7|                                  |18|= cycle_3        
       not used *| 8|                                  |17|= count_0        
       not used *| 9|                                  |16|= count_1        
     row_n_full =|10|                                  |15|* not used       
     col_n_full =|11|                                  |14|* not used       
       not used *|12|                                  |13|* not used       
                 __________________________________________


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
  Information: Checking for duplicate NODE logic.
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

RESOURCE ALLOCATION        (23:03:07)

  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    4  |   12  |
                 | Clock/Inputs       |    1  |    1  |
                 | Enable/Inputs      |    0  |    1  |
                 | Output Macrocells  |    7  |    8  |
                 ______________________________________
                                          12  /   22   = 54  %


  Information: Output Logic Product Term Utilization.

                  Node#  Output Signal Name  Used   Max
                 ________________________________________
                 | 15  |  Unused          |   0  |   8  |
                 | 16  |  count_1         |   2  |   8  |
                 | 17  |  count_0         |   2  |   8  |
                 | 18  |  cycle_3         |   1  |   8  |
                 | 19  |  cycle_2         |   1  |   8  |
                 | 20  |  cycle_1         |   1  |   8  |
                 | 21  |  cycle_0         |   1  |   8  |
                 | 22  |  dram_n_ras      |   2  |   8  |
                 ________________________________________
                                             10  /  64   = 15  %


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

JEDEC ASSEMBLE             (23:03:07)

Messages:
  Information: Output file 'diffctl.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 23:03:08
