
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x95
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|    1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  count8-diffctl.vhd
Options:    -m -e10 -w100 -o2 -ygs -fP -v10 -dc22v10 -pPALCE22V10-25PC/PI count8-diffctl.vhd
======================================================================

vhdlfe V4 IR x95:  VHDL parser
Sun May  9 14:00:15 1999

Library 'work' => directory 'lc22v10'
Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/mit/6.111/warp4.3/lib/ieee/work'
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
count8-diffctl.vhd (line 44, col 25):  Note: Substituting module 'add_vi_us' for '+'.
count8-diffctl.vhd (line 50, col 28):  Note: Substituting module 'cmp_vv_us' for '/='.
count8-diffctl.vhd (line 56, col 25):  Note: Substituting module 'cmp_vv_us' for '='.
count8-diffctl.vhd (line 56, col 40):  Note: Substituting module 'cmp_vv_us' for '='.
count8-diffctl.vhd (line 56, col 57):  Note: Substituting module 'cmp_vv_us' for '='.
count8-diffctl.vhd (line 62, col 27):  Note: Substituting module 'cmp_vv_us' for '='.
count8-diffctl.vhd (line 68, col 25):  Note: Substituting module 'cmp_vv_us' for '='.
count8-diffctl.vhd (line 68, col 40):  Note: Substituting module 'cmp_vv_us' for '='.
count8-diffctl.vhd (line 68, col 57):  Note: Substituting module 'cmp_vv_us' for '='.
count8-diffctl.vhd (line 69, col 10):  Note: Substituting module 'cmp_vv_us' for '='.
count8-diffctl.vhd (line 75, col 27):  Note: Substituting module 'cmp_vv_us' for '='.
count8-diffctl.vhd (line 81, col 27):  Note: Substituting module 'cmp_vv_us' for '='.

vhdlfe:  No errors.


tovif V4 IR x95:  High-level synthesis
Sun May  9 14:00:23 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.

tovif:  No errors.


topld V4 IR x96:  Synthesis and optimization
Sun May  9 14:00:32 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
Linking '/mit/6.111/warp4.3/lib/lc22v10/stdlogic/c22v10.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------



------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 39 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

----------------------------------------------------------
Circuit simplification results:

	Expanded 24 signals.
	Turned 0 signals into soft nodes.
	Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 87 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN HEADER INFORMATION  (14:00:39)

Input File(s): count8-diffctl.pla
Device       : C22V10
Package      : PALCE22V10-25PC/PI
ReportFile   : count8-diffctl.rpt

Program Controls:
                 None.

Signal Requests:
    GROUP FAST_SLEW ALL

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (14:00:40)

Messages:
  Information: Process virtual 'count_0D' ... expanded.
  Information: Process virtual 'count_1D' ... expanded.
  Information: Process virtual 'count_2D' ... expanded.
  Information: Process virtual 'diff_final_enD' ... expanded.
  Information: Process virtual 'diff_old_en_colcntD' ... expanded.
  Information: Process virtual 'a2d_n_oeD' ... expanded.
  Information: Process virtual 'dram_n_weD' ... expanded.
  Information: Process virtual 'dram_n_oeD' ... expanded.
  Information: Process virtual 'dram_n_casD' ... expanded.
  Information: Optimizing logic using best output polarity for signals:
         diff_final_en.D diff_old_en_colcnt.D a2d_n_oe.D dram_n_we.D
         dram_n_oe.D dram_n_cas.D count_0.D count_1.D count_2.D

  Information: Selected logic optimization OFF for signals:
         diff_final_en.C diff_old_en_colcnt.C a2d_n_oe.C dram_n_we.C
         dram_n_oe.C dram_n_cas.C dram_n_ras.D dram_n_ras.C count_0.C
         count_1.C count_2.C



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     11/NOV/97    [v4.02 ] 4 IR x95

LOGIC MINIMIZATION         (14:00:42)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (14:00:43)

Messages:
  Information: Optimizing Banked Preset/Reset requirements.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN EQUATIONS           (14:00:46)


    /diff_final_en.D =
          cblank * row_n_full * col_n_full * count_2.Q * count_1.Q * 
          count_0.Q 

    diff_final_en.AR =
          GND

    diff_final_en.SP =
          GND

    diff_final_en.C =
          clk 

    /diff_old_en_colcnt.D =
          cblank * row_n_full * col_n_full * /count_2.Q * count_1.Q * 
          /count_0.Q 

    diff_old_en_colcnt.AR =
          GND

    diff_old_en_colcnt.SP =
          GND

    diff_old_en_colcnt.C =
          clk 

    /a2d_n_oe.D =
          cblank * row_n_full * col_n_full * count_2.Q 

    a2d_n_oe.AR =
          GND

    a2d_n_oe.SP =
          GND

    a2d_n_oe.C =
          clk 

    /dram_n_we.D =
          cblank * row_n_full * col_n_full * count_2.Q * count_1.Q * 
          /count_0.Q 

    dram_n_we.AR =
          GND

    dram_n_we.SP =
          GND

    dram_n_we.C =
          clk 

    /dram_n_oe.D =
          cblank * row_n_full * col_n_full * /count_2.Q * count_0.Q 
        + cblank * row_n_full * col_n_full * /count_2.Q * count_1.Q 

    dram_n_oe.AR =
          GND

    dram_n_oe.SP =
          GND

    dram_n_oe.C =
          clk 

    /dram_n_cas.D =
          cblank * row_n_full * col_n_full * /count_2.Q 
        + cblank * row_n_full * col_n_full * /count_0.Q 
        + cblank * row_n_full * col_n_full * /count_1.Q 

    dram_n_cas.AR =
          GND

    dram_n_cas.SP =
          GND

    dram_n_cas.C =
          clk 

    dram_n_ras.D =
          hdrive 

    dram_n_ras.AR =
          GND

    dram_n_ras.SP =
          GND

    dram_n_ras.C =
          clk 

    count_2.D =
          /count_2.Q * count_1.Q * count_0.Q * hdrive 
        + count_2.Q * /count_0.Q * hdrive 
        + count_2.Q * /count_1.Q * hdrive 
        + /cblank * hdrive 

    count_2.AR =
          GND

    count_2.SP =
          GND

    count_2.C =
          clk 

    count_1.D =
          count_1.Q * /count_0.Q * hdrive 
        + /count_1.Q * count_0.Q * hdrive 
        + /cblank * hdrive 

    count_1.AR =
          GND

    count_1.SP =
          GND

    count_1.C =
          clk 

    /count_0.D =
          cblank * count_0.Q * hdrive 

    count_0.AR =
          GND

    count_0.SP =
          GND

    count_0.C =
          clk 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN RULE CHECK          (14:00:46)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (14:00:46)

Messages:
  Information: Checking for duplicate NODE logic.
                 None.


                                 C22V10
                 __________________________________________
            clk =| 1|                                  |24|* not used       
         hdrive =| 2|                                  |23|= count_1        
         cblank =| 3|                                  |22|= dram_n_ras     
       not used *| 4|                                  |21|= dram_n_cas     
       not used *| 5|                                  |20|= dram_n_oe      
       not used *| 6|                                  |19|= dram_n_we      
       not used *| 7|                                  |18|= a2d_n_oe       
       not used *| 8|                                  |17|= diff_old_en_.. 
       not used *| 9|                                  |16|= diff_final_en  
     row_n_full =|10|                                  |15|= count_0        
     col_n_full =|11|                                  |14|= count_2        
       not used *|12|                                  |13|* not used       
                 __________________________________________


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

RESOURCE ALLOCATION        (14:00:46)

  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    4  |   11  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |   10  |   10  |
                 ______________________________________
                                          15  /   22   = 68  %


  Information: Output Logic Product Term Utilization.

                  Node#  Output Signal Name  Used   Max
                 ________________________________________
                 | 14  |  count_2         |   4  |   8  |
                 | 15  |  count_0         |   1  |  10  |
                 | 16  |  diff_final_en   |   1  |  12  |
                 | 17  |  diff_old_en_..  |   1  |  14  |
                 | 18  |  a2d_n_oe        |   1  |  16  |
                 | 19  |  dram_n_we       |   1  |  16  |
                 | 20  |  dram_n_oe       |   2  |  14  |
                 | 21  |  dram_n_cas      |   3  |  12  |
                 | 22  |  dram_n_ras      |   1  |  10  |
                 | 23  |  count_1         |   3  |   8  |
                 | 25  |  Unused          |   0  |   1  |
                 ________________________________________
                                             18  / 121   = 14  %


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

JEDEC ASSEMBLE             (14:00:47)

Messages:
  Information: Output file 'count8-diffctl.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 14:00:47
