
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x95
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|    1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  ballx.vhd
Options:    -e10 -w100 -o2 -yga -fP -v10 -dc20v8 -pPALCE20V8-25PC ballx.vhd
======================================================================

vhdlfe V4 IR x95:  VHDL parser
Fri May  7 19:20:38 1999

Library 'work' => directory 'lc20v8'
Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/mit/6.111/warp4.3/lib/ieee/work'
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
ballx.vhd (line 40, col 34):  Note: Substituting module 'add_vv_us' for '+'.

vhdlfe:  No errors.


tovif V4 IR x95:  High-level synthesis
Fri May  7 19:20:39 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/madd_sub.vif'.

tovif:  No errors.


topld V4 IR x96:  Synthesis and optimization
Fri May  7 19:20:42 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/madd_sub.vif'.
Linking '/mit/6.111/warp4.3/lib/lc16v8/stdlogic/c16v8.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------


Deleted 0 User equations/components.
Deleted 0 Synthesized equations/components.

------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 15 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

----------------------------------------------------------
Circuit simplification results:

	Expanded 4 signals.
	Turned 0 signals into soft nodes.
	Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 46 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN HEADER INFORMATION  (19:20:44)

Input File(s): ballx.pla
Device       : c20v8
Package      : PALCE20V8-25PC
ReportFile   : ballx.rpt

Program Controls:
                 None.

Signal Requests:
    GROUP FAST_SLEW ALL

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (19:20:44)

Messages:
  Information: Process virtual 'MODULE_1_g1_a0_g0_u0_ci_2' ... expanded.
  Information: Process virtual 'rand_1D' ... expanded.
  Information: Process virtual 'MODIN2_0D' ... expanded.
  Information: Process virtual 'MODIN2_1D' ... expanded.
  Information: Process virtual 'count_0D' ... expanded.
  Information: Process virtual 'count_1D' ... expanded.
  Information: Process virtual 'count_2D' ... expanded.
  Information: Process virtual 'MODULE_1_g1_a0_g0_u0_c_0' ... expanded.
  Information: Process virtual 'rand_0' ... converted to NODE.
  Information: Process virtual 'rand_1' ... converted to NODE.
  Information: Process virtual 'MODIN2_0' ... converted to NODE.
  Information: Process virtual 'MODIN2_1' ... converted to NODE.
  Information: Process virtual 'count_0' ... expanded.
  Information: Process virtual 'count_1' ... expanded.
  Information: Process virtual 'count_2' ... expanded.
  Information: Optimizing logic using best output polarity for signals:
         cnt_out_2.D cnt_out_1.D cnt_out_0.D rand_1.D MODIN2_0.D MODIN2_1.D
         MODULE_1_g1_a0_g0_u0_ga_g1_ua0

  Information: Selected logic optimization OFF for signals:
         cnt_out_2.C cnt_out_2.OE cnt_out_1.C cnt_out_1.OE cnt_out_0.C
         cnt_out_0.OE rand_0.D rand_0.C rand_1.C MODIN2_0.C MODIN2_1.C



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     11/NOV/97    [v4.02 ] 4 IR x95

LOGIC MINIMIZATION         (19:20:45)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (19:20:45)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN EQUATIONS           (19:20:45)


    cnt_out_2.D =
          MODULE_1_g1_a0_g0_u0_ga_g1_ua0 * /clr * /n_cnt * /cnt_out_2.Q 
        + /clr * n_cnt * cnt_out_2.Q 
        + /MODULE_1_g1_a0_g0_u0_ga_g1_ua0 * /clr * cnt_out_2.Q 

    cnt_out_2.C =
          clk 

    cnt_out_2.OE =
          /n_oe 

    cnt_out_1.D =
          /MODIN2_1.Q * MODIN2_0.Q * /clr * /n_cnt * cnt_out_0.Q * 
          /cnt_out_1.Q 
        + MODIN2_1.Q * /clr * /n_cnt * /cnt_out_0.Q * /cnt_out_1.Q 
        + MODIN2_1.Q * /MODIN2_0.Q * /clr * /n_cnt * /cnt_out_1.Q 
        + MODIN2_1.Q * MODIN2_0.Q * /clr * cnt_out_0.Q * cnt_out_1.Q 
        + /MODIN2_1.Q * /clr * /cnt_out_0.Q * cnt_out_1.Q 
        + /MODIN2_1.Q * /MODIN2_0.Q * /clr * cnt_out_1.Q 
        + /clr * n_cnt * cnt_out_1.Q 

    cnt_out_1.C =
          clk 

    cnt_out_1.OE =
          /n_oe 

    cnt_out_0.D =
          MODIN2_0.Q * /clr * /n_cnt * /cnt_out_0.Q 
        + /clr * n_cnt * cnt_out_0.Q 
        + /MODIN2_0.Q * /clr * cnt_out_0.Q 

    cnt_out_0.C =
          clk 

    cnt_out_0.OE =
          /n_oe 

    rand_0.D =
          rand_in 

    rand_0.C =
          clk 

    MODIN2_1.D =
          incr_load * rand_1.Q 
        + MODIN2_1.Q * /incr_load 

    MODIN2_1.C =
          clk 

    MODIN2_0.D =
          incr_load * rand_0.Q 
        + MODIN2_0.Q * /incr_load 

    MODIN2_0.C =
          clk 

    rand_1.D =
          rand_1.Q * /rand_in 
        + rand_0.Q 

    rand_1.C =
          clk 

    MODULE_1_g1_a0_g0_u0_ga_g1_ua0 =
          MODIN2_0.Q * cnt_out_0.Q * cnt_out_1.Q 
        + MODIN2_1.Q * MODIN2_0.Q * cnt_out_0.Q 
        + MODIN2_1.Q * cnt_out_1.Q 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN RULE CHECK          (19:20:45)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (19:20:45)

Messages:
  Information: Checking for duplicate NODE logic.
                 None.


                                 C20V8C
                 __________________________________________
            clk =| 1|                                  |24|* not used       
            clr =| 2|                                  |23|* not used       
          n_cnt =| 3|                                  |22|= cnt_out_0      
       not used *| 4|                                  |21|= cnt_out_1      
      incr_load =| 5|                                  |20|= cnt_out_2      
        rand_in =| 6|                                  |19|= (rand_0)       
       not used *| 7|                                  |18|= (MODIN2_1)     
       not used *| 8|                                  |17|= (MODIN2_0)     
       not used *| 9|                                  |16|= (rand_1)       
       not used *|10|                                  |15|= (MODULE_1_g1.. 
       not used *|11|                                  |14|* not used       
       not used *|12|                                  |13|= n_oe           
                 __________________________________________


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

RESOURCE ALLOCATION        (19:20:45)

  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    4  |   12  |
                 | Clock/Inputs       |    1  |    1  |
                 | Enable/Inputs      |    1  |    1  |
                 | Output Macrocells  |    8  |    8  |
                 ______________________________________
                                          14  /   22   = 63  %


  Information: Output Logic Product Term Utilization.

                  Node#  Output Signal Name  Used   Max
                 ________________________________________
                 | 15  |  MODULE_1_g1_..  |   3  |   8  |
                 | 16  |  rand_1          |   2  |   8  |
                 | 17  |  MODIN2_0        |   2  |   8  |
                 | 18  |  MODIN2_1        |   2  |   8  |
                 | 19  |  rand_0          |   1  |   8  |
                 | 20  |  cnt_out_2       |   3  |   8  |
                 | 21  |  cnt_out_1       |   7  |   8  |
                 | 22  |  cnt_out_0       |   3  |   8  |
                 ________________________________________
                                             23  /  64   = 35  %


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

JEDEC ASSEMBLE             (19:20:45)

Messages:
  Information: Output file 'ballx.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 19:20:46
