
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x95
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|    1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  boundaryx.vhd
Options:    -m -e10 -w100 -o2 -yga -fP -v1 -dc22v10 -pPALCE22V10-25PC/PI boundaryx.vhd
======================================================================

vhdlfe V4 IR x95:  VHDL parser
Fri May  7 20:32:41 1999

Library 'work' => directory 'lc22v10'
Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/mit/6.111/warp4.3/lib/ieee/work'
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
boundaryx.vhd (line 32, col 53):  Note: Substituting module 'add_vv_us' for '+'.
boundaryx.vhd (line 32, col 53):  Note: Substituting module 'cmp_vv_us' for '='.
boundaryx.vhd (line 37, col 27):  Note: Substituting module 'add_vi_us' for '+'.

vhdlfe:  No errors.


tovif V4 IR x95:  High-level synthesis
Fri May  7 20:32:43 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/madd_sub.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mcompare.vif'.

tovif:  No errors.


topld V4 IR x96:  Synthesis and optimization
Fri May  7 20:32:47 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/madd_sub.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mcompare.vif'.
Linking '/mit/6.111/warp4.3/lib/lc22v10/stdlogic/c22v10.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------


Deleted 0 User equations/components.
Deleted 0 Synthesized equations/components.

------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 25 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------
Note:  Virtual signal MODULE_3_g1_a0_gx_u0_eq_0 with ( cost: 48 or cost_inv: 4)  > 30 or with size: 4 > 58 has been made a (soft) node.
Note:  Virtual signal MODULE_3_g1_a0_gx_u0_eq_1 with ( cost: 48 or cost_inv: 12)  > 30 or with size: 12 > 58 has been made a (soft) node.
Note:  Virtual signal MODULE_3_g1_a0_gx_u0_eq_3 with ( cost: 32 or cost_inv: 8)  > 30 or with size: 8 > 58 has been made a (soft) node.

----------------------------------------------------------
Circuit simplification results:

	Expanded 17 signals.
	Turned 3 signals into soft nodes.
	Maximum expansion cost was set at 1.
----------------------------------------------------------
Created 101 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN HEADER INFORMATION  (20:32:50)

Input File(s): boundaryx.pla
Device       : C22V10
Package      : PALCE22V10-25PC/PI
ReportFile   : boundaryx.rpt

Program Controls:
                 None.

Signal Requests:
    GROUP FAST_SLEW ALL
    GROUP SOFT MODULE_3_g1_a0_gx_u0_eq_3 MODULE_3_g1_a0_gx_u0_eq_1 
          MODULE_3_g1_a0_gx_u0_eq_0 

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (20:32:50)

Messages:
  Information: Process virtual 'MODULE_3_g1_a0_gx_u0_eq_3' ... converted to NODE.
 ... converted to NODE.
 ... converted to NODE.
  Information: Process virtual 'MODULE_2_g1_a0_g0_u0_c_4' ... expanded.
  Information: Process virtual 'MODULE_2_g1_a0_g0_u0_ci_2' ... expanded.
  Information: Process virtual 'MODULE_2_g1_a0_g0_u0_ci_4' ... expanded.
  Information: Process virtual 'MODULE_2_g1_a0_g0_u0_c_0' ... expanded.
  Information: Process virtual 'add_vi_us_MODGEN_3_1' ... expanded.
  Information: Process virtual 'old_ballx_msb' ... converted to NODE.
  Information: Process virtual 'MODIN3_0' ... converted to NODE.
  Information: Process virtual 'MODIN3_1' ... converted to NODE.
  Information: Optimizing logic using best output polarity for signals:
         incr_lden MODIN3_1.D MODULE_3_g1_a0_gx_u0_eq_1
         MODULE_3_g1_a0_gx_u0_eq_0 MODULE_2_g1_a0_g0_u0_ga_g1_ua0
         MODULE_3_g1_a0_gx_u0_eq_3

  Information: Selected logic optimization OFF for signals:
         old_ballx_msb.D old_ballx_msb.C MODIN3_0.D MODIN3_0.C MODIN3_1.C
         MODULE_2_g1_a0_g0_u0_ga_t1_ga0_1_u3



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     11/NOV/97    [v4.02 ] 4 IR x95

LOGIC MINIMIZATION         (20:32:50)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (20:32:51)

Messages:
  Information: Optimizing Banked Preset/Reset requirements.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN EQUATIONS           (20:32:51)


    incr_lden =
          /bally_4 * /pady_4 * /ballx_msb * old_ballx_msb.Q * 
          MODULE_3_g1_a0_gx_u0_eq_3 * /MODULE_2_g1_a0_g0_u0_ga_t1_ga0_1_u3 
        + bally_4 * pady_4 * /ballx_msb * old_ballx_msb.Q * 
          MODULE_3_g1_a0_gx_u0_eq_3 * /MODULE_2_g1_a0_g0_u0_ga_t1_ga0_1_u3 
        + bally_4 * /pady_4 * /ballx_msb * old_ballx_msb.Q * 
          MODULE_3_g1_a0_gx_u0_eq_3 * MODULE_2_g1_a0_g0_u0_ga_t1_ga0_1_u3 

    MODIN3_0.D =
          /MODIN3_0.Q 

    MODIN3_0.AR =
          GND

    MODIN3_0.SP =
          GND

    MODIN3_0.C =
          clk 

    old_ballx_msb.D =
          ballx_msb 

    old_ballx_msb.AR =
          GND

    old_ballx_msb.SP =
          GND

    old_ballx_msb.C =
          clk 

    MODIN3_1.D =
          MODIN3_1.Q * /MODIN3_0.Q 
        + /MODIN3_1.Q * MODIN3_0.Q 

    MODIN3_1.AR =
          GND

    MODIN3_1.SP =
          GND

    MODIN3_1.C =
          clk 

    MODULE_3_g1_a0_gx_u0_eq_1 =
          MODIN3_1.Q * MODIN3_0.Q * /pady_1 * pady_0 * /bally_1 * 
          MODULE_3_g1_a0_gx_u0_eq_0 
        + /MODIN3_1.Q * MODIN3_0.Q * pady_1 * pady_0 * /bally_1 * 
          MODULE_3_g1_a0_gx_u0_eq_0 
        + /MODIN3_1.Q * MODIN3_0.Q * /pady_1 * pady_0 * bally_1 * 
          MODULE_3_g1_a0_gx_u0_eq_0 
        + MODIN3_1.Q * MODIN3_0.Q * pady_1 * pady_0 * bally_1 * 
          MODULE_3_g1_a0_gx_u0_eq_0 
        + /MODIN3_1.Q * /pady_1 * /pady_0 * /bally_1 * 
          MODULE_3_g1_a0_gx_u0_eq_0 
        + MODIN3_1.Q * pady_1 * /pady_0 * /bally_1 * 
          MODULE_3_g1_a0_gx_u0_eq_0 
        + /MODIN3_1.Q * /MODIN3_0.Q * /pady_1 * /bally_1 * 
          MODULE_3_g1_a0_gx_u0_eq_0 
        + MODIN3_1.Q * /MODIN3_0.Q * pady_1 * /bally_1 * 
          MODULE_3_g1_a0_gx_u0_eq_0 
        + MODIN3_1.Q * /pady_1 * /pady_0 * bally_1 * 
          MODULE_3_g1_a0_gx_u0_eq_0 
        + /MODIN3_1.Q * pady_1 * /pady_0 * bally_1 * 
          MODULE_3_g1_a0_gx_u0_eq_0 
        + MODIN3_1.Q * /MODIN3_0.Q * /pady_1 * bally_1 * 
          MODULE_3_g1_a0_gx_u0_eq_0 
        + /MODIN3_1.Q * /MODIN3_0.Q * pady_1 * bally_1 * 
          MODULE_3_g1_a0_gx_u0_eq_0 

    MODULE_2_g1_a0_g0_u0_ga_g1_ua0 =
          MODIN3_0.Q * pady_1 * pady_0 
        + MODIN3_1.Q * MODIN3_0.Q * pady_0 
        + MODIN3_1.Q * pady_1 

    MODULE_3_g1_a0_gx_u0_eq_0 =
          /MODIN3_0.Q * /pady_0 * /bally_0 
        + MODIN3_0.Q * pady_0 * /bally_0 
        + MODIN3_0.Q * /pady_0 * bally_0 
        + /MODIN3_0.Q * pady_0 * bally_0 

    MODULE_2_g1_a0_g0_u0_ga_t1_ga0_1_u3 =
          MODULE_2_g1_a0_g0_u0_ga_g1_ua0 * pady_3 * pady_2 

    MODULE_3_g1_a0_gx_u0_eq_3 =
          /MODULE_2_g1_a0_g0_u0_ga_g1_ua0 * /pady_3 * /pady_2 * /bally_3 * 
          /bally_2 * MODULE_3_g1_a0_gx_u0_eq_1 
        + MODULE_2_g1_a0_g0_u0_ga_g1_ua0 * pady_3 * pady_2 * /bally_3 * 
          /bally_2 * MODULE_3_g1_a0_gx_u0_eq_1 
        + /MODULE_2_g1_a0_g0_u0_ga_g1_ua0 * pady_3 * /pady_2 * bally_3 * 
          /bally_2 * MODULE_3_g1_a0_gx_u0_eq_1 
        + MODULE_2_g1_a0_g0_u0_ga_g1_ua0 * /pady_3 * pady_2 * bally_3 * 
          /bally_2 * MODULE_3_g1_a0_gx_u0_eq_1 
        + MODULE_2_g1_a0_g0_u0_ga_g1_ua0 * /pady_3 * /pady_2 * /bally_3 * 
          bally_2 * MODULE_3_g1_a0_gx_u0_eq_1 
        + /MODULE_2_g1_a0_g0_u0_ga_g1_ua0 * /pady_3 * pady_2 * /bally_3 * 
          bally_2 * MODULE_3_g1_a0_gx_u0_eq_1 
        + MODULE_2_g1_a0_g0_u0_ga_g1_ua0 * pady_3 * /pady_2 * bally_3 * 
          bally_2 * MODULE_3_g1_a0_gx_u0_eq_1 
        + /MODULE_2_g1_a0_g0_u0_ga_g1_ua0 * pady_3 * pady_2 * bally_3 * 
          bally_2 * MODULE_3_g1_a0_gx_u0_eq_1 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN RULE CHECK          (20:32:51)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (20:32:51)

Messages:
  Information: Checking for duplicate NODE logic.
                 None.


                                 C22V10
                 __________________________________________
            clk =| 1|                                  |24|* not used       
      ballx_msb =| 2|                                  |23|= incr_lden      
        bally_0 =| 3|                                  |22|= (MODULE_2_g1.. 
        bally_1 =| 4|                                  |21|= (MODIN3_1)     
        bally_2 =| 5|                                  |20|= (MODIN3_0)     
        bally_3 =| 6|                                  |19|* not used       
        bally_4 =| 7|                                  |18|= (MODULE_2_g1.. 
         pady_0 =| 8|                                  |17|= (old_ballx_m.. 
         pady_1 =| 9|                                  |16|= (MODULE_3_g1.. 
         pady_2 =|10|                                  |15|= (MODULE_3_g1.. 
         pady_3 =|11|                                  |14|= (MODULE_3_g1.. 
       not used *|12|                                  |13|= pady_4         
                 __________________________________________


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

RESOURCE ALLOCATION        (20:32:51)

  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |   11  |   11  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |    9  |   10  |
                 ______________________________________
                                          21  /   22   = 95  %


  Information: Output Logic Product Term Utilization.

                  Node#  Output Signal Name  Used   Max
                 ________________________________________
                 | 14  |  MODULE_3_g1_..  |   8  |   8  |
                 | 15  |  MODULE_3_g1_..  |   4  |  10  |
                 | 16  |  MODULE_3_g1_..  |  12  |  12  |
                 | 17  |  old_ballx_msb   |   1  |  14  |
                 | 18  |  MODULE_2_g1_..  |   1  |  16  |
                 | 19  |  Unused          |   0  |  16  |
                 | 20  |  MODIN3_0        |   1  |  14  |
                 | 21  |  MODIN3_1        |   2  |  12  |
                 | 22  |  MODULE_2_g1_..  |   3  |  10  |
                 | 23  |  incr_lden       |   3  |   8  |
                 | 25  |  Unused          |   0  |   1  |
                 ________________________________________
                                             35  / 121   = 28  %


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

JEDEC ASSEMBLE             (20:32:51)

Messages:
  Information: Output file 'boundaryx.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 20:32:51
