
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x95
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|    1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  output.vhd
Options:    -m -o2 -ygs -fP -v10 -dc20v8 -pPALCE20V8-25PC output.vhd
======================================================================

vhdlfe V4 IR x95:  VHDL parser
Fri May  7 20:01:01 1999

Library 'work' => directory 'lc20v8'
Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/mit/6.111/warp4.3/lib/ieee/work'
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.

vhdlfe:  No errors.


tovif V4 IR x95:  High-level synthesis
Fri May  7 20:01:03 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.

tovif:  No errors.


topld V4 IR x96:  Synthesis and optimization
Fri May  7 20:01:04 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------



------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 0 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

----------------------------------------------------------
Circuit simplification results:

	Expanded 0 signals.
	Turned 0 signals into soft nodes.
	Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 17 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN HEADER INFORMATION  (20:01:06)

Input File(s): output.pla
Device       : c20v8
Package      : PALCE20V8-25PC
ReportFile   : output.rpt

Program Controls:
                 None.

Signal Requests:
    GROUP FAST_SLEW ALL

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (20:01:06)

Messages:
  Information: Optimizing logic using best output polarity for signals:
         x_out_7 x_out_6 x_out_5 x_out_4 x_out_3 x_out_2 x_out_1 x_out_0



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     11/NOV/97    [v4.02 ] 4 IR x95

LOGIC MINIMIZATION         (20:01:06)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (20:01:06)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN EQUATIONS           (20:01:06)


    x_out_7 =
          x_in_7 * /flip 
        + /x_in_7 * flip 

    x_out_6 =
          flip * /x_in_6 
        + /flip * x_in_6 

    x_out_5 =
          flip * /x_in_5 
        + /flip * x_in_5 

    x_out_4 =
          flip * /x_in_4 
        + /flip * x_in_4 

    x_out_3 =
          flip * /x_in_3 
        + /flip * x_in_3 

    x_out_2 =
          flip * /x_in_2 
        + /flip * x_in_2 

    x_out_1 =
          flip * /x_in_1 
        + /flip * x_in_1 

    x_out_0 =
          flip * /x_in_0 
        + /flip * x_in_0 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN RULE CHECK          (20:01:06)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (20:01:06)

Messages:
  Information: All signals pre-placed in user design.


                                 C20V8A
                 __________________________________________
       not used *| 1|                                  |24|* not used       
       not used *| 2|                                  |23|* not used       
         x_in_0 =| 3|                                  |22|= x_out_0        
         x_in_1 =| 4|                                  |21|= x_out_1        
         x_in_2 =| 5|                                  |20|= x_out_2        
         x_in_3 =| 6|                                  |19|= x_out_3        
         x_in_4 =| 7|                                  |18|= x_out_4        
         x_in_5 =| 8|                                  |17|= x_out_5        
         x_in_6 =| 9|                                  |16|= x_out_6        
         x_in_7 =|10|                                  |15|= x_out_7        
           flip =|11|                                  |14|* not used       
       not used *|12|                                  |13|* not used       
                 __________________________________________


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
  Information: Checking for duplicate NODE logic.
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

RESOURCE ALLOCATION        (20:01:06)

  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    9  |   14  |
                 | Output Macrocells  |    2  |    2  |
                 | I/O Macrocells     |    6  |    6  |
                 ______________________________________
                                          17  /   22   = 77  %


  Information: Output Logic Product Term Utilization.

                  Node#  Output Signal Name  Used   Max
                 ________________________________________
                 | 15  |  x_out_7         |   2  |   7  |
                 | 16  |  x_out_6         |   2  |   7  |
                 | 17  |  x_out_5         |   2  |   7  |
                 | 18  |  x_out_4         |   2  |   7  |
                 | 19  |  x_out_3         |   2  |   7  |
                 | 20  |  x_out_2         |   2  |   7  |
                 | 21  |  x_out_1         |   2  |   7  |
                 | 22  |  x_out_0         |   2  |   7  |
                 ________________________________________
                                             16  /  56   = 28  %


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

JEDEC ASSEMBLE             (20:01:07)

Messages:
  Information: Output file 'output.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 20:01:07
