
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x95
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|    1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  pong.vhd
Options:    -m -e10 -w100 -o2 -yga -fO -fP -v7 -dc372i -pCY7C372I-66JC pong.vhd
======================================================================

vhdlfe V4 IR x95:  VHDL parser
Wed May 12 06:42:31 1999

Library 'work' => directory 'lc372i'
Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/mit/6.111/warp4.3/lib/ieee/work'
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
pong.vhd (line 50, col 34):  Note: Substituting module 'sub_vi_us' for '-'.
pong.vhd (line 75, col 49):  Note: Substituting module 'cmp_vv_us' for '='.
pong.vhd (line 90, col 25):  Note: Substituting module 'add_vi_us' for '+'.
pong.vhd (line 92, col 26):  Note: Substituting module 'add_vv_us' for '+'.
pong.vhd (line 101, col 26):  Note: Substituting module 'add_vv_us' for '+'.
pong.vhd (line 108, col 21):  Note: Substituting module 'cmp_vv_us' for '='.
pong.vhd (line 108, col 47):  Note: Substituting module 'cmp_vv_us' for '='.

vhdlfe:  No errors.


tovif V4 IR x95:  High-level synthesis
Wed May 12 06:42:38 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/madd_sub.vif'.

tovif:  No errors.


topld V4 IR x96:  Synthesis and optimization
Wed May 12 06:42:53 1999

Linking '/mit/6.111/warp4.3/lib/common/work/cypress.vif'.
Linking '/mit/6.111/warp4.3/lib/ieee/work/stdlogic.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/lpmpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/rtlpkg.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_cnst.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mthu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_mths.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/mod_genu.vif'.
Linking '/mit/6.111/warp4.3/lib/common/stdlogic/madd_sub.vif'.
Linking '/mit/6.111/warp4.3/lib/lc370/stdlogic/c370.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------


Deleted 0 User equations/components.
Deleted 0 Synthesized equations/components.

------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 114 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------
Note:  Virtual signal cmp_vv_us_MODGEN_2 with ( cost: 4941 or cost_inv: 1)  > 2100 or with size: 1 > 190 has been made a (soft) node.

----------------------------------------------------------
Circuit simplification results:

	Expanded 60 signals.
	Turned 1 signals into soft nodes.
	Maximum expansion cost was set at 7.
----------------------------------------------------------
Created 296 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN HEADER INFORMATION  (06:43:02)

Input File(s): pong.pla
Device       : c372i
Package      : CY7C372I-66JC
ReportFile   : pong.rpt

Program Controls:
                 None.

Signal Requests:
    GROUP DT-OPT ALL
    GROUP FAST_SLEW ALL
    GROUP SOFT cmp_vv_us_MODGEN_2 

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (06:43:02)

Messages:
  Information: Process virtual 'cmp_vv_us_MODGEN_2' ... converted to NODE.
  Information: Process virtual 'MODULE_6_g1_a0_g0_u0_c_8' ... expanded.
  Information: Process virtual 'MODULE_6_g1_a0_g0_u0_c_6' ... expanded.
  Information: Process virtual 'MODULE_6_g1_a0_g0_u0_c_4' ... expanded.
  Information: Process virtual 'MODULE_6_g1_a0_g0_u0_ci_2' ... expanded.
  Information: Process virtual 'MODULE_1_g1_a0_g0_u0_c_8' ... expanded.
  Information: Process virtual 'MODULE_1_g1_a0_g0_u0_c_6' ... expanded.
  Information: Process virtual 'MODULE_1_g1_a0_g0_u0_c_4' ... expanded.
  Information: Process virtual 'MODULE_1_g1_a0_g0_u0_ci_2' ... expanded.
  Information: Process virtual 'ymsb_7' ... expanded.
  Information: Process virtual 'x_0' ... expanded.
  Information: Process virtual 'old_oddevenD' ... expanded.
  Information: Process virtual 'random_vy_0D' ... expanded.
  Information: Process virtual 'random_vy_1D' ... expanded.
  Information: Process virtual 'random_vy_2D' ... expanded.
  Information: Process virtual 'random_vx_0D' ... expanded.
  Information: Process virtual 'random_vx_1D' ... expanded.
  Information: Process virtual 'MODIN8_0D' ... expanded.
  Information: Process virtual 'MODIN8_1D' ... expanded.
  Information: Process virtual 'MODIN2_0D' ... expanded.
  Information: Process virtual 'MODIN2_1D' ... expanded.
  Information: Process virtual 'y_0D' ... expanded.
  Information: Process virtual 'y_1D' ... expanded.
  Information: Process virtual 'y_2D' ... expanded.
  Information: Process virtual 'y_3D' ... expanded.
  Information: Process virtual 'y_4D' ... expanded.
  Information: Process virtual 'y_5D' ... expanded.
  Information: Process virtual 'y_6D' ... expanded.
  Information: Process virtual 'y_7D' ... expanded.
  Information: Process virtual 'ymsb_7D' ... expanded.
  Information: Process virtual 'x_0D' ... expanded.
  Information: Process virtual 'x_1D' ... expanded.
  Information: Process virtual 'x_2D' ... expanded.
  Information: Process virtual 'x_3D' ... expanded.
  Information: Process virtual 'x_4D' ... expanded.
  Information: Process virtual 'x_5D' ... expanded.
  Information: Process virtual 'x_6D' ... expanded.
  Information: Process virtual 'x_7D' ... expanded.
  Information: Process virtual 'x_8D' ... expanded.
  Information: Process virtual 'win2D' ... expanded.
  Information: Process virtual 'win1D' ... expanded.
  Information: Process virtual 'vrandomizeD' ... expanded.
  Information: Process virtual 'reverseD' ... expanded.
  Information: Process virtual 'MODULE_6_g1_a0_g0_u0_ci_8' ... expanded.
  Information: Process virtual 'MODULE_6_g1_a0_g0_u0_ci_6' ... expanded.
  Information: Process virtual 'MODULE_6_g1_a0_g0_u0_ci_4' ... expanded.
  Information: Process virtual 'MODULE_6_g1_a0_g0_u0_c_0' ... expanded.
  Information: Process virtual 'MODULE_1_g1_a0_g0_u0_ci_8' ... expanded.
  Information: Process virtual 'MODULE_1_g1_a0_g0_u0_ci_6' ... expanded.
  Information: Process virtual 'MODULE_1_g1_a0_g0_u0_ci_4' ... expanded.
  Information: Process virtual 'MODULE_1_g1_a0_g0_u0_c_0' ... expanded.
  Information: Process virtual 'old_oddeven' ... converted to NODE.
  Information: Process virtual 'random_vy_0' ... converted to NODE.
  Information: Process virtual 'random_vy_1' ... converted to NODE.
  Information: Process virtual 'random_vy_2' ... converted to NODE.
  Information: Process virtual 'random_vx_0' ... converted to NODE.
  Information: Process virtual 'random_vx_1' ... converted to NODE.
  Information: Process virtual 'clock_2' ... converted to NODE.
  Information: Process virtual 'latched_diff' ... converted to NODE.
  Information: Process virtual 'MODIN8_0' ... converted to NODE.
  Information: Process virtual 'MODIN8_1' ... converted to NODE.
  Information: Process virtual 'MODIN2_0' ... converted to NODE.
  Information: Process virtual 'MODIN2_1' ... converted to NODE.
  Information: Process virtual 'y_0' ... converted to NODE.
  Information: Process virtual 'y_1' ... converted to NODE.
  Information: Process virtual 'y_2' ... converted to NODE.
  Information: Process virtual 'y_3' ... converted to NODE.
  Information: Process virtual 'y_4' ... converted to NODE.
  Information: Process virtual 'y_5' ... converted to NODE.
  Information: Process virtual 'y_6' ... converted to NODE.
  Information: Process virtual 'y_7' ... converted to NODE.
  Information: Process virtual 'ymsb_6' ... converted to NODE.
  Information: Process virtual 'sub_vi_us_MODGEN_1_0' ... converted to NODE.
  Information: Process virtual 'x_1' ... converted to NODE.
  Information: Process virtual 'x_2' ... converted to NODE.
  Information: Process virtual 'x_3' ... converted to NODE.
  Information: Process virtual 'x_4' ... converted to NODE.
  Information: Process virtual 'x_5' ... converted to NODE.
  Information: Process virtual 'x_7' ... converted to NODE.
  Information: Process virtual 'x_8' ... converted to NODE.
  Information: Generating both D & T register equations for signal win1.D[16]
  Information: Expanding XOR equation found on signal win1.T[16]
  Information: Generating both D & T register equations for signal win2.D[17]
  Information: Expanding XOR equation found on signal win2.T[17]
  Information: Generating both D & T register equations for signal ballx_6.D[25]
  Information: Expanding XOR equation found on signal ballx_6.T[25]
  Information: Generating both D & T register equations for signal old_oddeven.D
  Information: Expanding XOR equation found on signal old_oddeven.T
  Information: Generating both D & T register equations for signal random_vy_0.D
  Information: Expanding XOR equation found on signal random_vy_0.T
  Information: Generating both D & T register equations for signal random_vy_1.D
  Information: Expanding XOR equation found on signal random_vy_1.T
  Information: Generating both D & T register equations for signal random_vy_2.D
  Information: Expanding XOR equation found on signal random_vy_2.T
  Information: Generating both D & T register equations for signal random_vx_0.D
  Information: Expanding XOR equation found on signal random_vx_0.T
  Information: Generating both D & T register equations for signal random_vx_1.D
  Information: Expanding XOR equation found on signal random_vx_1.T
  Information: Generating both D & T register equations for signal clock_2.D
  Information: Expanding XOR equation found on signal clock_2.T
  Information: Generating both D & T register equations for signal latched_diff.D
  Information: Expanding XOR equation found on signal latched_diff.T
  Information: Signal diff is converted to a Input Register.
  Information: Generating both D & T register equations for signal MODIN8_0.D
  Information: Expanding XOR equation found on signal MODIN8_0.T
  Information: Generating both D & T register equations for signal MODIN8_1.D
  Information: Expanding XOR equation found on signal MODIN8_1.T
  Information: Generating both D & T register equations for signal MODIN2_0.D
  Information: Expanding XOR equation found on signal MODIN2_0.T
  Information: Generating both D & T register equations for signal MODIN2_1.D
  Information: Expanding XOR equation found on signal MODIN2_1.T
  Information: Generating both D & T register equations for signal y_0.D
  Information: Expanding XOR equation found on signal y_0.T
  Information: Generating both D & T register equations for signal y_1.D
  Information: Expanding XOR equation found on signal y_1.T
  Information: Generating both D & T register equations for signal y_2.D
  Information: Expanding XOR equation found on signal y_2.T
  Information: Generating both D & T register equations for signal y_3.D
  Information: Expanding XOR equation found on signal y_3.T
  Information: Generating both D & T register equations for signal y_4.D
  Information: Expanding XOR equation found on signal y_4.T
  Information: Generating both D & T register equations for signal y_5.D
  Information: Expanding XOR equation found on signal y_5.T
  Information: Generating both D & T register equations for signal y_6.D
  Information: Expanding XOR equation found on signal y_6.T
  Information: Generating both D & T register equations for signal y_7.D
  Information: Expanding XOR equation found on signal y_7.T
  Information: Generating both D & T register equations for signal x_1.D
  Information: Expanding XOR equation found on signal x_1.T
  Information: Generating both D & T register equations for signal x_2.D
  Information: Expanding XOR equation found on signal x_2.T
  Information: Generating both D & T register equations for signal x_3.D
  Information: Expanding XOR equation found on signal x_3.T
  Information: Generating both D & T register equations for signal x_4.D
  Information: Expanding XOR equation found on signal x_4.T
  Information: Generating both D & T register equations for signal x_5.D
  Information: Expanding XOR equation found on signal x_5.T
  Information: Generating both D & T register equations for signal x_7.D
  Information: Expanding XOR equation found on signal x_7.T
  Information: Generating both D & T register equations for signal x_8.D
  Information: Expanding XOR equation found on signal x_8.T
  Information: Generating both D & T register equations for signal vrandomize.D
  Information: Expanding XOR equation found on signal vrandomize.T
  Information: Generating both D & T register equations for signal reverse.D
  Information: Expanding XOR equation found on signal reverse.T
  Information: Generating both D & T register equations for signal ymsb_6.D
  Information: Expanding XOR equation found on signal ymsb_6.T
  Information: Generating both D & T register equations for signal sub_vi_us_MODGEN_1_0.D
  Information: Expanding XOR equation found on signal sub_vi_us_MODGEN_1_0.T
  Information: Optimizing logic without changing polarity for signals:
         win1.T win2.T ballx_6.T old_oddeven.T random_vy_0.T random_vy_1.T
         random_vy_2.T random_vx_0.T random_vx_1.T clock_2.T MODIN8_0.T
         MODIN8_1.T MODIN2_0.T MODIN2_1.T y_0.T y_1.T y_2.T y_3.T y_4.T y_5.T
         y_6.T y_7.T x_1.T x_2.T x_3.T x_4.T x_5.T x_7.T x_8.T vrandomize.T
         reverse.T ymsb_6.T sub_vi_us_MODGEN_1_0.T

  Information: Optimizing logic using best output polarity for signals:
         win1.D win2.D ballx_7 ballx_6.D ballx_5 ballx_4 ballx_3 ballx_2
         ballx_1 ballx_0 bally_7 bally_6 bally_5 bally_4 bally_3 bally_2
         bally_1 bally_0 old_oddeven.D random_vy_0.D random_vy_1.D
         random_vy_2.D random_vx_0.D random_vx_1.D MODIN8_0.D MODIN8_1.D
         MODIN2_0.D MODIN2_1.D y_0.D y_1.D y_2.D y_3.D y_4.D y_5.D y_6.D y_7.D
         x_1.D x_2.D x_3.D x_4.D x_5.D x_7.D x_8.D vrandomize.D reverse.D
         MODULE_6_g1_a0_g0_u0_ga_g1_ua0 MODULE_1_g1_a0_g0_u0_ga_g1_ua0
         ymsb_6.D sub_vi_us_MODGEN_1_0.D

  Information: Selected logic optimization OFF for signals:
         countclk1 countclk2 win1.C win2.C ballx_6.C diff.CI old_oddeven.C
         random_vy_0.C random_vy_1.C random_vy_2.C random_vx_0.C random_vx_1.C
         clock_2.D clock_2.C MODIN8_0.C MODIN8_1.C MODIN2_0.C MODIN2_1.C y_0.C
         y_1.C y_2.C y_3.C y_4.C y_5.C y_6.C y_7.C x_1.C x_2.C x_3.C x_4.C
         x_5.C x_7.C x_8.C vrandomize.C reverse.C cmp_vv_us_MODGEN_2
         MODULE_6_g1_a0_g0_u0_ga_t1_ga0_3_u3
         MODULE_6_g1_a0_g0_u0_ga_t1_ga0_2_u3
         MODULE_6_g1_a0_g0_u0_ga_t1_ga0_1_u3
         MODULE_1_g1_a0_g0_u0_ga_t1_ga0_3_u3
         MODULE_1_g1_a0_g0_u0_ga_t1_ga0_2_u3
         MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3 ymsb_6.C sub_vi_us_MODGEN_1_0.C



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     11/NOV/97    [v4.02 ] 4 IR x95

LOGIC MINIMIZATION         (06:43:05)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

OPTIMIZATION OPTIONS       (06:43:07)

Messages:
  Information: Optimizing Banked Preset/Reset requirements.
  Information: Selecting D register equation as minimal for signal win1
  Information: Selecting D register equation as minimal for signal win2
  Information: Selecting T register equation as minimal for signal ballx_6
  Information: Selecting T register equation as minimal for signal sub_vi_us_MODGEN_1_0
  Information: Selecting T register equation as minimal for signal ymsb_6
  Information: Selecting D register equation as minimal for signal reverse
  Information: Selecting D register equation as minimal for signal vrandomize
  Information: Selecting T register equation as minimal for signal x_8
  Information: Selecting T register equation as minimal for signal x_7
  Information: Selecting T register equation as minimal for signal x_5
  Information: Selecting T register equation as minimal for signal x_4
  Information: Selecting T register equation as minimal for signal x_3
  Information: Selecting T register equation as minimal for signal x_2
  Information: Selecting T register equation as minimal for signal x_1
  Information: Selecting T register equation as minimal for signal y_7
  Information: Selecting T register equation as minimal for signal y_6
  Information: Selecting T register equation as minimal for signal y_5
  Information: Selecting T register equation as minimal for signal y_4
  Information: Selecting T register equation as minimal for signal y_3
  Information: Selecting T register equation as minimal for signal y_2
  Information: Selecting T register equation as minimal for signal y_1
  Information: Selecting T register equation as minimal for signal y_0
  Information: Selecting D register equation as minimal for signal MODIN2_1
  Information: Selecting D register equation as minimal for signal MODIN2_0
  Information: Selecting D register equation as minimal for signal MODIN8_1
  Information: Selecting D register equation as minimal for signal MODIN8_0
  Information: Selecting D register equation as minimal for signal clock_2
  Information: Selecting T register equation as minimal for signal random_vx_1
  Information: Selecting D register equation as minimal for signal random_vx_0
  Information: Selecting D register equation as minimal for signal random_vy_2
  Information: Selecting D register equation as minimal for signal random_vy_1
  Information: Selecting D register equation as minimal for signal random_vy_0
  Information: Selecting D register equation as minimal for signal old_oddeven


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN EQUATIONS           (06:43:12)


    countclk1 =
          /win1.Q 

    countclk2 =
          /win2.Q 

    /win1.D =
          /MODIN2_1.Q * /MODIN2_0.Q * n_reset * /oddeven * col_eq_ballx * 
          row_eq_bally * diff.QI * /cmp_vv_us_MODGEN_2.CMB * 
          /old_oddeven.Q 
        + x_7.Q * /ballx_6.Q * n_reset * /oddeven * col_eq_ballx * 
          row_eq_bally * diff.QI * /cmp_vv_us_MODGEN_2.CMB * 
          /old_oddeven.Q 
        + /MODIN2_1.Q * /MODIN2_0.Q * n_reset * oddeven * col_eq_ballx * 
          row_eq_bally * diff.QI * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q 
        + x_7.Q * /ballx_6.Q * n_reset * oddeven * col_eq_ballx * 
          row_eq_bally * diff.QI * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q 
        + /win1.Q * n_reset * /cmp_vv_us_MODGEN_2.CMB 
        + /x_8.Q * cmp_vv_us_MODGEN_2.CMB 
        + /x_8.Q * /n_reset 

    win1.AP =
          GND

    win1.AR =
          GND

    win1.C =
          clk 

    /win2.D =
          /MODIN2_1.Q * /MODIN2_0.Q * n_reset * /oddeven * col_eq_ballx * 
          row_eq_bally * diff.QI * /cmp_vv_us_MODGEN_2.CMB * 
          /old_oddeven.Q 
        + x_7.Q * /ballx_6.Q * n_reset * /oddeven * col_eq_ballx * 
          row_eq_bally * diff.QI * /cmp_vv_us_MODGEN_2.CMB * 
          /old_oddeven.Q 
        + /MODIN2_1.Q * /MODIN2_0.Q * n_reset * oddeven * col_eq_ballx * 
          row_eq_bally * diff.QI * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q 
        + x_7.Q * /ballx_6.Q * n_reset * oddeven * col_eq_ballx * 
          row_eq_bally * diff.QI * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q 
        + /win2.Q * n_reset * /cmp_vv_us_MODGEN_2.CMB 
        + x_8.Q * cmp_vv_us_MODGEN_2.CMB 
        + x_8.Q * /n_reset 

    win2.AP =
          GND

    win2.AR =
          GND

    win2.C =
          clk 

    ballx_7 =
          x_8.Q * x_7.Q * /ballx_6.Q 
        + /x_7.Q * ballx_6.Q 
        + /x_8.Q * /x_7.Q 

    /ballx_6.T =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          MODULE_1_g1_a0_g0_u0_ga_t1_ga0_2_u3.CMB * /reverse.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          MODULE_1_g1_a0_g0_u0_ga_t1_ga0_2_u3.CMB * /reverse.Q 
        + /ballx_6.Q * cmp_vv_us_MODGEN_2.CMB 
        + /ballx_6.Q * /n_reset 

    ballx_6.AP =
          GND

    ballx_6.AR =
          GND

    ballx_6.C =
          clk 

    ballx_5 =
          /x_8.Q * /x_5.Q 
        + x_8.Q * x_5.Q 

    ballx_4 =
          /x_8.Q * /x_4.Q 
        + x_8.Q * x_4.Q 

    ballx_3 =
          /x_8.Q * /x_3.Q 
        + x_8.Q * x_3.Q 

    ballx_2 =
          /x_8.Q * /x_2.Q 
        + x_8.Q * x_2.Q 

    ballx_1 =
          /x_8.Q * /x_1.Q 
        + x_8.Q * x_1.Q 

    ballx_0 =
          /x_8.Q * /sub_vi_us_MODGEN_1_0.Q 
        + x_8.Q * sub_vi_us_MODGEN_1_0.Q 

    diff.CI =
          /clk 

    bally_7 =
          /y_7.Q * ymsb_6.Q 
        + y_7.Q * /ymsb_6.Q 

    bally_6 =
          /y_6.Q * ymsb_6.Q 
        + y_6.Q * /ymsb_6.Q 

    bally_5 =
          /y_5.Q * ymsb_6.Q 
        + y_5.Q * /ymsb_6.Q 

    bally_4 =
          /y_4.Q * ymsb_6.Q 
        + y_4.Q * /ymsb_6.Q 

    bally_3 =
          /y_3.Q * ymsb_6.Q 
        + y_3.Q * /ymsb_6.Q 

    bally_2 =
          /y_2.Q * ymsb_6.Q 
        + y_2.Q * /ymsb_6.Q 

    bally_1 =
          /y_1.Q * ymsb_6.Q 
        + y_1.Q * /ymsb_6.Q 

    bally_0 =
          /y_0.Q * ymsb_6.Q 
        + y_0.Q * /ymsb_6.Q 

    sub_vi_us_MODGEN_1_0.T =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          reverse.Q 
        + MODIN2_0.Q * n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * 
          /old_oddeven.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          reverse.Q 
        + MODIN2_0.Q * n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * 
          old_oddeven.Q 
        + cmp_vv_us_MODGEN_2.CMB * sub_vi_us_MODGEN_1_0.Q 
        + /n_reset * sub_vi_us_MODGEN_1_0.Q 

    sub_vi_us_MODGEN_1_0.AP =
          GND

    sub_vi_us_MODGEN_1_0.AR =
          GND

    sub_vi_us_MODGEN_1_0.C =
          clk 

    ymsb_6.T =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          random_vy_2.Q * vrandomize.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          random_vy_2.Q * vrandomize.Q 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          /vrandomize.Q * MODULE_6_g1_a0_g0_u0_ga_t1_ga0_3_u3.CMB 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          /vrandomize.Q * MODULE_6_g1_a0_g0_u0_ga_t1_ga0_3_u3.CMB 
        + cmp_vv_us_MODGEN_2.CMB * /random_vy_0.Q * ymsb_6.Q 
        + /n_reset * /random_vy_0.Q * ymsb_6.Q 
        + cmp_vv_us_MODGEN_2.CMB * random_vy_0.Q * /ymsb_6.Q 
        + /n_reset * random_vy_0.Q * /ymsb_6.Q 

    ymsb_6.AP =
          GND

    ymsb_6.AR =
          GND

    ymsb_6.C =
          clk 

    reverse.D =
          /MODIN2_1.Q * /MODIN2_0.Q * n_reset * /oddeven * col_eq_ballx * 
          row_eq_bally * diff.QI * /cmp_vv_us_MODGEN_2.CMB * 
          /old_oddeven.Q 
        + x_7.Q * /ballx_6.Q * n_reset * /oddeven * col_eq_ballx * 
          row_eq_bally * diff.QI * /cmp_vv_us_MODGEN_2.CMB * 
          /old_oddeven.Q 
        + /MODIN2_1.Q * /MODIN2_0.Q * n_reset * oddeven * col_eq_ballx * 
          row_eq_bally * diff.QI * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q 
        + x_7.Q * /ballx_6.Q * n_reset * oddeven * col_eq_ballx * 
          row_eq_bally * diff.QI * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          reverse.Q 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          reverse.Q 
        + cmp_vv_us_MODGEN_2.CMB * random_vy_1.Q 
        + /n_reset * random_vy_1.Q 

    reverse.AP =
          GND

    reverse.AR =
          GND

    reverse.C =
          clk 

    vrandomize.D =
          /MODIN2_1.Q * /MODIN2_0.Q * n_reset * /oddeven * col_eq_ballx * 
          row_eq_bally * diff.QI * /cmp_vv_us_MODGEN_2.CMB * 
          /old_oddeven.Q 
        + x_7.Q * /ballx_6.Q * n_reset * /oddeven * col_eq_ballx * 
          row_eq_bally * diff.QI * /cmp_vv_us_MODGEN_2.CMB * 
          /old_oddeven.Q 
        + /MODIN2_1.Q * /MODIN2_0.Q * n_reset * oddeven * col_eq_ballx * 
          row_eq_bally * diff.QI * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q 
        + x_7.Q * /ballx_6.Q * n_reset * oddeven * col_eq_ballx * 
          row_eq_bally * diff.QI * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          vrandomize.Q 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          vrandomize.Q 

    vrandomize.AP =
          GND

    vrandomize.AR =
          GND

    vrandomize.C =
          clk 

    x_8.T =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          /reverse.Q * MODULE_1_g1_a0_g0_u0_ga_t1_ga0_3_u3.CMB 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          /reverse.Q * MODULE_1_g1_a0_g0_u0_ga_t1_ga0_3_u3.CMB 
        + /ballx_6.Q * n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * 
          /old_oddeven.Q * reverse.Q 
        + x_7.Q * n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * 
          /old_oddeven.Q * reverse.Q 
        + /ballx_6.Q * n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * 
          old_oddeven.Q * reverse.Q 
        + x_7.Q * n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * 
          old_oddeven.Q * reverse.Q 
        + x_8.Q * cmp_vv_us_MODGEN_2.CMB 
        + x_8.Q * /n_reset 

    x_8.AP =
          GND

    x_8.AR =
          GND

    x_8.C =
          clk 

    x_7.T =
          /ballx_6.Q * n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * 
          /old_oddeven.Q * reverse.Q 
        + /ballx_6.Q * n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * 
          old_oddeven.Q * reverse.Q 
        + /ballx_6.Q * n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * 
          /old_oddeven.Q * MODULE_1_g1_a0_g0_u0_ga_t1_ga0_2_u3.CMB 
        + /ballx_6.Q * n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * 
          old_oddeven.Q * MODULE_1_g1_a0_g0_u0_ga_t1_ga0_2_u3.CMB 
        + /x_7.Q * cmp_vv_us_MODGEN_2.CMB 
        + /x_7.Q * /n_reset 

    x_7.AP =
          GND

    x_7.AR =
          GND

    x_7.C =
          clk 

    x_5.T =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          x_4.Q * MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3.CMB 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          x_4.Q * MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3.CMB 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          reverse.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          reverse.Q 
        + cmp_vv_us_MODGEN_2.CMB * x_5.Q 
        + /n_reset * x_5.Q 

    x_5.AP =
          GND

    x_5.AR =
          GND

    x_5.C =
          clk 

    x_4.T =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          reverse.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          reverse.Q 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3.CMB 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3.CMB 
        + cmp_vv_us_MODGEN_2.CMB * /x_4.Q 
        + /n_reset * /x_4.Q 

    x_4.AP =
          GND

    x_4.AR =
          GND

    x_4.C =
          clk 

    x_3.T =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          x_2.Q * MODULE_1_g1_a0_g0_u0_ga_g1_ua0.CMB 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          x_2.Q * MODULE_1_g1_a0_g0_u0_ga_g1_ua0.CMB 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          reverse.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          reverse.Q 
        + cmp_vv_us_MODGEN_2.CMB * /x_3.Q 
        + /n_reset * /x_3.Q 

    x_3.AP =
          GND

    x_3.AR =
          GND

    x_3.C =
          clk 

    x_2.T =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          reverse.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          reverse.Q 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          MODULE_1_g1_a0_g0_u0_ga_g1_ua0.CMB 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          MODULE_1_g1_a0_g0_u0_ga_g1_ua0.CMB 
        + cmp_vv_us_MODGEN_2.CMB * x_2.Q 
        + /n_reset * x_2.Q 

    x_2.AP =
          GND

    x_2.AR =
          GND

    x_2.C =
          clk 

    x_1.T =
          /MODIN2_1.Q * MODIN2_0.Q * n_reset * oddeven * 
          /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          sub_vi_us_MODGEN_1_0.Q 
        + /MODIN2_1.Q * MODIN2_0.Q * n_reset * /oddeven * 
          /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * sub_vi_us_MODGEN_1_0.Q 
        + MODIN2_1.Q * /MODIN2_0.Q * n_reset * oddeven * 
          /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q 
        + MODIN2_1.Q * n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * 
          /old_oddeven.Q * /sub_vi_us_MODGEN_1_0.Q 
        + MODIN2_1.Q * /MODIN2_0.Q * n_reset * /oddeven * 
          /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q 
        + MODIN2_1.Q * n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * 
          old_oddeven.Q * /sub_vi_us_MODGEN_1_0.Q 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          reverse.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          reverse.Q 
        + cmp_vv_us_MODGEN_2.CMB * /x_1.Q 
        + /n_reset * /x_1.Q 

    x_1.AP =
          GND

    x_1.AR =
          GND

    x_1.C =
          clk 

    y_7.T =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          /vrandomize.Q * y_6.Q * MODULE_6_g1_a0_g0_u0_ga_t1_ga0_2_u3.CMB 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          /vrandomize.Q * y_6.Q * MODULE_6_g1_a0_g0_u0_ga_t1_ga0_2_u3.CMB 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          random_vy_2.Q * vrandomize.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          random_vy_2.Q * vrandomize.Q 
        + cmp_vv_us_MODGEN_2.CMB * /y_7.Q 
        + /n_reset * /y_7.Q 

    y_7.AP =
          GND

    y_7.AR =
          GND

    y_7.C =
          clk 

    y_6.T =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          random_vy_2.Q * vrandomize.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          random_vy_2.Q * vrandomize.Q 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          /vrandomize.Q * MODULE_6_g1_a0_g0_u0_ga_t1_ga0_2_u3.CMB 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          /vrandomize.Q * MODULE_6_g1_a0_g0_u0_ga_t1_ga0_2_u3.CMB 
        + cmp_vv_us_MODGEN_2.CMB * y_6.Q 
        + /n_reset * y_6.Q 

    y_6.AP =
          GND

    y_6.AR =
          GND

    y_6.C =
          clk 

    y_5.T =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          /vrandomize.Q * y_4.Q * MODULE_6_g1_a0_g0_u0_ga_t1_ga0_1_u3.CMB 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          /vrandomize.Q * y_4.Q * MODULE_6_g1_a0_g0_u0_ga_t1_ga0_1_u3.CMB 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          random_vy_2.Q * vrandomize.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          random_vy_2.Q * vrandomize.Q 
        + cmp_vv_us_MODGEN_2.CMB * y_5.Q 
        + /n_reset * y_5.Q 

    y_5.AP =
          GND

    y_5.AR =
          GND

    y_5.C =
          clk 

    y_4.T =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          random_vy_2.Q * vrandomize.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          random_vy_2.Q * vrandomize.Q 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          /vrandomize.Q * MODULE_6_g1_a0_g0_u0_ga_t1_ga0_1_u3.CMB 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          /vrandomize.Q * MODULE_6_g1_a0_g0_u0_ga_t1_ga0_1_u3.CMB 
        + cmp_vv_us_MODGEN_2.CMB * y_4.Q 
        + /n_reset * y_4.Q 

    y_4.AP =
          GND

    y_4.AR =
          GND

    y_4.C =
          clk 

    y_3.T =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          /vrandomize.Q * y_2.Q * MODULE_6_g1_a0_g0_u0_ga_g1_ua0.CMB 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          /vrandomize.Q * y_2.Q * MODULE_6_g1_a0_g0_u0_ga_g1_ua0.CMB 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          random_vy_2.Q * vrandomize.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          random_vy_2.Q * vrandomize.Q 
        + cmp_vv_us_MODGEN_2.CMB * y_3.Q 
        + /n_reset * y_3.Q 

    y_3.AP =
          GND

    y_3.AR =
          GND

    y_3.C =
          clk 

    y_2.T =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          random_vy_2.Q * vrandomize.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          random_vy_2.Q * vrandomize.Q 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          /vrandomize.Q * MODULE_6_g1_a0_g0_u0_ga_g1_ua0.CMB 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          /vrandomize.Q * MODULE_6_g1_a0_g0_u0_ga_g1_ua0.CMB 
        + cmp_vv_us_MODGEN_2.CMB * y_2.Q 
        + /n_reset * y_2.Q 

    y_2.AP =
          GND

    y_2.AR =
          GND

    y_2.C =
          clk 

    y_1.T =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          /MODIN8_1.Q * MODIN8_0.Q * /vrandomize.Q * y_0.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          /MODIN8_1.Q * MODIN8_0.Q * /vrandomize.Q * y_0.Q 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          MODIN8_1.Q * /MODIN8_0.Q * /vrandomize.Q 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          MODIN8_1.Q * /vrandomize.Q * /y_0.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          MODIN8_1.Q * /MODIN8_0.Q * /vrandomize.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          MODIN8_1.Q * /vrandomize.Q * /y_0.Q 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          random_vy_2.Q * vrandomize.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          random_vy_2.Q * vrandomize.Q 
        + cmp_vv_us_MODGEN_2.CMB * y_1.Q 
        + /n_reset * y_1.Q 

    y_1.AP =
          GND

    y_1.AR =
          GND

    y_1.C =
          clk 

    y_0.T =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          random_vy_2.Q * vrandomize.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          random_vy_2.Q * vrandomize.Q 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          MODIN8_0.Q * /vrandomize.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          MODIN8_0.Q * /vrandomize.Q 
        + cmp_vv_us_MODGEN_2.CMB * y_0.Q 
        + /n_reset * y_0.Q 

    y_0.AP =
          GND

    y_0.AR =
          GND

    y_0.C =
          clk 

    MODIN2_1.D =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          random_vx_1.Q * vrandomize.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          random_vx_1.Q * vrandomize.Q 
        + MODIN2_1.Q * n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * 
          /old_oddeven.Q 
        + MODIN2_1.Q * n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * 
          old_oddeven.Q 
        + MODIN2_1.Q * n_reset * /cmp_vv_us_MODGEN_2.CMB * /vrandomize.Q 

    MODIN2_1.AP =
          GND

    MODIN2_1.AR =
          GND

    MODIN2_1.C =
          clk 

    MODIN2_0.D =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          random_vx_0.Q * vrandomize.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          random_vx_0.Q * vrandomize.Q 
        + MODIN2_0.Q * n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * 
          /old_oddeven.Q 
        + MODIN2_0.Q * n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * 
          old_oddeven.Q 
        + MODIN2_0.Q * n_reset * /cmp_vv_us_MODGEN_2.CMB * /vrandomize.Q 

    MODIN2_0.AP =
          GND

    MODIN2_0.AR =
          GND

    MODIN2_0.C =
          clk 

    MODIN8_1.D =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          random_vy_1.Q * vrandomize.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          random_vy_1.Q * vrandomize.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          MODIN8_1.Q 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          MODIN8_1.Q 
        + n_reset * /cmp_vv_us_MODGEN_2.CMB * MODIN8_1.Q * /vrandomize.Q 

    MODIN8_1.AP =
          GND

    MODIN8_1.AR =
          GND

    MODIN8_1.C =
          clk 

    MODIN8_0.D =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          random_vy_0.Q * vrandomize.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          random_vy_0.Q * vrandomize.Q 
        + n_reset * /oddeven * /cmp_vv_us_MODGEN_2.CMB * /old_oddeven.Q * 
          MODIN8_0.Q 
        + n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB * old_oddeven.Q * 
          MODIN8_0.Q 
        + n_reset * /cmp_vv_us_MODGEN_2.CMB * MODIN8_0.Q * /vrandomize.Q 

    MODIN8_0.AP =
          GND

    MODIN8_0.AR =
          GND

    MODIN8_0.C =
          clk 

    clock_2.D =
          /clock_2.Q 

    clock_2.AP =
          GND

    clock_2.AR =
          GND

    clock_2.C =
          clk 

    random_vx_1.T =
          random_vx_1.Q * /random_vx_0.Q * random_in * /clock_2.Q 
        + /random_vx_1.Q * random_vx_0.Q * /clock_2.Q 

    random_vx_1.AP =
          GND

    random_vx_1.AR =
          GND

    random_vx_1.C =
          clk 

    random_vx_0.D =
          random_in * /clock_2.Q 
        + random_vx_0.Q * clock_2.Q 

    random_vx_0.AP =
          GND

    random_vx_0.AR =
          GND

    random_vx_0.C =
          clk 

    random_vy_2.D =
          random_vy_2.Q * /clock_2.Q 
        + random_vy_1.Q * clock_2.Q 

    random_vy_2.AP =
          GND

    random_vy_2.AR =
          GND

    random_vy_2.C =
          clk 

    random_vy_1.D =
          random_vy_1.Q * /clock_2.Q 
        + random_vy_0.Q * clock_2.Q 

    random_vy_1.AP =
          GND

    random_vy_1.AR =
          GND

    random_vy_1.C =
          clk 

    random_vy_0.D =
          random_vy_0.Q * /clock_2.Q 
        + random_in * clock_2.Q 

    random_vy_0.AP =
          GND

    random_vy_0.AR =
          GND

    random_vy_0.C =
          clk 

    old_oddeven.D =
          n_reset * oddeven * /cmp_vv_us_MODGEN_2.CMB 
        + /oddeven * cmp_vv_us_MODGEN_2.CMB 
        + /n_reset * /oddeven 

    old_oddeven.AP =
          GND

    old_oddeven.AR =
          GND

    old_oddeven.C =
          clk 

    MODULE_6_g1_a0_g0_u0_ga_t1_ga0_3_u3 =
          y_6.Q * MODULE_6_g1_a0_g0_u0_ga_t1_ga0_2_u3.CMB * y_7.Q 

    MODULE_1_g1_a0_g0_u0_ga_t1_ga0_3_u3 =
          x_7.Q * /ballx_6.Q * MODULE_1_g1_a0_g0_u0_ga_t1_ga0_2_u3.CMB 

    MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3 =
          x_2.Q * MODULE_1_g1_a0_g0_u0_ga_g1_ua0.CMB * x_3.Q 

    MODULE_1_g1_a0_g0_u0_ga_g1_ua0 =
          MODIN2_1.Q * MODIN2_0.Q * sub_vi_us_MODGEN_1_0.Q 
        + MODIN2_0.Q * x_1.Q * sub_vi_us_MODGEN_1_0.Q 
        + MODIN2_1.Q * x_1.Q 

    MODULE_6_g1_a0_g0_u0_ga_t1_ga0_2_u3 =
          y_4.Q * MODULE_6_g1_a0_g0_u0_ga_t1_ga0_1_u3.CMB * y_5.Q 

    MODULE_6_g1_a0_g0_u0_ga_t1_ga0_1_u3 =
          y_2.Q * MODULE_6_g1_a0_g0_u0_ga_g1_ua0.CMB * y_3.Q 

    MODULE_6_g1_a0_g0_u0_ga_g1_ua0 =
          MODIN8_1.Q * MODIN8_0.Q * y_0.Q 
        + MODIN8_0.Q * y_0.Q * y_1.Q 
        + MODIN8_1.Q * y_1.Q 

    MODULE_1_g1_a0_g0_u0_ga_t1_ga0_2_u3 =
          x_4.Q * MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3.CMB * x_5.Q 

    cmp_vv_us_MODGEN_2 =
          /x_7.Q * ballx_6.Q 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN RULE CHECK          (06:43:13)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

PARTITION LOGIC            (06:43:13)

Messages:
  Information: Checking design is strictly SYNCHRONOUS.
  Information: Initializing Logic Block structures.
  Information: Checking for duplicate NODE logic.
  Information: Forming input seeds.
  Information: Forming input seeds.
  Information: Assigning fixed logic to Logic Blocks.
  Information: Processing banked global preset, reset and output enable.
  Information: Separating output logic set to GND/VCC.
  Information: Validating Logic Block's with pre-placed signals.
  Information: Assigning floating outputs to Logic Blocks.
  Information: Separating input register logic.
  Information: Assigning initializing equations to empty Logic Blocks.
  Information: Separating output combinatorial logic.
  Information: Separating disjoint output logic.
  Information: Separating output node logic.
  Information: Compacting Logic Block interconnect.
  ................................................
  Information: Separating disjoint output logic.
  Information: Separating output node logic.
  Information: Assigning floating outputs to Logic Blocks.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (06:43:14)

Messages:
  Information: Fitting signals to Logic Block A.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Combining 'MODIN8_0' definition with input pin 'col_eq_ballx'.
  Information: Fitting signals to Logic Block B.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Combining 'MODIN2_0' definition with input pin 'row_eq_bally'.
  Information: Fitting signals to Logic Block C.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block D.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Routing signals to Logic Blocks.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

LOGIC BLOCK A PLACEMENT   (06:43:14)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(MODIN8_0)col_eq_ballx
XXXX+++X++++++++................................................................
| 1 |(MODULE_6_g1_a0_g0_u0_ga_t1_ga0_1_u3)
......X+++++++++++++++..........................................................
| 2 |(MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3)
..........X+++++++++++++++......................................................
| 3 |(random_vy_1)
..............XX++++++++++++++..................................................
| 4 |(old_oddeven)
..................XXX+++++++++++++..............................................
| 5 |(y_3)
......................XXXX++++++++XX++..........................................
| 6 |(y_5)
..........................XXXX++++XX++++++......................................
| 7 |(ymsb_6)
..............................XXXXXXXX++++++++..................................
| 8 |(y_4)
..................................XX++XXXX++++XX++..............................
| 9 |(y_2)
......................................++++XXXXXX++++++..........................
|10 |(random_vy_2)
..........................................++++++XX++++++++......................
|11 |(random_vy_0)
..............................................++++++XX++++++++..................
|12 |(MODULE_1_g1_a0_g0_u0_ga_t1_ga0_3_u3)
..................................................X+++++++++++++++..............
|13 |(MODULE_6_g1_a0_g0_u0_ga_t1_ga0_2_u3)
......................................................X+++++++++++++++..........
|14 |(cmp_vv_us_MODGEN_2)
..........................................................X+++++++++++++++......
|15 |(MODULE_1_g1_a0_g0_u0_ga_g1_ua0)
................................................................XXX+++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  16 
Total count of unique Product Terms  =  46 
Total Product Terms to be assigned   =  54 
Max Product Terms used / available   =  48 /  80   = 60.1  %


Control Signals for Logic Block A
---------------------------------
CLK pin  13 : clk
CLK pin  35 : <not used>
PRESET      : GND
RESET       : GND
OE 0        : <not used>
OE 1        : <not used>
OE 2        : <not used>
OE 3        : <not used>



                              Logic Block A
                 ____________________________________________
                 |   |= >n_reset                        |   |                 
                 |   |= >x_1.Q                          |   |                 
                 |   |> not used:47                     |   |                 
                 |   |= >MODIN8_0.Q                     |   |                 
                 |   |= >cmp_vv_us_M..                  |  2|= (MODIN8_0)col_eq_ballx 
                 |   |= >sub_vi_us_M..                  |   |                 
                 |   |= >MODULE_1_g1..  (MODULE_6_g1_a0_g0_u0_ga_t1_ga0_1_u3) =|   |                 
                 |   |= >x_7.Q                          |   |                 
                 |   |> not used:53                     |  3|= (MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3) 
                 |   |= >random_vy_2.Q                  |   |                 
                 |   |= >x_2.Q           (random_vy_1) =|   |                 
                 |   |= >old_oddeven.Q                  |   |                 
                 |   |= >random_in                      |  4|= (old_oddeven)  
                 |   |= >oddeven                        |   |                 
                 |   |= >x_3.Q                   (y_3) =|   |                 
                 |   |= >ymsb_6.Q                       |   |                 
                 |   |= >MODIN2_1.Q                     |  5|= (y_5)          
                 |   |= >y_4.Q                          |   |                 
                 |   |= >MODULE_6_g1..        (ymsb_6) =|   |                 
                 |   |= >y_2.Q                          |   |                 
                 |   |> not used:65                     |  6|= (y_4)          
                 |   |= >MODULE_6_g1..                  |   |                 
                 |   |= >MODIN2_0.Q              (y_2) =|   |                 
                 |   |= >random_vy_1.Q                  |   |                 
                 |   |= >clock_2.Q                      |  7|= (random_vy_2)  
                 |   |= >MODULE_1_g1..                  |   |                 
                 |   |> not used:71      (random_vy_0) =|   |                 
                 |   |= >y_3.Q                          |   |                 
                 |   |> not used:73                     |  8|= (MODULE_1_g1_a0_g0_u0_ga_t1_ga0_3_u3) 
                 |   |> not used:74                     |   |                 
                 |   |> not used:75     (MODULE_6_g1_a0_g0_u0_ga_t1_ga0_2_u3) =|   |                 
                 |   |> not used:76                     |   |                 
                 |   |> not used:77                     |  9|= (cmp_vv_us_MODGEN_2) 
                 |   |= >MODULE_6_g1..                  |   |                 
                 |   |= >ballx_6.Q      (MODULE_1_g1_a0_g0_u0_ga_g1_ua0) =|   |                 
                 |   |= >random_vy_0.Q                  |   |                 
                 |   |= >vrandomize.Q                   |   |                 
                 |   |> not used:82                     |   |                 
                 |   |= >y_5.Q                          |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    8  |    8  |
                 | PIM Input Connects |   29  |   36  |
                 ______________________________________
                                          45  /   52   = 86  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

LOGIC BLOCK B PLACEMENT   (06:43:15)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0>|countclk1
++X+++++++++++++................................................................
| 1 |(MODIN8_1)
......XXXX+X++++++++++..........................................................
| 2>|countclk2
..........X+++++++++++++++......................................................
| 3 |(x_1)
..............XXXX++XXXXXX++++..................................................
| 4>|win1
..................XX++++++XX++X+XX..............................................
| 5 |(sub_vi_us_MODGEN_1_0)
......................XX++++XX+X++X+++..........................................
| 6>|win2
..........................XX++++XX+X++++XX......................................
| 7 |(x_8)
..............................++++++XXXXXXXX++..................................
| 8 |(MODIN2_0)row_eq_bally
..................................++++++++++XXX+XX..............................
| 9 |(clock_2)
......................................+++++++++X++++++..........................
|10 |reverse
..........................................++++++++XXXXXXXX......................
|11 |(random_vx_1)
..............................................++++++++++++XX++..................
|12 |vrandomize
..................................................XX++XX++++++XX++..............
|13 |(MODIN2_1)
......................................................++++++XX++XXX+++..........
|14 |(random_vx_0)
..........................................................++++++++++XX++++......
|15 |(y_1)
................................................................+++X++XXXXXXXXX+
________________________________________________________________________________

Total count of outputs placed        =  16 
Total count of unique Product Terms  =  68 
Total Product Terms to be assigned   =  84 
Max Product Terms used / available   =  72 /  80   = 90.1  %


Control Signals for Logic Block B
---------------------------------
CLK pin  13 : clk
CLK pin  35 : <not used>
PRESET      : GND
RESET       : GND
OE 0        : <not used>
OE 1        : <not used>
OE 2        : <not used>
OE 3        : <not used>



                              Logic Block B
                 ____________________________________________
                 |   |= >old_oddeven.Q                  |   |                 
                 |   |= >diff.QI                        |   |                 
                 |   |= >random_in                      |   |                 
                 |   |= >oddeven                        |   |                 
                 |   |= >random_vx_1.Q                  | 14|= countclk1      
                 |   |= >MODIN2_0.Q                     |   |                 
                 |   |= >MODIN8_0.Q         (MODIN8_1) =|   |                 
                 |   |= >MODULE_1_g1..                  |   |                 
                 |   |= >MODIN2_1.Q                     | 15|= countclk2      
                 |   |= >y_0.Q                          |   |                 
                 |   |= >random_vx_0.Q           (x_1) =|   |                 
                 |   |= >cmp_vv_us_M..                  |   |                 
                 |   |= >random_vy_1.Q                  | 16|= win1           
                 |   |= >sub_vi_us_M..                  |   |                 
                 |   |= >x_8.Q          (sub_vi_us_MODGEN_1_0) =|   |                 
                 |   |= >MODIN8_1.Q                     |   |                 
                 |   |> not used:100                    | 17|= win2           
                 |   |= >row_eq_bally                   |   |                 
                 |   |= >random_vy_2.Q           (x_8) =|   |                 
                 |   |> not used:103                    |   |                 
                 |   |= >x_1.Q                          | 18|= (MODIN2_0)row_eq_bally 
                 |   |= >y_1.Q                          |   |                 
                 |   |= >win1.Q              (clock_2) =|   |                 
                 |   |> not used:107                    |   |                 
                 |   |= >ballx_6.Q                      | 19|= reverse        
                 |   |> not used:109                    |   |                 
                 |   |= >win2.Q          (random_vx_1) =|   |                 
                 |   |> not used:111                    |   |                 
                 |   |> not used:112                    | 20|= vrandomize     
                 |   |= >clock_2.Q                      |   |                 
                 |   |> not used:114        (MODIN2_1) =|   |                 
                 |   |= >n_reset                        |   |                 
                 |   |> not used:116                    | 21|= (random_vx_0)  
                 |   |= >reverse.Q                      |   |                 
                 |   |= >x_7.Q                   (y_1) =|   |                 
                 |   |= >col_eq_ballx                   |   |                 
                 |   |> not used:120                    |   |                 
                 |   |= >vrandomize.Q                   |   |                 
                 |   |> not used:122                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    8  |    8  |
                 | PIM Input Connects |   29  |   36  |
                 ______________________________________
                                          45  /   52   = 86  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

LOGIC BLOCK C PLACEMENT   (06:43:15)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0>|ballx_7
XXX+++++++++++++................................................................
| 1 |(y_6)
......XXXX++XX++++++++..........................................................
| 2>|ballx_6
..........XX++++XX++++++++......................................................
| 3 |(x_7)
..............XX++XX++XX++++++..................................................
| 4>|ballx_5
..................++++++++XX++++++..............................................
| 5 |(x_5)
......................++XX++XXXX++++++..........................................
| 6>|ballx_4
..........................++++++XX++++++++......................................
| 7 |(x_4)
..............................XX++XXXX++++++++..................................
| 8>|ballx_3
..................................++++XX++++++++++..............................
| 9 |(x_3)
......................................++XXXX++XX++++++..........................
|10>|ballx_2
..........................................++XX++++++++++++......................
|11 |(x_2)
..............................................XXXX++++XX++++++..................
|12>|ballx_1
..................................................XX++++++++++++++..............
|13 |(y_7)
......................................................++XXXX++++++XX++..........
|14>|ballx_0
..........................................................++XX++++++++++++......
|15 |(y_0)
................................................................XXXX++XX++++++++
________________________________________________________________________________

Total count of outputs placed        =  16 
Total count of unique Product Terms  =  57 
Total Product Terms to be assigned   =  67 
Max Product Terms used / available   =  61 /  80   = 76.26 %


Control Signals for Logic Block C
---------------------------------
CLK pin  13 : clk
CLK pin  35 : <not used>
PRESET      : GND
RESET       : GND
OE 0        : <not used>
OE 1        : <not used>
OE 2        : <not used>
OE 3        : <not used>



                              Logic Block C
                 ____________________________________________
                 |   |= >MODULE_1_g1..                  |   |                 
                 |   |= >y_6.Q                          |   |                 
                 |   |= >reverse.Q                      |   |                 
                 |   |= >x_8.Q                          |   |                 
                 |   |> not used:127                    | 24|= ballx_7        
                 |   |= >y_7.Q                          |   |                 
                 |   |= >MODIN8_0.Q              (y_6) =|   |                 
                 |   |> not used:130                    |   |                 
                 |   |> not used:131                    | 25|= ballx_6        
                 |   |= >MODULE_6_g1..                  |   |                 
                 |   |= >MODULE_1_g1..           (x_7) =|   |                 
                 |   |= >cmp_vv_us_M..                  |   |                 
                 |   |> not used:135                    | 26|= ballx_5        
                 |   |= >x_7.Q                          |   |                 
                 |   |= >old_oddeven.Q           (x_5) =|   |                 
                 |   |= >vrandomize.Q                   |   |                 
                 |   |> not used:139                    | 27|= ballx_4        
                 |   |= >x_2.Q                          |   |                 
                 |   |= >random_vy_2.Q           (x_4) =|   |                 
                 |   |> not used:142                    |   |                 
                 |   |= >x_1.Q                          | 28|= ballx_3        
                 |   |> not used:144                    |   |                 
                 |   |= >oddeven                 (x_3) =|   |                 
                 |   |= >x_4.Q                          |   |                 
                 |   |= >ballx_6.Q                      | 29|= ballx_2        
                 |   |> not used:148                    |   |                 
                 |   |> not used:149             (x_2) =|   |                 
                 |   |= >x_3.Q                          |   |                 
                 |   |> not used:151                    | 30|= ballx_1        
                 |   |> not used:152                    |   |                 
                 |   |> not used:153             (y_7) =|   |                 
                 |   |= >n_reset                        |   |                 
                 |   |= >MODULE_1_g1..                  | 31|= ballx_0        
                 |   |> not used:156                    |   |                 
                 |   |= >y_0.Q                   (y_0) =|   |                 
                 |   |= >sub_vi_us_M..                  |   |                 
                 |   |> not used:159                    |   |                 
                 |   |> not used:160                    |   |                 
                 |   |= >x_5.Q                          |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    8  |    8  |
                 | PIM Input Connects |   24  |   36  |
                 ______________________________________
                                          40  /   52   = 76  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

LOGIC BLOCK D PLACEMENT   (06:43:15)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0>|bally_7
XX++++++++++++++................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2>|bally_6
..........XX++++++++++++++......................................................
| 3 |(MODULE_6_g1_a0_g0_u0_ga_g1_ua0)
..............XXX+++++++++++++..................................................
| 4>|bally_5
..................XX++++++++++++++..............................................
| 5 |(MODULE_6_g1_a0_g0_u0_ga_t1_ga0_3_u3)
......................X+++++++++++++++..........................................
| 6>|bally_4
..........................XX++++++++++++++......................................
| 7 |(MODULE_1_g1_a0_g0_u0_ga_t1_ga0_2_u3)
..............................X+++++++++++++++..................................
| 8>|bally_3
..................................XX++++++++++++++..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10>|bally_2
..........................................XX++++++++++++++......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12>|bally_1
..................................................XX++++++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14>|bally_0
..........................................................XX++++++++++++++......
|15 |UNUSED
................................................................++++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  11 
Total count of unique Product Terms  =  21 
Total Product Terms to be assigned   =  21 
Max Product Terms used / available   =  21 /  80   = 26.26 %


Control Signals for Logic Block D
---------------------------------
CLK pin  13 : <not used>
CLK pin  35 : <not used>
PRESET      : <not used>
RESET       : <not used>
OE 0        : <not used>
OE 1        : <not used>
OE 2        : <not used>
OE 3        : <not used>



                              Logic Block D
                 ____________________________________________
                 |   |= >y_7.Q                          |   |                 
                 |   |= >y_5.Q                          |   |                 
                 |   |= >MODULE_6_g1..                  |   |                 
                 |   |= >MODIN8_0.Q                     |   |                 
                 |   |= >y_0.Q                          | 36|= bally_7        
                 |   |= >y_4.Q                          |   |                 
                 |   |> not used:168      not used:250 *|   |                 
                 |   |= >MODULE_1_g1..                  |   |                 
                 |   |> not used:170                    | 37|= bally_6        
                 |   |> not used:171                    |   |                 
                 |   |= >MODIN8_1.Q     (MODULE_6_g1_a0_g0_u0_ga_g1_ua0) =|   |                 
                 |   |= >x_5.Q                          |   |                 
                 |   |> not used:174                    | 38|= bally_5        
                 |   |= >y_3.Q                          |   |                 
                 |   |> not used:176    (MODULE_6_g1_a0_g0_u0_ga_t1_ga0_3_u3) =|   |                 
                 |   |= >ymsb_6.Q                       |   |                 
                 |   |> not used:178                    | 39|= bally_4        
                 |   |> not used:179                    |   |                 
                 |   |> not used:180    (MODULE_1_g1_a0_g0_u0_ga_t1_ga0_2_u3) =|   |                 
                 |   |= >y_2.Q                          |   |                 
                 |   |= >y_1.Q                          | 40|= bally_3        
                 |   |> not used:183                    |   |                 
                 |   |> not used:184      not used:258 *|   |                 
                 |   |> not used:185                    |   |                 
                 |   |= >y_6.Q                          | 41|= bally_2        
                 |   |> not used:187                    |   |                 
                 |   |> not used:188      not used:260 *|   |                 
                 |   |> not used:189                    |   |                 
                 |   |> not used:190                    | 42|= bally_1        
                 |   |> not used:191                    |   |                 
                 |   |> not used:192      not used:262 *|   |                 
                 |   |> not used:193                    |   |                 
                 |   |= >x_4.Q                          | 43|= bally_0        
                 |   |> not used:195                    |   |                 
                 |   |> not used:196      not used:264 *|   |                 
                 |   |> not used:197                    |   |                 
                 |   |> not used:198                    |   |                 
                 |   |> not used:199                    |   |                 
                 |   |> not used:200                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    3  |    8  |
                 | PIM Input Connects |   15  |   36  |
                 ______________________________________
                                          26  /   52   = 50  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

DESIGN SIGNAL PLACEMENT    (06:43:16)


Device:  c372i
Package: CY7C372I-66JC

                  1  :  GND
                  2  :  (MODIN8_0)col_eq_ballx
                  3  :  (MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3)
                  4  :  (old_oddeven)
                  5  :  (y_5)
                  6  :  (y_4)
                  7  :  (random_vy_2)
                  8  :  (MODULE_1_g1_a0_g0_u0_ga_t1_ga0_3_u3)
                  9  :  (cmp_vv_us_MODGEN_2)
                 10  :  n_reset
                 11  :  VPP
                 12  :  GND
                 13  :  clk
                 14  :  countclk1
                 15  :  countclk2
                 16  :  win1
                 17  :  win2
                 18  :  (MODIN2_0)row_eq_bally
                 19  :  reverse
                 20  :  vrandomize
                 21  :  (random_vx_0)
                 22  :  VCC
                 23  :  GND
                 24  :  ballx_7
                 25  :  ballx_6
                 26  :  ballx_5
                 27  :  ballx_4
                 28  :  ballx_3
                 29  :  ballx_2
                 30  :  ballx_1
                 31  :  ballx_0
                 32  :  oddeven
                 33  :  random_in
                 34  :  GND
                 35  :  diff
                 36  :  bally_7
                 37  :  bally_6
                 38  :  bally_5
                 39  :  bally_4
                 40  :  bally_3
                 41  :  bally_2
                 42  :  bally_1
                 43  :  bally_0
                 44  :  VCC


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    3  |    3  |
                 | Clock/Inputs       |    2  |    2  |
                 | I/O Macrocells     |   32  |   32  |
                 | Buried Macrocells  |   27  |   32  |
                 | PIM Input Connects |   97  |  156  |
                 ______________________________________
                                         161  /  225   = 71  %



                                      Required     Max (Available)
          CLOCK/LATCH ENABLE signals     1            2
          Input REG/LATCH signals        1           36
          Input PIN signals              3            3
          Input PINs using I/O cells     0            0
          Output PIN signals            32           32


          Total PIN signals             37           37
          Macrocells Used               59           64
          Unique Product Terms         183          320



----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

PRESET/RESET AND OUTPUT ENABLE COMBINATIONS

PRESET: GND
RESET : GND
Used by Logic Blocks: ABC
Total unique inputs =  48 
count of registered equations =  33 
==>OE: GND or VCC
   count of OE equations =  33 


PRESET: NONE-COMBINATORIAL
RESET : NONE-COMBINATORIAL
Total unique inputs =  30 
count of combinatorial equations =  26 
==>OE: GND or VCC
   count of OE equations =  26 

----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

TIMING PATH ANALYSIS       (06:43:16) using Package: CY7C372I-66JC

Messages:

----------------------------------------------------------------------------
Signal Name | Delay Type  |   tmax   | Path Description
----------------------------------------------------------------------------
reg::(MODIN8_0)col_eq_ballx[2]
inp::n_reset
              tS              10.0 ns    1 pass
inp::x_7.Q
---->cmp_vv_us_MODGEN_2
              tSCS            30.0 ns    2 passes
out::MODIN8_0
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::(old_oddeven)[4]
inp::n_reset
              tS              10.0 ns    1 pass
inp::x_7.Q
---->cmp_vv_us_MODGEN_2
              tSCS            30.0 ns    2 passes
out::old_oddeven
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::(y_5)[5]
inp::n_reset
              tS              10.0 ns    1 pass
inp::MODIN8_1.Q
---->MODULE_6_g1_a0_g0_u0_ga_g1_ua0
---->MODULE_6_g1_a0_g0_u0_ga_t1_ga0_1_u3
              tSCS            45.0 ns    3 passes
out::bally_5
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------
reg::(y_4)[6]
inp::n_reset
              tS              10.0 ns    1 pass
inp::MODIN8_1.Q
---->MODULE_6_g1_a0_g0_u0_ga_g1_ua0
---->MODULE_6_g1_a0_g0_u0_ga_t1_ga0_1_u3
              tSCS            45.0 ns    3 passes
out::bally_4
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------
reg::(random_vy_2)[7]
inp::random_vy_2.Q
              tSCS            15.0 ns    1 pass
out::random_vy_2
              tCO             10.0 ns  
----------------------------------------------------------------------------
cmb::countclk1[14]
inp::win1.Q
              tCO             25.0 ns    1 pass
----------------------------------------------------------------------------
cmb::countclk2[15]
inp::win2.Q
              tCO             25.0 ns    1 pass
----------------------------------------------------------------------------
reg::win1[16]
inp::n_reset
              tS              10.0 ns    1 pass
inp::x_7.Q
---->cmp_vv_us_MODGEN_2
              tSCS            30.0 ns    2 passes
out::countclk1
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------
reg::win2[17]
inp::n_reset
              tS              10.0 ns    1 pass
inp::x_7.Q
---->cmp_vv_us_MODGEN_2
              tSCS            30.0 ns    2 passes
out::countclk2
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------
reg::(MODIN2_0)row_eq_bally[18]
inp::n_reset
              tS              10.0 ns    1 pass
inp::x_7.Q
---->cmp_vv_us_MODGEN_2
              tSCS            30.0 ns    2 passes
out::MODIN2_0
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::reverse[19]
inp::n_reset
              tS              10.0 ns    1 pass
inp::x_7.Q
---->cmp_vv_us_MODGEN_2
              tSCS            30.0 ns    2 passes
out::reverse
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::vrandomize[20]
inp::n_reset
              tS              10.0 ns    1 pass
inp::x_7.Q
---->cmp_vv_us_MODGEN_2
              tSCS            30.0 ns    2 passes
out::vrandomize
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::(random_vx_0)[21]
inp::random_in
              tS              10.0 ns    1 pass
inp::clock_2.Q
              tSCS            15.0 ns    1 pass
out::random_vx_0
              tCO             10.0 ns  
----------------------------------------------------------------------------
cmb::ballx_7[24]
inp::x_8.Q
              tCO             25.0 ns    1 pass
----------------------------------------------------------------------------
reg::ballx_6[25]
inp::n_reset
              tS              10.0 ns    1 pass
inp::MODIN2_1.Q
---->MODULE_1_g1_a0_g0_u0_ga_g1_ua0
---->MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3
---->MODULE_1_g1_a0_g0_u0_ga_t1_ga0_2_u3
              tSCS            60.0 ns    4 passes
out::ballx_7
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------
cmb::ballx_5[26]
inp::x_8.Q
              tCO             25.0 ns    1 pass
----------------------------------------------------------------------------
cmb::ballx_4[27]
inp::x_8.Q
              tCO             25.0 ns    1 pass
----------------------------------------------------------------------------
cmb::ballx_3[28]
inp::x_8.Q
              tCO             25.0 ns    1 pass
----------------------------------------------------------------------------
cmb::ballx_2[29]
inp::x_8.Q
              tCO             25.0 ns    1 pass
----------------------------------------------------------------------------
cmb::ballx_1[30]
inp::x_8.Q
              tCO             25.0 ns    1 pass
----------------------------------------------------------------------------
cmb::ballx_0[31]
inp::x_8.Q
              tCO             25.0 ns    1 pass
----------------------------------------------------------------------------
cmb::bally_7[36]
inp::y_7.Q
              tCO             25.0 ns    1 pass
----------------------------------------------------------------------------
cmb::bally_6[37]
inp::y_6.Q
              tCO             25.0 ns    1 pass
----------------------------------------------------------------------------
cmb::bally_5[38]
inp::y_5.Q
              tCO             25.0 ns    1 pass
----------------------------------------------------------------------------
cmb::bally_4[39]
inp::y_4.Q
              tCO             25.0 ns    1 pass
----------------------------------------------------------------------------
cmb::bally_3[40]
inp::y_3.Q
              tCO             25.0 ns    1 pass
----------------------------------------------------------------------------
cmb::bally_2[41]
inp::y_2.Q
              tCO             25.0 ns    1 pass
----------------------------------------------------------------------------
cmb::bally_1[42]
inp::y_1.Q
              tCO             25.0 ns    1 pass
----------------------------------------------------------------------------
cmb::bally_0[43]
inp::y_0.Q
              tCO             25.0 ns    1 pass
----------------------------------------------------------------------------
reg::(random_vy_1)[204]
inp::random_vy_1.Q
              tSCS            15.0 ns    1 pass
out::random_vy_1
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::(y_3)[206]
inp::n_reset
              tS              10.0 ns    1 pass
inp::x_7.Q
---->cmp_vv_us_MODGEN_2
              tSCS            30.0 ns    2 passes
out::bally_3
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------
reg::(ymsb_6)[208]
inp::n_reset
              tS              10.0 ns    1 pass
inp::MODIN8_1.Q
---->MODULE_6_g1_a0_g0_u0_ga_g1_ua0
---->MODULE_6_g1_a0_g0_u0_ga_t1_ga0_1_u3
---->MODULE_6_g1_a0_g0_u0_ga_t1_ga0_2_u3
---->MODULE_6_g1_a0_g0_u0_ga_t1_ga0_3_u3
              tSCS            75.0 ns    5 passes
out::bally_7
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------
reg::(y_2)[210]
inp::n_reset
              tS              10.0 ns    1 pass
inp::x_7.Q
---->cmp_vv_us_MODGEN_2
              tSCS            30.0 ns    2 passes
out::bally_2
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------
reg::(random_vy_0)[212]
inp::random_in
              tS              10.0 ns    1 pass
inp::random_vy_0.Q
              tSCS            15.0 ns    1 pass
out::random_vy_0
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::(MODIN8_1)[218]
inp::n_reset
              tS              10.0 ns    1 pass
inp::x_7.Q
---->cmp_vv_us_MODGEN_2
              tSCS            30.0 ns    2 passes
out::MODIN8_1
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::(x_1)[220]
inp::n_reset
              tS              10.0 ns    1 pass
inp::x_7.Q
---->cmp_vv_us_MODGEN_2
              tSCS            30.0 ns    2 passes
out::ballx_1
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------
reg::(sub_vi_us_MODGEN_1_0)[222]
inp::n_reset
              tS              10.0 ns    1 pass
inp::x_7.Q
---->cmp_vv_us_MODGEN_2
              tSCS            30.0 ns    2 passes
out::ballx_0
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------
reg::(x_8)[224]
inp::n_reset
              tS              10.0 ns    1 pass
inp::MODIN2_1.Q
---->MODULE_1_g1_a0_g0_u0_ga_g1_ua0
---->MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3
---->MODULE_1_g1_a0_g0_u0_ga_t1_ga0_2_u3
---->MODULE_1_g1_a0_g0_u0_ga_t1_ga0_3_u3
              tSCS            75.0 ns    5 passes
out::ballx_7
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------
reg::(clock_2)[226]
inp::clock_2.Q
              tSCS            15.0 ns    1 pass
out::clock_2
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::(random_vx_1)[228]
inp::random_in
              tS              10.0 ns    1 pass
inp::random_vx_1.Q
              tSCS            15.0 ns    1 pass
out::random_vx_1
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::(MODIN2_1)[230]
inp::n_reset
              tS              10.0 ns    1 pass
inp::x_7.Q
---->cmp_vv_us_MODGEN_2
              tSCS            30.0 ns    2 passes
out::MODIN2_1
              tCO             10.0 ns  
----------------------------------------------------------------------------
reg::(y_1)[232]
inp::n_reset
              tS              10.0 ns    1 pass
inp::x_7.Q
---->cmp_vv_us_MODGEN_2
              tSCS            30.0 ns    2 passes
out::bally_1
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------
reg::(y_6)[234]
inp::n_reset
              tS              10.0 ns    1 pass
inp::MODIN8_1.Q
---->MODULE_6_g1_a0_g0_u0_ga_g1_ua0
---->MODULE_6_g1_a0_g0_u0_ga_t1_ga0_1_u3
---->MODULE_6_g1_a0_g0_u0_ga_t1_ga0_2_u3
              tSCS            60.0 ns    4 passes
out::bally_6
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------
reg::(x_7)[236]
inp::n_reset
              tS              10.0 ns    1 pass
inp::MODIN2_1.Q
---->MODULE_1_g1_a0_g0_u0_ga_g1_ua0
---->MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3
---->MODULE_1_g1_a0_g0_u0_ga_t1_ga0_2_u3
              tSCS            60.0 ns    4 passes
out::ballx_7
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------
reg::(x_5)[238]
inp::n_reset
              tS              10.0 ns    1 pass
inp::MODIN2_1.Q
---->MODULE_1_g1_a0_g0_u0_ga_g1_ua0
---->MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3
              tSCS            45.0 ns    3 passes
out::ballx_5
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------
reg::(x_4)[240]
inp::n_reset
              tS              10.0 ns    1 pass
inp::MODIN2_1.Q
---->MODULE_1_g1_a0_g0_u0_ga_g1_ua0
---->MODULE_1_g1_a0_g0_u0_ga_t1_ga0_1_u3
              tSCS            45.0 ns    3 passes
out::ballx_4
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------
reg::(x_3)[242]
inp::n_reset
              tS              10.0 ns    1 pass
inp::x_7.Q
---->cmp_vv_us_MODGEN_2
              tSCS            30.0 ns    2 passes
out::ballx_3
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------
reg::(x_2)[244]
inp::n_reset
              tS              10.0 ns    1 pass
inp::x_7.Q
---->cmp_vv_us_MODGEN_2
              tSCS            30.0 ns    2 passes
out::ballx_2
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------
reg::(y_7)[246]
inp::n_reset
              tS              10.0 ns    1 pass
inp::MODIN8_1.Q
---->MODULE_6_g1_a0_g0_u0_ga_g1_ua0
---->MODULE_6_g1_a0_g0_u0_ga_t1_ga0_1_u3
---->MODULE_6_g1_a0_g0_u0_ga_t1_ga0_2_u3
              tSCS            60.0 ns    4 passes
out::bally_7
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------
reg::(y_0)[248]
inp::n_reset
              tS              10.0 ns    1 pass
inp::x_7.Q
---->cmp_vv_us_MODGEN_2
              tSCS            30.0 ns    2 passes
out::bally_0
              tCO             24.0 ns    1 pass
----------------------------------------------------------------------------

Worst Case Path Summary
-----------------------

                     tS = 10.0 ns for MODIN8_0.D
                   tSCS = 75.0 ns for ymsb_6.T
                    tCO = 25.0 ns for countclk1



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37XFIT.EXE    19/JUN/1998  [v4.02 ] 4 IR x96

JEDEC ASSEMBLE             (06:43:16)

Messages:
  Information: Processing JEDEC for Logic Block 1.
  Information: Processing JEDEC for Logic Block 2.
  Information: Processing JEDEC for Logic Block 3.
  Information: Processing JEDEC for Logic Block 4.
  Information: JEDEC output file 'pong.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 06:43:17
