6.374 Analysis & Design of Digital Circuits
Fall 2010
Instructor: Anantha P Chandrakasan
TA: Marcus Yip
Lecture: TR11-12.30 (32-124)
Information:
6.374 examines the device and circuit level optimization of digital building blocks. Topics covered include: MOS device models including Deep Sub-Micron effects; circuit design styles for logic, arithmetic and sequential blocks; estimation and minimization of energy consumption; interconnect models and parasitics; device sizing and logical effort; timing issues (clock skew and jitter) and active clock distribution techniques; memory architectures, circuits (sense amplifiers) and devices; testing of integrated circuits. The course employs extensive use of circuit layout and SPICE in design projects and software labs.
If you have any questions please e-mail 6.374-staff@mit.edu.
Announcements
e-mail address
Thanks,
Marcus
Announced on 03 December 2010 3:16 p.m. by Marcus Yip
reminder: final project details
This will be the last reminder about details pertaining to your report and presentation:
1) Final Report:
- please turn in 4 paper copies of the 2-page report with the technical summary by 5pm 12/3 in 38-107
- please also e-mail me an electronic copy
2) Presentation:
- presentations should be 7/12/18 minutes for 1/2/3 member teams, with each person speaking for the same amount of time
- please e-mail me the slides (PPT or PDF) by 9am the morning of your presentation
There will be no office hours next week, so if you need to speak to me about the presentation, feel free to e-mail.
-Marcus
Announced on 03 December 2010 1:51 a.m. by Marcus Yip
Final Project Presentation Schedule
I've uploaded the schedule for the final presentations next week.
We've increased the length of the presentation to 7 minutes for a one student project, 12 minutes for a two student team, and 18 minutes for a 3 person team. I've updated the guidelines with this information. This will give each person roughly 5 mins to present, with the remaining time for questions. During the presentation, I will hold up a sign to indicate that there is 1 minute remaining, upon which you will have 1 minute to wrap up. I would suggest that you practice the presentation beforehand to make sure you adhere to this time limit.
-Marcus
Announced on 29 November 2010 6:42 p.m. by Marcus Yip
Important - Final Project Information
I have a few announcements to make about the final project report and presentation:
1) I've uploaded a document with project report and presentation guidelines. Please read this carefully as it contains important information about both the report and final presentation.
2) Project reports with the technical summary sheet are due Thursday (12/2) at 5pm in 38-107. You can find the project report templates (MS Word and Framemaker) as well as a sample project report on Stellar. You must follow the style guidelines provided in these templates.
3) Final project presentations will take place during two separate sessions on 12/7 and 12/9. Please e-mail me your preferred presentation date by this Thursday (11/25). We will try to accomodate your preference.
Please let us know if you have questions. Also, please try to keep Prof. Chandrakasan and myself informed about your progress on your final projects.
-Marcus
Announced on 22 November 2010 9:46 p.m. by Marcus Yip
Problems working remotely
Many of you have been having problems with Cadence RTL compiler and/or Encounter when working remotely from home. Please try to do the ASIC flow question in 38-301 to avoid running into problems because they have been specially set up for the CAD tools.
Thanks,
Marcus
Announced on 14 November 2010 10:50 a.m. by Marcus Yip