6.775  CMOS Analog and Circuit Design

Tips for simulation speed

Use these lines to improve your speed

analysis(
'tran
?stop "20.1u"
?errpreset "conservative"
?strobeperiod "1n" <<<<<<<<< IMPORTANT

)
option(
'iabstol "1e-13"
'vabstol "1e-7"
'reltol "1e-4"
'multithread "on" <<<<<<<<< IMPORTANT
)
saveOption( 'save "selected" ) <<<<<<<<< IMPORTANT
save( 'v "/vo_adc_eval"
"/I0/vdac"
) /* save node voltage */
save( 'i "/VDD/PLUS"
"/VREF/PLUS"
) /* save current (for power calculation later )
temp(27)
run()

Announced on 13 May 2014  5:04  p.m. by Do Yeon Yoon

Athena capacity and simulation speed issues

Lots of students have athena account capacity and simulation speed issues because your final project simulation file size is much bigger.
To avoid this issue,
Go to home directory/simulation folder and delete your previous simulation results regularly.

Also, you can reduce your simulation file size in Cadence. This is IMPORTANT for your very final simulation because this method enhance your simulation speed as well.
Previously you saved all signals so it caused this capacity and speed issues. We need to save selected signals(e.g. ADC outputs) only.
1) In Cadence,
Analog Design Environment --> Outputs tab --> Save all.. --> change allpub (default) to selected
Now you need to specify the nets you want to save.
Analog Design Environment --> Outputs tab --> To be Saved --> Select On Schematic --> Click the nets on your schematic window

2) In Ocean,
Remove "'saveOption( 'currents "all")". Also replace "saveOption( 'save "all")" with "saveOption('save "selected")" along with save(...) function as
shown in the ADC test tutorial.

Don't forget that you cannot check all signals if you use this method. (Don't use this method when you are debugging some problems. You might be able to waste your time !)

Announced on 07 May 2014  10:07  a.m. by Do Yeon Yoon

Tips to reduce long transient simulation time for finding ENOB

First, please note that running Cadence simulation on laptop computers
over remote Athena session might often FAIL WITHOUT REASON.
Because almost always 50-100 people are using the remote Athena
servers using their laptop computers through {x.dialup, linerva,
linux, express.dialup}.mit.edu, remote Athena servers are slow
and UNRELIABLE. For this reason, if all at possible, please avoid
running Cadence on your laptop computers for final project
transient simulation to find ENOB.
As a solution to this Cadence simulation failures on laptop computers,
if you need a long time transient simulation with Cadence for final project,
please use Athena workstations around the campus. You could visit one
of the following places to use the Athena workstations: 38-530,
Rotch library, Barker library, Hayden library, Dewey library, W20-575,
56-129, 37-312, 38-370, 2-225. More complete list of Athena workstation
rooms is available here: http://amap.mit.edu
In addition, please carefully read the tips below to reduce the
transient simulation time. With these in mind, the transient
simulation to find ENOB could be completed within 4-5 hours:
1. Use physical Athena workstations, not laptop computers
2. When getting ENOB, before running 512- or 1024-point FFT for
project reporting, please run 64-point FFT to get a quick result to
see there is any potential problems. Going for 64-point FFT
will make your simulation x16 faster compared to 1024-point.
An example parameter set for ENOB calculation from 64-point FFT
is shown below.:

* Transient simulation stop time (IMPORTANT) : 1.25 us + initial response
* First FFT bin freq : 800 kHz
* Test input signal : 6400 kHz
For 128-point FFT, an example parameter set could be
* Transient simulation stop time (IMPORTANT) : 2.5 us + initial response
* First FFT bin freq : 400 kHz
* Test input signal : 3200 kHz
3. Enable 'multithread' option as shown in the ADC test tutorial.
This option set up the simulator to use multiple CPUs in the same
time. If the design is large, it will reduce the run time by more than 2x.
4. Remove "'saveOption( 'currents "all")". Also replace "saveOption( 'save "all")"
with "saveOption('save "selected")" along with save(...) function as
shown in the ADC test tutorial.
5. Also, in order to reduce design iterations, please verify that your
SAR ADC can convert DC input signals (min, max, medium of input
range) as expected by running a short transient simulation only
to produce one sample conversion (typically less than 40 ns simulation
stop time with 50 MSPS ADC).
We understand this long-time Cadence simulation is frustrating.
Since even 1-2 weeks of transient simulation time is not rare
with a more advanced design beyond the level of 6.775 final project,
we hope the ENOB simulation would be a valuable experience
at the end of day though it might be tough for now.

Announced on 28 April 2014  10:52  a.m. by Do Yeon Yoon

PS7 announcement

#1 When you check your delay, use 0.6V for the output differential
voltage instead of 1.8V

#2 For an input referred noise simulation, a new tutorial was
uploaded.

Announced on 27 April 2014  9:58  p.m. by Do Yeon Yoon

Midterm quiz results

Please pick up your quiz from Professor Lee's office (39-517) on 4/18.

Average : 13.563
STDEV : 6.088

You can check the solution and histogram on the website.

Announced on 17 April 2014  5:46  p.m. by Do Yeon Yoon