6.012  Microelectronic Devices & Circuits

PSs #9 and #10; BJTs on Final; DPs

PSs #9 and #10: The last set of #10 have been graded (some regrading had to be done) and now all are available outside 13-3058. I am still looking for #9 grades from those of you who picked up your graded sets early. 22 people have already responded; I hope to e-mail those who haven't during the final tomorrow (if there are not a lot of questions). I also have a few PS's (various numbers) turned in late that are still being graded.

BJTs on the Final: BJTs will not appear in any circuit problems, but you may find a small question or two on their basic operation. Also, keep in mind the content of 6.012 evolves over time so some of the previous final exams have questions that are not appropriate for this semesters edition; the problem sets and lecture notes are a better indication of what will and will not be on the exam.

DPs: The DPs are still being graded and we want to have them for reference during grade assignment on Thursday, so you will not be able to pick them up until Friday in 13-3058.

Announced on 18 May 2008  9:53  a.m. by Clifton Fonstad

DP Answer Sheet; DP Report

The Excel file of the answer sheet has been posted and is ready for use. You will should fill it in and submit it on-line through Stellar. Print it out also and use it as the cover sheet of your report.

Your report should basically tell us where the numbers you submit as your design came from. Tell us the reasoning you used to arrive at the values for the widths, lengths, and bias conditions (voltages and currents) and how you determined the performance values you predict. Also include the reference voltages established at points A, B, C, and D by your bias trees. You do not have to rederive the equations you have been given in lecture and/or on the design problem foils. Use a copy of your completed answer sheet as the cover. There is no need to have an abstract.

Announced on 08 May 2008  2:29  p.m. by Clifton Fonstad

DC Offset Voltage Foils; Voltage Gains

DC Offset Voltage: The DC Offset Voltage is the differential voltage, vIN1-VIN2 that must be applied to the amplifier to make the output voltage, vOUT, zero. It requires that the voltage on the high impedance node (the drain of Q21) be adjusted to the proper value and thus depends on the voltage gain from the input to that point, rather on the overall voltage gain of the amplifier. I have posted a set of foils on the offset voltage under Lecture 24. They have also been added to the Design Problem Collection as Slides 30 through 35.

Voltage Gains: I would like you to give the voltage gains with a 300 Ohm resistor connected to the output.

Announced on 07 May 2008  5:35  p.m. by Clifton Fonstad

Answers to Frequently (at least once) Asked DP Questions

1. "Kmin" was used to in the original DP statement to be the K of a transistor with W = Wmin and L = Lmin, but the K of a device with L = 2Lmin is smaller so we have eliminated the Kmin terminology and just say "K of a minimum size device."
2. Calculate the voltage gains with a 300 Ohm load attached to the output.
3. State VDS and VGS values with vIN1 = vIN2 = 0 for all transistors except Q19, Q21, and Q24 thru 29. For those transistors state the values when the output voltage, vOUT, is zero.
4. Specification 7 has been rephrased: The value of |vID| (=|vIN1-vIN2|) required to make vOUT = 0 must be less than 5 microvolts.
5. The |vIC|min spec was very confusing to staff and student both, so it has been restated as "vIC,max ≥ 0.8 V; vIC,min ≤ -0.8 V" and is now perfectly clear. Similarly, the |vOUT| spec has been restated as "vOUT,max ≥ 0.6 V; vOUT,min ≤ -0.6 V."

Announced on 04 May 2008  11:54  a.m. by Clifton Fonstad

Design Problem Postings on Stellar

A pdf file containing a collection of thirty (30) slides taken from Lectures 20, 21, and 22 dealing with various design problem relevant issues has been posted in the Design Problem section of the web site. The only thing not discussed is the desgin of the bias trees, but I think that has been adequately covered in the problem sets; if you still have questions ask a staff member. As I hope is clear from lecture, you should In general try to bias the transistors as close to threshold as you can since high frequency performance is not an issue in this design problem (that is next week's topic). Please notify me of any errors or confusing items you find so I can address them for everyone's benefit. A mock-up of the answer sheet has been posted also. Finally, the staff has worked hard to provide you with a rainy week end to help you concentrate on your design problem solution and your other assignments due next Friday. Enjoy.

Announced on 03 May 2008  11:49  a.m. by Clifton Fonstad