6.012 Class Home

6.012 Microelectronic Devices & Circuits

Spring 2011

Instructors: Dimitri A Antoniadis, Clifton G Fonstad

TAs: Shaya Famenini, Philip Godoy

Lecture: TR11 (32-155)
Recitations: WF 1 P.M. and 2 P.M. (36-153)
TA Office Hours #1: M 4-5:30 (36-156)
TA Office Hours #2: T 1-2:30 (24-316)

What is Different this Time, and Where to Find Things:

With Prof. Fonstad lecturing, 6.012 will differ somewhat from recent semesters which have tended to focus exclusively on traditional MOS field effect transistors (MOSFETs) and circuits. This semester, in addition to those topics, we will also learn about light emitting diodes (LEDs), semiconductor photodetectors and solar cells, charge-coupled imagers (CCDs), fully-depleted MOSFETs, and bipolar junction transistors (BJTs). We will also develop circuit models for BJTs and for sub-threshold and fully-depleted MOSFETs, and discuss circuit applications of these devices.

The lecture slides and all of the handouts can are available on line under "Materials" to the left, and paper copies of most items can found outside the course office, 13-3058.

The text book, "Microelectronic Devices and Circuits" by Clifton G. Fonstad, Jr., is available on line at no charge and can be downloaded at: http://dspace.mit.edu/handle/1721.1/34219 . Paperback copies can be purchased from CopyTech in 11-004 for approximately $20.00. (If the cover of the copy they sell you says "Spring 2009" rather than "Fall 2011" do not worry; they are identical inside.)

OCW archive available

Announcements

Quiz Review Questions Uploaded + Pset Grades

Since some of you asked, we uploaded a soft copy of the questions we went over in the quiz review today.
(Final 2008, Q1 & Q4 and Final 2009, Q4)
Also the problem set grades are available on the gradebook part of the website. You can check if none (that you have submitted) is missing.
Btw, in Pset10, Q4, last part, if you got Vout_max=1.8V and points are deducted, let us know and we will fix your grade for this pset.
Good luck with all your finals and the plans afterwards!

Announced on 14 May 2011 11:14 p.m. by Shaya Famenini

Few comments on DP

1) Vth is 26mV. (Which matches the characteristics you're given for the BJTs.)
2) When filling in the spreadsheet (which also serves as a cover sheet for your report), mention the values of VCEs and VDSs in a closed loop structure, i.e. when the external feedback is connected and Vout=0 at DC bias. For instance this means |VCE23|=|VCE24|=1.5V.
3) As most of you already know, you can't assume VBE equal to 0.6V. You should calculate the exact values, for instance for bias or swing cases.
4) And finally, when you're deciding about IQ19 and IQ22, make sure that they can provide enough current for bases of Q23 and Q24 when the swing is maximum.
5) If you think you have any last minute questions tomorrow, let us know by email and we will be available 1-3pm.
Good luck w/ finalizing your design and putting the report together.

Announced on 05 May 2011 6:52 p.m. by Shaya Famenini

Design Competition; No Recitation Friday

We want to challenge those of you who find the design problem fairly straightforward to strive to get the highest gain you can while keeping the power dissipation low. When you submit your design on the spread sheet, a figure of merit will be calculated (you can see the formula by clicking on the corresponding cell of the spread sheet). We will award 10 extra points to each of the three designs with the highest figures of merit that also meet all of the design specs, and we will award 5 extra points to each of the three designs with the next highest figures of merit that also meet all of the design specs (i.e. 1, 2 and 3 get +10 pts and 4, 5, and 6 get +5 pts).

There will not be a formal recitation on Friday, but the TAs will be available during their regular recitation hour to answer last minute questions.

Announced on 03 May 2011 10:55 p.m. by Clifton G Fonstad

Extra office hours & Writeup format

Philip and I are having extra office hours this week for design project questions in the following days:
Wednesday 3-4:30pm in 24-316, and Thursday 4-5:30pm the same place.

Regarding the format of writeup, you essentially need to show in detail your thinking process; how you decided to choose the dimensions and biases of each transistor and how you met the specs. The report doesn't need to be typed, but it's essential for it to be legible and well organized.

Good luck with the design and let us know if you had any questions.

Announced on 03 May 2011 9:01 p.m. by Shaya Famenini

Few comments on Pset10

1) Regarding the last part of problem 1, the actual labels of transistors in your design problem circuit is one less of labels mentioned in the question. (i.e. gm4 stands for gm3 and go10 should be go9 etc.)
2) In problem 2, be careful on what rt you use in calculating the output resistance of the common gate stage.
3) In problem 3, when B & C are connected, you can use symmetry if VDS3 is needed.
4) In problem 3) part h), VGS6 should be calculated instead of VGS3 that the question is asking for. (Think about the two equations two unknowns you need to solve to find Vout_max.)
5) In problem 5, Q5 and Q6 are identical (same area), where as Q7 is differently sized.
Finally, hope you enjoyed working through this interesting and educational pset.

Announced on 21 April 2011 4:16 p.m. by Shaya Famenini

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