6.374 Anal& Design: Digital Circuits
Fall 2009
Instructor: Anantha P Chandrakasan
TA: Mahmut Ersin Sinangil
Lecture: TR11-12.30 (32-124)
Information:
6.374 examines the device and circuit level optimization of digital building blocks. Topics covered include: MOS device models including Deep Sub-Micron effects; circuit design styles for logic, arithmetic and sequential blocks; estimation and minimization of energy consumption; interconnect models and parasitics; device sizing and logical effort; timing issues (clock skew and jitter) and active clock distribution techniques; memory architectures, circuits (sense amplifiers) and devices; testing of integrated circuits. The course employs extensive use of circuit layout and SPICE in design projects and software labs.
If you have any questions please e-mail 6.374-staff@mit.edu.
Announcements
Project Reports & Quiz/HW scores
As you already know, project reports are due tomorrow (5pm). You can bring your projects to 38-301. As explained in the guidelines document on the website, you are going to:
(a) submit 4 paper copies of (a) your two-page report and (b) the technical summarycover sheet to Room 38-107
AND
(b) email your two-page report in PDF format to 6.374-staff@mit.eduPresentation.
Today, in class, we handed out stripes showing your scores from quizes and all assignments. If you could not attend today's class, you can pick yours from 38-107 tomorrow. Please check your grades carefully to avoid any mistakes.
Finally, if you haven't picked up your graded quiz/assignments, you can also pick it up from 38-107.
Thanks,
-Mahmut Ersin
Announced on 03 December 2009 7:40 p.m. by Mahmut Ersin Sinangil
Project Presentation Schedule
Presentation schedule for final projects is added to the stellar website.
Thanks,
-Mahmut Ersin
Announced on 02 December 2009 11:52 a.m. by Mahmut Ersin Sinangil
Final Project Report
Below are some important information about the final project:
1) Project reports are due Thursday (12/3) at 5pm. Project report templates (MS Word and Framemaker) as well as a sample project report are uploaded to the website. You must follow the style guidelines provided in these templates.
2) Also added to the website is a document with guidelines for report and presentation. Please carefully read these guidelines and let me know if you have questions.
3) Final project presentations will take place in two separate sessions on 12/8 and 12/10. Please e-mail me your preference for the presentation schedule by Tuesday (12/1) at the end of the class. We will try to place your presentation on your prefered date, however, it is not guaranteed. I will e-mail presentation schedule next week.
Please let us know if you have questions. Also, please try to keep Prof. Chandrakasan and myself informed about your progress on your final projects. Feel free to e-mail or come to office hours if you need help.
Thanks,
-Mahmut Ersin
Announced on 28 November 2009 8:36 p.m. by Mahmut Ersin Sinangil
Problem Set #5
Hi everyone,
Clarification about problem set 5: The accumulator verilog code and useful scripts are located in /mit/6.374/cadence/acc/
You should first add 6.374 locker to be able to access these files.
Please let me know if you have questions.
Thanks,
-Mahmut Ersin
Announced on 10 November 2009 4:59 p.m. by Mahmut Ersin Sinangil
Pset2 Graded, Office Hours, Typo in 2007 Quiz 1 Solution
A few announcements for 6.374:
1) Your problem sets (pset2) are graded and you can pick them up from 38-107.
2) Since yesterday was a holiday, I am going to have office hours today and tomorrow between 4-6pm in 38-301. This change is only for this week and I will continue the regular schedule of MW 4-6pm starting next week.
3) There is a typo in the solution of 2007 Quiz 1. In Problem 2-c, input transitions in solution are different than the original question in the quiz. The answer for the original question should be 1-3-2 (from left to right).
Thanks,
-Mahmut Ersin
Announced on 13 October 2009 2:48 p.m. by Mahmut Ersin Sinangil
