6.012  Microelectronic Devices & Circuits

1) For those of us that didn't have enough time to cover this in tutorials, an example of finding w_LO* using short circuit time constant method is posted on stellar (under general section).

2) Unfortunately there aren't solutions for past final exams. Jack and I will solve some of them in the quiz review session. Beyond that, you can use office hours to ask questions if you're not sure about a problem.

3) Quiz review session for the final exam is on Saturday, 3-5pm in the lecture room (4-237).

4) I will have my office hour on Monday 11am-1pm, and Jack will have his on Monday 2-4pm.

5) Good luck with all your finals!

The 6.012 Staff encourages you to complete an evaluation of 6.012 for the HKN Course IV Underground Guide on the web at:  https://sixweb.mit.edu/student/evaluate/6.012-f2009 

Feedback on your experience this semester is valuable to the course staff as well as to prospective 6.012 students in the future, so please take a few minutes to complete this semester's evaluation form.  The site will be open from December 7 thru December 11.

The DC voltages we asked you to report, are for the case of Vout=0.
About what to present in your write up, you need to show how you met the specs, your thought process and the reasoning behind selecting biases and sizes.
Although there is no need to type your report, it is absolutely essential that it is legible and easy to follow.
And at the end, hope you enjoyed this design project as much as the staff did.

As discussed in Lectures 22 and 23 (and in the set of slides posted under Lecture 22 on Stellar), Q13 and Q13' have no impact on the difference-mode gain of the current mirror stage and thus it is the same as it would be if neither transistor was in the circuit.  However, Q13' makes the common-mode gain 1.5 (whereas it would be 1 if Q13' was not in the circuit) and you should use this value when calculating the common-mode gain of your design.  The performance specifications for the common-mode voltage gain and the common-mode rejection ration in the Dec. 1 version of the Design Problem statement, the one now posted on Stellar, have been adjusted to be consistent with this value. 

Current Mirror Stage:  Because this stage is biased by the Lee Load and does not have it's own current source bias shared by both legs of the differential circuit, it is no longer necessary to have the two legs of the circuit (Leg 1 = Q11,Q13',Q14; Leg 2 = Q12, Q13,Q15) biased at the same drain/collector currents.  This lets you bias one leg at a low current level to conserve power, and the other leg at a larger current level to lower the output resistances of the MOS transistors in order to get the low amplifier output resistance specified.  Since vGS on Q11 and Q12 is set by the Lee Load, the way to change the bias current levels is by changing the transistor widths.

Amplifier Output Resistance:  There seems to be some confusion as to how this is to be calculated.  What is specified is the small signal output resistance about zero bias.  This resistance is made up of the parallel combination of the output resistances of the two paths of the output circuit (Path 1 = CM,Q17,Q20; Path 2 = CM,Q18,Q21).  For example, the total output resistance will be 10 Ohms, if each of these paths has an output resistance of 20 Ohms.

Maximum Output Voltage Swing:   This spec is decoupled from the amplifier output resistance spec.  The main concern here is that you take into account the increased base-to-emitter voltage required to turn Q20 on sufficiently to supply 15 mA to the 50 Ohm load when the output goes positive, and similarly take into account the increased emitter-to-base voltage required to turn Q21 on sufficiently to sink 15 mA through the 50 Ohm load when the output goes negative.  You have to be certain that these voltages and the voltages across the load (0.75V+vBE20 in one case, and -0.75V-vEB21 in the other) are not so large that they push either Q16 or Q19 out of saturation.

Common Mode Voltage Gain and Common Mode Rejection Ratio:  The specs on these two items have been changed in the Dec. 1 version of the Design Problem statementm (which is the one currently posted on Stellar) to be consistent with the impact of Q13' on the current mirror stage common-mode voltage gain.