From bloom-picayune.mit.edu!mintaka!olivea!samsung!sdd.hp.com!zaphod.mps.ohio-state.edu!cis.ohio-state.edu!ucbvax!CORONA.ITD.MSSTATE.EDU!turner Fri Aug 16 13:22:30 EDT 1991 Article: 373 of comp.lang.vhdl Path: bloom-picayune.mit.edu!mintaka!olivea!samsung!sdd.hp.com!zaphod.mps.ohio-state.edu!cis.ohio-state.edu!ucbvax!CORONA.ITD.MSSTATE.EDU!turner From: turner@CORONA.ITD.MSSTATE.EDU (steve turner) Newsgroups: comp.lang.vhdl Subject: VHDL models available Message-ID: <9108161519.AA18060@Corona.ITD.MsState.Edu> Date: 16 Aug 91 15:19:36 GMT Sender: daemon@ucbvax.BERKELEY.EDU Lines: 74 VHDL Standard Component Library Version 2.1 A new release of VHDL standard component models is now available free-of-charge from the Institute for Technology Development. The library includes 23 TTL component models and a functional model of the Am29C01 4-bit ALU. The following models are included in Version 2.1: SN54xx00 quad 2-input NAND SN54xx02 quad 2-input NOR SN54xx04 hex inverter SN54xx08 quad 2-input AND SN54xx10 triple 3-input NAND SN54xx109 dual JK flip-flop SN54xx11 triple 3-input AND SN54xx112A dual JK flip-flop SN54xx138 3-to-8 decoder SN54xx140 dual 4-input NAND SN54xx161A 4-bit binary counter SN54xx175 quad D flip-flop SN54xx20 dual 4-input NAND SN54xx21 dual 4-input AND SN54xx251 8-to-1 mux SN54xx27 triple 3-input NOR SN54xx280 9-bit parity generator SN54xx30 8-input NAND SN54xx32 quad 2-input OR SN54xx33 quad 2-input NOR w/ open-collector outputs SN54xx368A hex inverting bus driver SN54xx38 quad 2-input NAND w/ open-collector ouptuts SN54xx86 quad 2-input XOR full_adder a simple structural example using the '86 and '00. Am29C01 4-bit ALU Each of the TTL models (SN54xx) includes a detailed timing module characterized with MIN/TYP/MAX delays for each of three TTL families (54, 54S, and 54LS). Models also alter propagation delays according to voltage, temperature, and capacitive loading. These models were written in accordance to the EIA-567 Commercial Component Specification and the VHDL Data Item Description. Each model include a WAVES test bench and a full set of test vectors. The Am29C01 is a functional model (no timing). The model is decomposed into 10 blocks, each with its own WAVES test bench. The top-level structural model includes a WAVES test bench and a complete set of test vectors. A brief User's Guide is included with the library. The User's Guide is in PostScript format. ------------------------------------------------------------------------------ The VHDL Standard Component Library is available free-of-charge via Internet FTP. The library is also distributed on 1/4" cartridge tape in UNIX tar format. There is a $50 media distribution fee for the cartridge tape. A licence agreement is required to prohibit unauthorized distribution of the models. For more information, send a request to model@itd.msstate.edu or contact Dan Johnson / CAD Section Manager Institute for Technology Development Advanced Microelectronics Division 1 Research Blvd / Suite 205 Starkville, MS 39759 phone (601) 325-2240 fax (601) 325-8144