\documentstyle[newcen,utility,margins,11pt]{report}
\title{Code Appendices for 6.111 C Simulator}
\author{Mark W. Eichin}

\begin{document}
\maketitle
\newpage
\tableofcontents
\newpage

\newcommand{\getcode}[2]{\chapter{#2}\par\begin{frepcode}{#1}}

\appendix

\getcode{../src/builder.c}{builder.c --- Common connecting procedures}\end{frepcode}
\getcode{../src/chains.c}{chains.c --- Macro and Sugar definitions}\end{frepcode}
\getcode{../src/debugdisps.c}{debugdisps.c --- Debugging structure
print procdures}\end{frepcode}
\getcode{../src/getblocks.c}{getblocks.c --- Memory Allocator Interface}\end{frepcode}
\getcode{../src/master.c}{master.c --- Simulator Driver Loop}\end{frepcode}
\getcode{../src/process.c}{process.c --- Event Processor}\end{frepcode}
\getcode{../src/mysim.c}{mysim.c --- User Simulation Template}\end{frepcode}
\getcode{../src/demo.c}{demo.c --- Demo User File}\end{frepcode}

\getcode{../src/awk/mkchn.awk}{mkchn.awk --- Macro Definition Builder}\end{frepcode}
\getcode{../src/awk/mkfunc.awk}{mkfunc.awk --- Function Declaration
Builder}\end{frepcode}

%%%\getcode{../src/Makefile}{Makefile --- Construction Makefile}\end{frepcode}

\getcode{../src/funclib/and.c}{funclib/and.c --- Primitive AND Gate}\end{frepcode}
\getcode{../src/funclib/or.c}{funclib/or.c --- Primitive OR Gate}\end{frepcode}
\getcode{../src/funclib/xor.c}{funclib/xor.c --- Primitive XOR Gate}\end{frepcode}
\getcode{../src/funclib/not.c}{funclib/not.c --- Primitive Inverter}\end{frepcode}
\getcode{../src/funclib/tristate.c}{funclib/tristate.c --- Primitive
Tristate Driver}\end{frepcode}
\getcode{../src/funclib/dff.c}{funclib/dff.c --- Primitive D-type Flip-Flop}\end{frepcode}
\getcode{../src/funclib/delay.c}{funclib/delay.c --- Primitive Delay Element}\end{frepcode}
\getcode{../src/funclib/pout.c}{funclib/pout.c --- Primitive Output
Printing Element}\end{frepcode}

%%%\getcode{../src/funclib/Makefile}{funclib/Makefile --- Construction
%%%Makefile}\end{frepcode}


\end{document}

