Designing digital optical computing systems: power distribution and cross talk

Jonathan P. Pratt and Vincent P. Heuring

When this work was performed, both the authors were with the Boulder Optoelectronic Computing Systems Center and Department of Electrical and Computer Engineering, University of Colorado,

Campus Box 425, Boulder, Colorado 80309-0425. They are now with the Department of Radiology, University of Colorado Health Sciences Center, Box A034, 4200 East Ninth Avenue,

Denver, Colorado 80262.

Abstract

Complex optical computer designs must implicitly or explicitly allow for power budgeting, to compensate for cross talk and loss in both devices and interconnections. We develop algorithms for calculating the system cross talk and power loss in optical systems, using a graph-theoretic model. Devices are modeled as directed graphs with nodes representing inputs and outputs, and edges are weighted with the power relationships between nodes. Systems are modeled by interconnecting the individual device graphs in a manner that reflects the connectivity of the system. A system’s power budget is efficiently computed by a depth-first search of its graph. The algorithms have been incorporated into an optical computer-aided design system that is now being used to design a bit-serial optical computer containing hundreds of components.

Key words: Optical computing, optical systems, optical communications, power loss, cross talk, graphs.

\begin{matrix}c \\ ◯ \end{matrix} Optical Society of America, 1992.

1. Introduction

We describe a technique that facilitates the design of digital optical computers and other complex optical circuitry, such as optical communications systems. Although there has been some discussion in the literature of power budgeting in optical systems,^{1,2} the treatment has been limited to relatively uncomplicated applications, in which heuristics and simple analysis are sufficient to estimate power loss and cross talk of the system from the loss and cross talk of individual components. The primary motivation for this research is to implement a storedprogram bit-serial optical computer,^{3,4} containing hundreds of components, interconnected in quite complex fashion. In such a system, simple heuristics for power loss and cross talk estimation such as are described in Refs. 1 and 2 are inadequate because a given optical signal might take any one of a multitude of paths before being detected and thus doing useful work. The methods developed here are applicable to a wide variety of optical systems besides optical computing systems, such as optical communications systems and optical signal processors.

In a previous paper^{5} we discussed the use of a graph-theoretic technique for synchronizing optical systems that rely on time of flight rather than latching or gating for synchronization. In this paper we extend these graph-theoretic methods to the estimation of cross talk and loss in optical systems.

2. Power Loss and Cross Talk in the System

A. Introduction

Appropriate signal levels must be maintained in any digital optical system that uses signal level thresholds to encode transmitted information. Usually a high-level signal represents a logic 1 and a low-level signal represents a logic 0. In these systems the device characteristics of importance are power loss and cross talk. Power loss quantifies the attenuation of optical power in devices. Cross talk represents the addition of extraneous optical power to signals transmitted by these devices. …

… We present a graph-theoretic device model that permits efficient and complete power analysis of optical systems. By tracking certain power–related quantities, we can determine the worst–case operating conditions of a system, and optimal logic thresholds can be computed.

The following discussion assumes either that loss and cross talk are independent of wavelength or that linewidths are small enough to permit these variations.

B. Power Levels and Correct Device Operation

Here we discuss the type of power information desired from a system model. Since the objective is to find weak points in the system power flow, only power extremes are considered. Power extremes are the cross talk and signal levels obtained when the worst possible combinations of device states and input power levels are assumed. The power extremes at detection points are of particular interest, because these are the locations where design flaws are expressed through signal misinterpretation. Detection points are places where signal power is interpreted. Detection points in a system may be control points where the signal level is used to control a device; at the input to a logic gate, for example. Or they may be output points where the power level is detected and conveyed to an output subsystem as a data stream. That distinction is irrelevant for this discussion, and we will refer to detection points in both of these cases. Consider the problem of correctly interpreting a bit stream at some arbitrary detection point. Figure 1 depicts a stream of 1’s and 0’s arriving at a detection point. P_{D} represents the power detection threshold of the detector: that power level below which the detector detects a 0 and above which it detects a 1. P_{S1} and P_{S2} define a safety zone around P_{D}. They are based on the uncertainty in P_{D} and are established so that the chance of erroneous signal interpretation is negligible. By definition, the device will operate correctly as long as all 1’s arriving at the detection point have power levels greater than P_{S1} and all 0’s arriving at the detection point have power levels less than P_{S2}. The weakest 1 arriving at the detection point under all conditions from all possible paths to the point is defined as P_{1min}, and similarly, the strongest 0 is defined as P_{0max}. Proper device operation can be ensured if the following relations are met:

P_{0max} < P_{S2} < P_{D} < P_{S1} < P_{1min}. (1)

It is also desirable to have information about P_{max}, the maximum power level that can occur at the inputs to a given device. A power detector may provide erroneous results when the power of a logic 1 arriving at a detection point is too large; that is, when P_{max} exceeds P_{D} by some large amount. A second and more important reason for computing P_{max} is that it makes the major contribution to cross talk, as discussed below. Knowledge of the power triple P_{0max}, P_{1min}, and P_{max} at each device in a system permits the tracking of power levels throughout the entire system.

C. Modeling the Device

Here we discuss the means for calculating the power triples P_{0max}, P_{1min}, and P_{max} at the outputs of a given device, given the values of the triples at each of its inputs. …

… The power triple for the jth output of a device is computed from the input triples and the coupling terms as follows:

P_{1min}(out)_{j} = \begin{matrix}min \\ s ∈ states \end{matrix} \{ \begin{matrix}min \\ inputs i \end{matrix} [P_{1min}(in)_{i} − L_{ij}(s)]\}, L_{ij}(s) ∈ loss,  (2)
P_{0max}(out)_{j} = max ; s ∈ states ∑_{inputs i} \{ \begin{matrix}P_{max}(in)_{i} − L_{ij}(s) , L_{ij}(s) ∈ cross talk, \\ P_{0max}(in)_{i} − L_{ij}(s) , L_{ij}(s) ∈ loss, \end{matrix}  (3)
P_{max}(out)_{j} = max ; s ∈ states ∑_{inputs i} P_{max}(in)_{i} − L_{ij}(s).  (4)

Equation (2) states that the power of the minimum 1 emerging from the jth output of the device will be the minimum over all possible states of the minimum over all possible inputs having loss terms of the minimum 1’s arriving at those inputs minus the loss terms. Equation (3) states that the power of the maximum 0 emerging from the jth output of the device will be the maximum over all possible states of the sum of the inputs of (P_{max} minus the cross talk term) for those inputs that have cross talk terms in that state, plus (P_{0max} minus the loss term) for those inputs that have loss terms in the particular state. Equation (4) states that P_{max} emerging from the jth output of the device will be the maximum over all the possible states of the sum over all the i inputs of P_{max} minus the loss or cross talk between each of those inputs and the output j. These equations are in representational format, as the subtraction of the loss parameters implies logarithmic units for power; so in practice the summations require conversion to linear units. …

The loss and cross talk terms L_{ij} are the edge weights mentioned above. Note that circuit heuristics are ignored because the extremes are taken over all device states. That is, the power triple is guaranteed to be a bound on the worst case; but in a circuit, the worst case may not be as poor as the triple owing to the exclusion of some combinations of states and inputs. Equation (3) shows the most important reason for tracking P_{max}: the greatest power produces the largest possible cross talk term in this model. Thus P_{max} is essential for calculating subsequent P_{0max} terms.

As example system components, consider lithium niobate directional couplers and passive 3-dB couplers as logic devices and optical fiber and 3-dB splitters for interconnection. Figure 3 shows a lithium niobate directional coupler configured as a five-terminal optical device.^{6} Of the three device inputs, a, b, and c, only the first two are transmitting inputs; inputs that couple power directly to the outputs. Input c, a detection point in our terminology, functions as a device control. As the logic equation shows, when sufficient power is applied to c, the switch is placed in the bar state; otherwise it is in the cross state. The graph model on the right of the figure makes c into a detection point that is independent of the two-state coupling between the other inputs and outputs. Figure 4 illustrates at a more functional level how the transmission coupling occurs.

3-dB couplers and splitters are modeled as devices with two inputs and two outputs, with 3-dB of loss from each input to each output, no cross talk, a single device state, and no detection points. Lossy interconnections, such as optical fibers, are modeled as devices with one input, one output, a single loss term, no cross talk, a single device state, and no detection points. There is no need to model loss-free interconnections, since they add nothing to the analysis. However, if it is desired to model them for clarity, or if a graphical system model already exists that contains them, they may be modeled exactly like lossy interconnections, but with zero loss and cross talk.

D. Modeling the System

In this section we extend the applicability of the device graph model to complete systems. … The problem of finding critical paths is efficiently solvable with order (n) depth-first search (DFS) algorithms.^{9} The power triples are calculated by scanning the vertices in ascending order and applying Eqs. (2)–(4) to each. When the search algorithm detects that the conditions of Eq. (1) are not met, it is desirable to know the critical path to the detector so that the problem can be corrected. …

3. Discussion

The technique described above is indispensable in designing complex optical systems whose components have significant nonidealities. It has been incorporated into a digital optical computer-assisted design system, HATCH,^{10} where it has proven invaluable in the design of optical counters^{11,12} and an optical delay line memory system.^{13} It is now being used in designing a bit-serial optical computer now under construction in our laboratories. …

As we mentioned above, linear cross talk and loss behaviors are assumed in the device models for computing the power triples. If the transfer functions of the devices are nonlinear, then the three equations should be modified to incorporate the appropriate transfer characteristics.

This research was supported by the National Science Foundation Engineering Research Centers program under grant CDR 8622236 and by the Colorado Advanced Technology Institute.

References

1. J. C. Palais, Fiber Optic Communications, 2nd ed. (Prentice-Hall, Englewood Cliffs, N.J., 1988), pp. 270-271.

2. E. E. Bash and H. A. Carnes, “Digital optical communications systems,”in Fiber Optics, J. Daly, ed. (CRC Press, Boca Raton, Fla., 1987), pp. 153-154.

3. V. P. Heuring, H. F. Jordan, and J. P. Pratt, ”A bit serial architecture for optical computing,” Appl. Opt. 31, 3213-3224 (1992).

4. V. P. Heuring, H. F. Jordan, and J. P. Pratt, ”Bit serial optical computer design,” in Optical Computing 1988, P. Chavel, J. W. Goodman, and G. Robin, eds., Proc. Soc. Photo-Opt. Instrum. Eng. 963, 346-353 (1988).

5. V. P. Heuring and J. P. Pratt, ”Designing continuous dataflow optical computing systems, I. synchronization,” in OSA Annual Meeting, Vol. 15 of 1990 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1990), paper TuUU2.

6. A. F. Benner, H. F. Jordan, and V. P. Heuring, ”Digital optical computer with optically switched directional coupler,” Opt. Eng. 30, 1936-1941 (1991).

7. J. P. Tremblay, P. G. Sorenson, The Theory and Practice of Compiler Writing (McGraw-Hill, New York, 1987), pp. 635-640.

8. C. Berge, Graphs (Elsevier, New York, 1985), pp. 143-152.

9. W. M. Waite and G. Goos, Compiler Construction (Springer-Verlag, New York, 1987), pp. 398-399.

10. J. P. Pratt, ”HATCH instruction manual,” OCS Tech. Rep. 89-31 (Optoelectronic Computing Systems Center, University of Colorado, Boulder, Colo., 1989).

11. V. P. Heuring, ”Systems considerations in the implementation of a bit serial optical computer,” Opt. Eng. 30, 1931-1935 (1991).

12. A. F. Benner, J. Bowman, T. Erkkila, R. J. Feuerstein, V. P. Heuring, H. F. Jordan, J. Sauer, and T. Soukup, ”Digital optical counter using directional coupler switches,” Appl. Opt. 30, 4179-4189 (1991).

13. T. J. Soukup, ”Implementation of a fiber optic delay line memory,” M.S. thesis (University of Colorado, Boulder, Colo., 1991).

FIGURES

Fig. 1. Power fluctuations at a detection point. Fig. 2. General device model. Fig. 3. Modeling a lithium niobate switch. Fig. 4. Modeling device loss and cross talk. Fig. 5. Optical circuit. Fig. 6. Graph model of optical circuit.

TABLES

Table 1. Minimum Signal Powers

Vertex  P_{1min} (dBm)
1  0
2  -3
3  -5
4  -5
5  -8
6  -11
7  -8