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\hspace*{\fill}{\LARGE{\bf References}}\hspace*{\fill}
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\begin{enumerate}

\item Annaratone, Marco. {\it Digital CMOS Circuit Design}.  Kluwer Academic
      Publishers, Boston, 1986.

\item Bahr, Tarak N., Edward J. McMahon. {\it Electrostatic Discharge
      Control}. Hayden Book Company, Inc., New Jersey, 1983.

\item Keller, Jack K.  Protection of MOS Integrated Circuits from
      Destruction by Electrostatic Discharge. In {\it EOS/ESD Symposium
      Proceedings}, pages 73-79.  Reliability Analysis Center, September,
      1980. 

\item Hulett, Terry V.  The Effects of VLSI Scaling on EOS/ESD Failure
      Threshold. In {\it EOS/ESD Symposium Proceedings},
      pages 85-89.  Reliability Analysis Center, September, 1981.

\item Pancholy, R. K.  On Chip Protection of High Density NMOS Devices.
      In {\it EOS/ESD Symposium Proceedings}, pages 90-96.  Reliability
      Analysis Center, September, 1981.

\item Hollis, Ernest E.  {\it Design of VLSI Gate Array ICs}.  Prentice
      Hall, Inc., New Jersey, 1987.

\item Latch-Lock$^{tm}$ Eliminates Latch-Up.  In {\it GAL Handbook},
      pages 6-30 to 6-32.  Lattice Semiconductor Corp., 1988.

\item Walsh, Michael J.  {\it Choosing and Using CMOS}.  Mc-Graw Hill Book
      Company, New York, 1986.

\end{enumerate}
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