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%% \hspace*{\fill}{\LARGE{\bf }}\hspace*{\fill}
%% \par\vspace{0.1 in}

\hspace*{\fill}{\LARGE{\bf Reliability Concerns in CMOS VLSI}}\hspace*{\fill}
\par\vspace{0.1 in}
\hspace*{\fill}{\large{\bf 6.313 Term Paper}}\hspace*{\fill}
\par\vspace{0.1 in}
\hspace*{\fill}{\large{\bf Andr\'e DeHon}}\hspace*{\fill}
\par\vspace{0.2 in}


%% what paper about

During this decade, CMOS has become the dominant circuit technology for
VLSI design.  Owing to its low power consumption and compatibility with a
large range of existing logic families, it has found wide usage in numerous
applications.  Despite its many strong points, it does have a few
undesirable characteristics.  In a few respects CMOS is
substantionally less reliable than other technologies.  CMOS is
particularly susceptible to Electro-Static Discharge (ESD) and Latch-up.
Over the course of CMOS usage, these phenomena have caused problems at a
sufficiently high rate to merit attempts to minimize their effects in
future components.  
\par


%% ESD

%% description and motivation


A component can easily encounter Electro-Static Discharge (ESD) during a
number of incidents 
in its life, but human handling seems to provide the most
pronounced effect.  The ESD resulting from human contact with the electronic
part, will normally generate very high voltages, on the order of kilovolts,
in sequences of short spikes.  These short repeated spikes will drive both
large voltages and large currents into the chip.  If the component is not
capable of handling such spikes, it may be damage during normal
handling.  Failure resulting from ESD is normally indicated by
excess gate leakage and gate short circuits [2,3].  
\par


ESD damage can easily occur without the knowledge of the person handling
the component.  The human body will withstand ESD charges under about 3000
volts without noticing, while many MOS devices will be irreparable damaged
by ESD around 400-500 volts[1].  \par

 MOS circuitry in general has proven to be significantly more
sensitive to ESD than other technologies.  CMOS is particularly susceptible
to ESD due to its thin (approximately 1000 
\AA) gate dielectrics.  Common MOS circuits are composed of thermally 
grown SiO$_2$.  They have a breakdown voltage around 8 $\times$ 10$^6$
volts/cm which means voltages around 80 volts, and possibly less, are
sufficient to destroy the gate insulation and render the chip disfunctional
[3].  This problem is further compounded as
the dimensions involved in fabricating CMOS devices continue to diminish;
the thinner gate structures are naturally more susceptible to ESD [4,5].
\par

Since parts will be handled during their lifetime, there is considerably
motivation to include protection on input pins to make the component less
susceptible to ESD.  Additionally, the increasing complexity of CMOS VLSI
circuits requires an increased pin-count.  This increased pin-count will
naturally increase the probability of ESD failure [4].  Hence, providing ESD
protection on-chip becomes a paramount concern.  The protection scheme,
however must fit within the processing technology already being utilized.
Requiring changes or complications to the processing steps is clearly not
economically feasible.  Additionally, protection methods may be limited by
circuit speed or size requirements.  Thus generally useful protection
schemes must be implementable within the existing processing steps,
remain relatively small, and not cause significant additional delays in the
operation of the chip [3,5]. \par

Numerous protection schemes have been proposed in the literature requiring
varying amounts of time and space.  Only a couple of representative
strategies will be discussed here.  Additionally strategies are described in
[2,3,5]. \par

\begin{figure}
\vspace{1 in}
\caption{Resistor-Diode Protection [3]}
\label{rdproc}
\end{figure}

Probably the most obvious form of protection is the one shown schematically
in Figure \ref{rdproc}.  The resistor serves to limit the input current flow.
The diodes should protect the gate oxide from destructive voltage levels of
either polarity.  Thus the reverse breakdown voltage on the diodes must be
significantly less than the breakdown breakdown voltage of the gate oxide.
This configuration turns out to be more effective when the resistor is
diffused.  The size of this resistor is dependent on the breakdown
impedance of the diodes and is typically one or two kilohms.  In theory
this technique will provide protection up to 4 kilovolts while requiring
minimal area and sacrificing little performance speed[3]. \par

\begin{figure}
\vspace{2 in}
\caption{Thick Oxide Transistor [3]}
\label{to}
\end{figure}

The thick oxide transistor scheme (shown in Figure \ref{to}) was
acknowledge as providing the best ESD protection for high density
fabrication by multiple sources [3,5].  In [5], it performed adequately up
at 3 kilovolts, which was the extent of their testing.  Here a diffused
input resistor is located adjacent another diffusion which is grounded.
This region then gets overlayed with a normal thick field oxide (10,000
\AA).  The oxide is in turn overlaid with a metal plate which is in
turn tied to the input pin.  In this manner, this structure will provide a
low impedance path to ground when the input voltage exceeds 10-30 volts
(depending on the thickness of the oxide), thus protecting the gate oxide
from destructive voltages.  Additionally, this structure
requires a small amount of silicon area and a minimal input resistance.
\par



%%%%% Latch-up

While ESD is a problem, though to a lesser extent, in other logic
technologies, latch-up is peculiar to CMOS.  Latch-up is a phenomenon in
which the output signal becomes ``latched'' in a high state and power and
ground are effectively shorted together.  Once latch-up occurs, this
phenomena will continue until the power supply is removed.  The excessive
supply current generated during latch-up can do permanent damage to the
chip [6,7].\par

\begin{figure}
\vspace{1.5 in}
\caption{Inverter Cross Section Showing Bipolar Transistors [1]}
\label{latch}
\end{figure}

Latch-up arises due to the effects of bipolar transistors which occur
intrinsicly in the fabrication of CMOS components.  Figure \ref{latch}
shows the intrinsic bipolar transistors drawn on a CMOS inverter.
The four transistors form a Semiconductor-Controlled-Rectifier (SCR).
Under the appropriate conditions, the SCR will exhibit positive feedback
and effectively short power to ground [1]. \par


Latch-up can occur ({\it i.e.\ }this positive feedback can be initiated)
under a number of circumstances.  The product of the common emitter gains
on the bipolar transistors must be greater than one for this positive
feedback to function; this will 
always be the case for CMOS devices.  Latch-up can be triggered by an output
overshooting or undershooting its value by more than one diode drop.
Powering up the chip can also trigger latch-up due to unknown bias
conditions.  Reflections from improperly terminated busses can also
be sufficiently non-well-behaved to trigger latch-up.  Similarly, a voltage
drop on the power-line can trigger latch-up [1,6,7].  In any case, once the
bipolar transistors have been allowed to turn ``on'' and allow conduction, the
positive feedback will work to keep them ``on'' and they will continue to
conduct until disconnected from the power supply. \par

Diminishing the trace size of CMOS VLSI will increase the
susceptibility to latch-up.  The decreased dimensions will mean that the
spacing between neighboring regions also shrinks.  This reduced spacing
will increase the probability of latch-up [4]. \par

A number of methods work to minimize or eliminate the likelihood of
latch-up.  Almost all of these add to the cost of fabrication and consume
space in the layout.  Epitaxial silicon is currently used as one of the
major means for eliminating latch-up effects in CMOS circuits.  The doping
and thickness can be chosen such that only high currents\footnote{ Currents
in excess of those in use by CMOS structures} are capable of forward
biasing the bipolar transistors and turning them ``on''.  Using Epitaxial
silicon 
is a relatively expensive technique [8].  Silicon on Insulator (SOI)
fabrication is free from latch-up since the silicon patches are isolated by
non-conductive regions; this prevents the arisal of the SCR path that
caused latch-up [6].  ``Guard rings'' can be used to prevent latch-up.
This works by inserting additionally diffusion regions into the silicon to
isolate the critical regions of the substrate by providing a ``discharge
path'' for electrons.  ``Guard rings'', of course, takes up space on the
die [1].  Carefully grounding the substrate regularly also helps to
minimize the possibility of latch-up by not allowing the cells to float.
This will prevent one or more of the bipolar transistors from ever being
capable of being biased ``on'' [6,7].

 \par



%% conclusion

Both of these phenomena represent serious drawbacks to using CMOS VLSI
components.  These problems will persist and increase as fabrication
technologies continue to be refined and smaller and smaller traces can be
utilized in VLSI design.  It is becoming increasingly important to
minimize or eliminate both ESD and latch-up effects as a part of the design.
As shown, there are a number of existing ways of dealing with these
problems, each with its own tradeoffs in space, efficiency, and cost.  As
current techniques available do not provide complete solutions to either
of these problems that optimize overhead in all three categories, research
will continue to determine better schemes for dealing with these
short-comings.  At present, the CMOS VLSI designer must be aware of these
potential hazards, the extent to which his fabrication process will avoid
them, and the various ways he can minimize their effects in his design in
order to produce a reliable VLSI circuit. \par

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