* Title:  Example Netlist to help with PS1 (always have a title)

* All lines that start with a star (*) are comments
* Start netlists by ".include"-ing other files
* Problem Set 1 model is a 1.2 micron min. length, 
*                          1.8 micron min. width process
* .include /u/6.371/ps1_mosmodels.sp             (use this in the lab)
* .include /mit/6.371/ps1spice/ps1_mosmodels.sp  (use this on athena)

.include /mit/6.371/ps1spice/ps1_mosmodels.sp

* turn on post-processing (needed for dc-sweeps and transient analysis
.options post

* set up operating conditions
.temp 25

* the following are simplistic spice models for your edification:

* N66D SPICE LEVEL1 PARAMETERS
.MODEL NMOSX NMOS (VT0=1.0 KP=3e-5 GAMMA=.5 PHI=0.6)

.MODEL NMOSY NMOS LEVEL=2 LD=0.15U TOX=200E-10
+ NSUB=5.37E15 VTO=0.74 KP=8E-5 GAMMA=0.54
+ PHI=0.6 U0=656 UEXP=0.157 UCRIT=31444
+ DELTA=2.34 VMAX=55261 XJ=0.25U LAMBDA=0.037
+ NFS=1E12 NEFF=1.001 NSS=1E11 TPG=1.0 RSH=70
+ CGDO=4.3E-10 CGSO=4.3E-10 CJ=0.0003 MJ=0.66
+ CJSW=8E-10 MJSW=0.24 PB=0.58


* circuit netlist.  Node 0 is ground.

* Circuit Elements at your disposal:
* ==================================================
* Element             Format
* -----------------   ---------------------------------------------
*       Resistor : R<name> +node -node resistance
*      Capacitor : C<name> +node -node capacitance
* current source : I<name> +node -node type current
* voltage source : V<name> +node -node type voltage
*         mosfet : M<name> drain gate souce bulk model params...
*                        don't forget the scale factor,
*                        (u = microns) when specifying w & l!
* v-ctl'd v-srce : E<name> +out -out +ctl -ctl gain
* ==================================================

* You can also declare variables - symbolic, algebraic 
*     evaluation happens inside of the single quotes.
* ==================================================
* .param minw=1.8u  (this is already in the ps1_mosmodels.sp file)
* .param minl=1.2u  (this is already in the ps1_mosmodels.sp file)

VDD  pwr 0 DC 'vdd'
.param vdd=5.0v

**************************************************
* Implements a NOR gate : 
**************************************************

V1   in1 0 DC 0
V2   in2 0 DC 0

MN1  out in1 0 0      nmos  w=1.8u     l=1.2u
MN2  out in2 0 0      nmos  w='  minw' l='  minl'

MP1  mid in1 pwr pwr  pmos  w='7*minw' l='2*minl' 
MP2  out in2 mid mid  pmos  w='4*minw' l='  minl'  

**************************************************
* Measure the current through an NMOS
* by sweeping V3 (vgs)
**************************************************

V3   in3 0 DC 0

MN3  pwr in3 bot  0  nmos  w=1.8u     l=1.2u
MN4x pwr in3 botx 0  nmosx w=1.8u     l=1.2u
MN4y pwr in3 boty 0  nmosy w=1.8u     l=1.2u

Vcurrent_meter  bot  0 dc 0v
Vmeterx         botx 0 dc 0v
Vmetery         boty 0 dc 0v

* see where circuit stabilizes
.op

*   perform transient analysis (results in xxx.tr0 file)
*   (specify increment/total duration, init. cndtn's, and input waveforms)
* --------------------
* .tran .05ns 3.0ns
* .ic V(mid) = 'vdd'
* V1 in1 0 pwl 0n 0v, 1.0n 0v, 1.1n 'vdd', 2.0n 'vdd', 2.1n 0v

*   perform steady-state analysis (results in xxx.st0 or xxx.sw0 file)
*   (specify source of sweep, start val for sweep, end val, increment val)
* --------------------
* .dc V2 0 'vdd' .1 
.dc V3 0 'vdd' .01

* "hspice example_netlist1.sp"       runs hspice
* "hspice example_netlist1.sp > out" runs hspice, dumps output to file "out"
* if on athena, you must first "add hspice" 
*         also, you must have a file named ".aliases" 
*               in your directory to run hspice (it can be empty)
* always have a .END statement!
.end