#========================================================================= # Command file for floorplanning using cadence encounter #------------------------------------------------------------------------- # $Id: fp.tcl,v 1.1 2007/03/21 17:12:12 jrk Exp $ # #------------------------------------------------------------ # Setup #------------------------------------------------------------ source make_generated_vars.tcl source fp.conf commitConfig # Connect all the power and ground pins # Note that these aren't specified in the verilog globalNetConnect VDD -type pgpin -pin VDD -inst * globalNetConnect VSS -type pgpin -pin VSS -inst * #------------------------------------------------------------ # Create die area #------------------------------------------------------------ # Most of our absolute measurements should be in multiples of either # the standard cell hieght (for Y measurements) or the vertical track # spacing (for X measurements). We use two TCL variables to specify # these values. set vtrack_unit 0.56 set cell_height 5.6 # A die includes the core area where the standard cell rows are # located as well as the margins around the core for pads and the # power ring. We specify the margins using some TCL variables. set margin_left [expr 36 * $vtrack_unit] set margin_bottom [expr 4 * $cell_height] set margin_right [expr 36 * $vtrack_unit] set margin_top [expr 4 * $cell_height] # We have two options when specifying the actual dimensions of the # core. The first specifies the die area as an aspect ratio and a # utilization of the total cell area estimated from the gate-level # netlist. We should use relatively low utilizations since Encounter # needs room to do buffer insertion and local netlist resynthesis. # This approach is useful since you don't need to change anything as # you refine the design - the core area will grow or shrink as # necessary to achieve the desired utilization. We can use the # following commands for this approach. The apsect ratio is the height # divided by the width. set aspect_ratio 1 set density 0.7 floorPlan -r $aspect_ratio $density \ $margin_left $margin_bottom $margin_right $margin_top # The second way to specify the core dimensions is to use absolute # measurements in microns. This gives the designer much more control # and enables much more precise module floorplanning, but these # measurements must be adjusted whenever we make a significant change # to the design. We can use the following commands for this approach. # # set die_width [expr 1300 * $vtrack_unit] # set die_height [expr 130 * $cell_height] # set core_width [expr $die_width - $margin_left - $margin_right] # set core_height [expr $die_height - $margin_bottom - $margin_top] # # floorPlan -d $die_width $die_height \ # $margin_left $margin_bottom $margin_right $margin_top # This command generates the (empty) standard cell rows generateTracks #------------------------------------------------------------ # Module Floorplanning #------------------------------------------------------------ # The floorplanning commands allow us to specify a position for # synthesized modules and RAM macro blocks. We can use various # TCL variables to help make the floorplanning more flexible. # To specify a position for a module we can use the following # command where (llx,lly) indicates the lower lefthand coordinate # and (urx,ury) indicates the upper righthand coordinate. # # setObjFPlanBOx Module # # To specify a position for a RAM macro block we can use the # following command where (llx,lly) indicates the lower lefthand # coordinate and orientation indicates whether to flip or # rotate the block. See the Encounter documenation for more info. # # relativeFPlan --place TR 0 0 # #------------------------------------------------------------ # Power Planning #------------------------------------------------------------ # M2/M5 ring addRing \ -layer_left M2 \ -layer_right M2 \ -layer_bottom M5 \ -layer_top M5 \ \ -spacing_left 0.6 \ -spacing_right 0.6 \ -spacing_bottom 0.6 \ -spacing_top 0.6 \ \ -width_left 9.0 \ -width_right 9.0 \ -width_bottom 9.0 \ -width_top 9.0 \ \ -offset_left 0.66 \ -offset_bottom 0.66 \ -offset_right 0.66 \ -offset_top 0.66 \ \ -threshold 0.66 \ -jog_distance 0.66 \ -stacked_via_bottom_layer M1 \ -stacked_via_top_layer TOP_M \ -center 1 \ -around core \ -nets { VDD VSS } # encounter gives a warning without this option setAddStripeOption -remove_floating_stripe_over_block 0 # M6 vertical stripes addStripe \ -layer TOP_M \ -direction vertical \ -width 1.4 \ -spacing 15.4 \ -set_to_set_distance 33.6 \ \ -xleft_offset 0 \ -xright_offset 0 \ \ -stacked_via_bottom_layer M1 \ -stacked_via_top_layer TOP_M \ -block_ring_bottom_layer_limit TOP_M \ -block_ring_top_layer_limit M1 \ -padcore_ring_bottom_layer_limit TOP_M \ -padcore_ring_top_layer_limit M1 \ \ -snap_wire_center_to_grid Grid \ -allow_jog_padcore_ring 0 \ -allow_jog_block_ring 0 \ -nets { VDD VSS } # M5 horizontal stripes addStripe \ -layer M5 \ -direction horizontal \ -width 1.4 \ -spacing 4.2 \ -set_to_set_distance 11.2 \ \ -ybottom_offset -0.7 \ -ytop_offset -0.7 \ \ -stacked_via_bottom_layer M1 \ -stacked_via_top_layer TOP_M \ -block_ring_bottom_layer_limit TOP_M \ -block_ring_top_layer_limit M1 \ -padcore_ring_bottom_layer_limit TOP_M \ -padcore_ring_top_layer_limit M1 \ \ -allow_jog_padcore_ring 0 \ -allow_jog_block_ring 0 \ -nets { VDD VSS } #------------------------------------------------------------ # Save floorplan #------------------------------------------------------------ saveFPlan floorplan.fp saveDesign floorplan exit