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6.004 Problem Set \psnum \\ Juliet Bourne -- #1} \\ \vspace{-.1in} 
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\begin{document}

\mytitle{10/24/90}

\prob{1: {\em Data Path Problems}}

\subprob{A} The fastest path from a clocked register to another clocked
device or register is through the Control ROMs. The delay through these
is approximately 250 ns. Since the DRSEL and LDSEL are clocked, there
shouldn't be any random writes into the SRAM when control signals are in
transition. 

\subprob{B}

\vspace*{3in}

\subprob{C} Only one drive signal can be selected at a time because the
DRSEL decoder chip can only select one of its outputs given its inputs.
EPROM programming can't make the DRSEL decoder select more than one of
its outputs and thus drive more than one device at a time.

\subprob{D} Yes, the drive and load signals could be generated directly
by the EPROM, using a total of 9 more outputs. This would eliminate the
extra delay time incurred by the clocked decoders. However, without the
decoders, the risk of driving more than one device at a time (due to an
EPROM programming error) is introduced.

\subprob{E} No, since the ability to latch (save) the condition bits is
lost if they are fed directly into the EPROM.

\subprob{F} With $x$ and $y$ as the A and B inputs, the '181 can be used
as a comparator. If the subtract function is selected (by setting the
selector inputs to 0110) and the carry condition bit is high ($C_n =
1$), the A=B pin (pin 14) of the '181 will be high if $A = B$ or, in
this case, $x = y$.

\subprob{G} No. Looking at the timing diagram in the spec for the 4-bit
counters used in the Microcode ROM, it appears that even if the ADR+ is
asserted, the original data is held until the next clock edge, at which
point it is incremented. Therefore, the data driven onto the bus does
not depend on the value of ADR+.

\mynewpage

\subprob{H} No. If two data lines on the SRAM are switched, operation
will not affected since they will get unswitched when the data are
retrieved (i.e. the SRAM connection to the bus is bidirectional).
However, if two data lines of the Microcode EPROM are switched,
operation will be affected because the EPROM outputs are defined to have
a certain order which has significance. Changing the data order (like
switching two data lines) changes the meaning.

\subprob{I} The order of sending the high- and low-order bits to the
DRAM is arbitrary, as long as it is consistent. Therefore, consistently
sending the low-order first will be indistinguishable from consistently
send the high-order first, as far as storing and retrieving data, even
though the data will be stored in a different DRAM location depending on
which is sent first.

\subprob{J} Until the capacitor wired between ground and $V_{cc}$ is
fully charged, $\overline{RESET}$ is low. Once the capacitor is fully
charged, $D_0$ is at a valid ``1'' value, at which point (at the next
clock edge), $\overline{RESET}$ goes high. While it is low, ADR, OPCODE,
and PHASE are being cleared at each clock edge. THe flip-flop assures
that $\overline{RESET}$ will always be at a valid logic level, even when
the capacitor is charging.

\subprob{K} While $\overline{RESET}$ is low, the Microcode ROM is driven
onto the bus. However, when $\overline{RESET}$ is low, all of the
$\overline{CLR}$ pins of the counters in the Microcode ROM are also low.
Thus, the address in the Microcode ROM is the first address (all zeros).
Whatever opcode is stored at that Microcode ROM address is driven onto
the bus and subsequently loaded into the OPCODE register.

\subprob{L}

\vspace*{2.25in}

\subprob{M} Looking at the default line (which is the only line which
refers to byte 0) in the BASIC.PROM code, the high byte is 11010000.
This is loaded into the OP register as the initial opcode.

\subprob{N} Since the initial opcode is 11010000, states 11010000~0000~*
through 11010000~0110~* are executed, at which point 11010000~0111~* is
executed, which changes the opcode to 0.

\subprob{O} After a few seconds (or lots of clock edges), and assuming
no buttons are pressed, the FSM specified by the EPROM will be looping
in state 5, waiting for a button to be pressed. Therefore, the OP
register will contain 00000101.

\mynewpage

\prob{2: {\em Abstraction and Its Tradeoffs}}

\subprob{A} While this proposal offers the ability to change the program
easily, it takes too much time and space to be worth this flexibility
and abstraction. Not only do you have to have your program in ROM, but
you also need the interpreter to interprete it each time it is used.
Also, you need to have the LISP interpreter program in ROM. For
something that's not going to be changed for 15 years, it is too slow
and cumbersome.

\subprob{B} This proposal seems more sensible, since all that is really
needed is a compiled program. It takes less ROM than the previous
proposal (since only the compiled program needs to be on ROM) and it is
also faster (since the program isn't interpreted each time). However, if
for some reason the program needs to be changed, you'll need to replace
the compiled program ROM with a ROM of the new compiled program. But
we're assuming that the program won't have to be changed for a while.

\subprob{C} This is certainly the fastest performance-wise of the
proposals, since the program is converted directly into logic and put on
a chip. There is no need to interprete code or even run compiled code.
However, there is no flexibility since the chip can only do one thing.
In our case, this might be the best solution, provided we don't make any
programming errors. If we do, we have to remanufacture all of the chips.

\prob{3: {\em Architecture and Nano-Code}}

\subprob{A} The MAR is also used to hold the location of an SRAM
location, which allows the manipulation of the data in the SRAM. For
example. movei(x,y), which puts the contents of location x into the
contents of location y, needs to be able to put the location of the
contents of a SRAM location into the MAR. Eliminating the MAR would
eliminate the ability to modify the SRAM data. Also, sometimes arbitrary
(i.e. not determined by the $\mu$ROM) addresses are used to access the
SRAM.

\subprob{B} This requires the use of the free (not connected) EPROM
output bit.

\mynewpage

\subprob{C} The modified code looks like this:

\begin{verbatim}
|                           O
| l (adrlo, adrhi, where)   E
00001111 0000 * = 1 1111 11 0 11 100 010 | A<-SRAM<uROM>; ADR+
00001111 0001 * = 0 1111 11 0 11 010 110 | DRAM<-A
00001111 0010 * = 1 1111 11 0 11 100 110 | DRAM<-SRAM<uROM>; ADR+
00001111 0011 * = 1 1111 11 0 11 110 100 | SRAM<uROM><-DRAM; ADR+
00001111 0100 * = 1 1111 11 1 11 001 000 | OPCODE<-uROM; ADR+

| s (value, adrlo, adrhi)
00010000 0000 * = 1 1111 11 0 11 100 011 | B<-SRAM<uROM>; ADR+
00010000 0001 * = 1 1111 11 0 11 100 010 | A<-SRAM<uROM>; ADR+
00010000 0010 * = 0 1111 11 0 11 010 110 | DRAM<-A
00010000 0011 * = 1 1111 11 0 11 100 110 | DRAM<-SRAM>uROM>; ADR+
00010000 0100 * = 0 1111 11 1 11 011 110 | DRAM<-B
00010000 0101 * = 1 1111 11 1 11 001 000 | OPCODE<-uROM; ADR+
\end{verbatim}

\noindent The first goes from 8 cycles to 5; the second goes from 9
cycles to 6.

\subprob{D} Examples: add, move, cadd, movei, cmp. All take 2 cycles to
get location into the MAR and get data in that SRAM location into a
register. 

\subprob{E} The hacked MAYBE will probably be no more than one-third
faster overall, since not all code can take advantage of this hack. Even
the code that can take advantage doesn't go much faster than one-third
faster. 

\prob{4: {\em Quiz One Revisited}}

\mynewpage

\end{document}
