\File{crc.c},{12:11},{Feb  6 1997}
\L{\LB{\K{\#include} \S{}\"squid.h\"\SE{}}}
\L{\LB{}}
\L{\LB{\C{}\/* As its name implies (Cyclic Redundancy Check) a crc adds}}
\L{\LB{redundancywhereas the topic of this group is to remove it. But since}}
\L{\LB{thisquestion comes up often, here is some code (by Rob Warnock}}
\L{\LB{\<rpw3@sgi.com\>).The following C code does CRC\-32 in}}
\L{\LB{BigEndian\/BigEndian byte\/bit order.That is, the data is sent most}}
\L{\LB{significant byte first, and each of the bitswithin a byte is sent most}}
\L{\LB{significant bit first, as in FDDI. You will needto twiddle with it to}}
\L{\LB{do Ethernet CRC, i.e., BigEndian\/LittleEndian byte\/bitorder. [Left as}}
\L{\LB{an exercise for the reader.]The CRCs this code generates agree with}}
\L{\LB{the vendor\-supplied Verilog modelsof several of the popular FDDI \"MAC\"}}
\L{\LB{chips. *\/\CE{}}}
\L{\LB{}}
\L{\LB{\K{long} crc32\_table[256];}}
\L{\LB{}}
\L{\LB{\K{long} crc32(\K{char} *buf, \K{int} len) \{ }}
\L{\LB{  \K{char} *p; }}
\L{\LB{  \K{long} crc; }}
\L{\LB{  \K{if} (!crc32\_table[1]) \C{}\/* if not already done, *\/\CE{} }}
\L{\LB{    init\_crc32(); \C{}\/* build table *\/\CE{} }}
\L{\LB{}}
\L{\LB{  crc = 0xffffffff; \C{}\/* preload shift register, per CRC\-32 spec *\/\CE{}}}
\L{\LB{}}
\L{\LB{  \K{for} (p = buf; len \> 0; ++p, \-\-len) }}
\L{\LB{    crc = (crc \<\< 8) \^ crc32\_table[(crc \>\> 24) \^ *p]; }}
\L{\LB{  \K{return} \~crc; \C{}\/* transmit complement, per CRC\-32 spec *\/\CE{}\}}}
\L{\LB{}}
\L{\LB{\C{}\/* Build auxiliary table for parallel byte\-at\-a\-time CRC\-32. *\/\CE{}}}
\L{\LB{}}
\L{\LB{\K{\#define} CRC32\_POLY 0x04c11db7   \C{}\/* AUTODIN II, Ethernet, \& FDDI *\/\CE{}}}
\L{\LB{}}
\L{\LB{\K{void} init\_crc32() \{ }}
\L{\LB{  \K{int} i, j; }}
\L{\LB{  \K{long} c;}}
\L{\LB{  \K{for} (i = 0; i \< 256; ++i) \{ }}
\L{\LB{    \K{for} (c = i \<\< 24, j = 8; j \> 0; \-\-j) }}
\L{\LB{      c = c \& 0x80000000 ? (c \<\< 1) \^ CRC32\_POLY : (c \<\< 1); }}
\L{\LB{    crc32\_table[i] = c;}}
\L{\LB{  \}}}
\L{\LB{\}}}
