A second design and protoboard implementation was done by Chris
Turner.[#ctpan#
Further development of a modified version of Turner's design was
carried out by the author. Both OOK and differential binary phase
shift keying (BPSK) were used for encoding, with limited success.
This design was built on PCBs, however the design ultimately failed
due to noise rejection problems. Attempts to resolve this problem
through use of an analog gain control (AGC) were made, but the AGC was
was also abandoned in favor of the final design.
A final hardware design by Matthew Reynolds, employing a
phase-locked-loop (PLL) for analog demodulation was implemented using
a frequency shift keying (FSK) encoding scheme. This design, as of
May, 1997, has shown the most promise, and has proven reliable for
speeds up to 9600 baud in certain geometries.