I. make and Makefiles
	A. make is a utility to track *dependencies* in a system of
	files, and to automate compilations
		1. examples of dependencies - C program
			- objs depend on source for that object
			- objs depend on headers
			- binary depends on objs
			- libs depend on objs
		2. Uses files called Makefiles as configuration
		3. Heirarchical dependencies determined by mod time -
		if any dependency is newer than target, remake target
		with command
	B. Makefiles - basic
		1. naming - GNUmakefile, makefile, Makefile in that order
			- latter is recommended - fairly standard,
			appears at top of dir
			- use GNUmakefile only for gmake-specific
			makefiles.
		2. explicit rules (basic)
			TARGET... : DEPENDENCIES... [; COMMAND]
				COMMAND
				...
				...
		3. tabs.  tabs tabs tabs tabs tabs.
		4. \newline syntax for breaking up lines
		5. phony targets i.e. clean, all - no dependencies
			- executed every time target is goal
			- (gmake:) declare as phony to avoid name conflicts
			with special target keyword .PHONY:
			.PHONY : clean
			clean :
				rm $(OBJS)
		6. default goal is first rule that does not start with
			a period
		7. Comments - `#' starts
	C. Commands
		1. each line is run in a different shell, if you want
		to cause a command to affect the next, use ; in the
		command so that make interprets it as a single command:
			foo:
				cd foodir ; doit
		or
			foo:
				cd foodir ; \
				doit
		2. To ignore errors from a command
			foo:
				-rm -rf *
	D. Variables
		1. Naming
			- case sensitive
			- any characters except trailing whitespace,
			`:', `#', or `='
			- should avoid all but alphanumerics and
				underscore
		2. Setting
			VARNAME = VARVALUE
				- note: trailing spaces not truncated
			make VARNAME=value
			inherits most environment variables except $SHELL
		3. referencing
			$(VARNAME)
		4. Standard variables for program Makefiles
			- $(OBJS)
			- $(SHELL)
			- $(MAKE)
			- $(CC)
			- $(CFLAGS)
			- $(INCLUDE)
			- $(LDFLAGS)
		5. Automatic variables - make sets these in special
		cases for substitutions and other purposes.  More later
	E. Multiple targets and rules
		1. Multiple targets equivalent to list of rules for
		each target
			foo bar baz: blah
				doit
			and
			foo: blah
				doit
			bar: blah
				doit
			baz: blah
				doit
			are equivalent
		2. Multiple rules for a single target are acceptable -
		make will check all files that depend on a given
		updated file.  Useful for adding dependencies.
			FILES = foo bar baz
			foo: bar
				doit
			bar baz: blah
				dothat
			$(FILES): gag
			# no commands allowed here
		will add dependency on gag to $(FILES)
		3. Multiple commands are *NOT* acceptable - there can
		be only one set of commands for a given target; all
		other rules using the target must not have commands.
			- exception - double-colon rules' commands are
			independent.
	F. Implicit rules
		1. default rules, either internal to make or
		user-defined, which set dependencies based on classes
		of filename.
		2. Pattern rules -
		TARGET-PATTERN: DEP-PATTERN
			COMMANDS
		eg
		%.o: %.c
			$(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@
		3. can be chained, i.e. .y -> .c -> .o - the .c file
		does not exist, but make considers it for dependency
		purposes.  Make deletes the temp files when it's done.
		4. a number of useful implicit rules are predefined
		e.g. .c -> .o as above.
	G. Static pattern rules
		1. used to take analagous dependencies and execute
		commands constructed from names
			TARGETS ...: TARGET-PATTERN: DEP-PATTERNS ...
				COMMANDS
				...
		ex:	OBJS = foo.o bar.o
			$(OBJS): %.o: %.c
				$(CC) -c $(CFLAGS) $< -o $@
		2. TARGET-PATTERN is used to construct names to place
		into DEP-PATTERNS
			a. `%' - is the variable which matches the
			stem of the targets, which is then substituted
			into the `%' in the dependency pattern to make
			the actual command.
			b. `$<' is the automatic variable which holds
			the name of the dependency.
			c. `$@' is the automatic variable which holds
			the name of the target.
			d. `$*' is an automatic variable which will
			expand to the stem (what matched the %)
		3. Different from implicit rules in that it only
		applies to the list of targets you specify.
	H. Including other Makefiles
		1. directive: 
			include FILENAMES
		2. FILENAMES can include shell globs and make vars
		3. useful for including global rules and vars
	I. makedepend
		1. parses .c files for other files they include, then
		writes them in the form of a dependency rule in a 
		makefile i.e.
		if foo.c #includes foo.h, bar.h, and quux.c, it will
		add a rule of the form:
			foo.c: foo.h bar.h quux.c
		to the makefile
		2. old way to use:
			dep:
				makedepend $(CPPFLAGS) *.c
		will remake all dependencies when make dep is called,
		and write them to the end of the current makefile
		3. gmake way to use:
include *.d
%.d: %.c
	$(SHELL) -ec '$(CC) -M $(CPPFLAGS) $< | sed '\''s/$*.o/& $@/g'\'' > $@'
		(gmake considers all included makefiles as targets,
		and, if any needed to be recreated, reruns itself with
		the updated makefiles.)
	J. Recursion
		1. Useful if you want to have subsections of code in
		subdirs with their own makefiles
		2. Basic syntax:
			subsystem:
				cd subdir; $(MAKE)
		3. Always use $(MAKE) rather than passing `make' -
		inherits path to make and command line arguments
		4. exporting variables to sub-makes normally only
		happens for variables defined in the environment or
		the command line.
			- export VARIABLE
			- unexport VARIABLE
	L. Archives (libraries)
		1. a specific member of an archive can be target or
		dependency:
			ARCHIVE(MEMBERS)
		eg
			libfoo.a(foo.o bar.o): foo.o bar.o
				ar -r libfoo.a foo.o bar.o

		
