-------------------------------------------------------------------------------
IO Address Space

The MACE chips take up 256 bytes of IO space starting at 0x1000 (EISA
IO Slot 1).  Add the base address to the MACE address to get the
address to do an IN or OUT to.

MACE 0	= 1000 - 10FF
MACE 1	= 1100 - 11FF

-------------------------------------------------------------------------------
Interrupts

Each MACE has a single interrupt, which will occur when its RDTREQ first
	becomes asserted.

MACE 0	= IRQ 5
MACE 1	= IRQ 6

-------------------------------------------------------------------------------
MACE Addresses

Bits are assigned as follows:
0	= unused, should always be 0
1 - 5	= MACE ADD1-ADD4 pins
6	= EOF boolean used to indicate the final (byte or word) write of
		a transmit (1 = normal, 0 = final byte/word)
7	= which MACE (0 or 1)
8-19	= MACE selector (0x1000)

All MACE registers are 8-bit except for the FIFOs.  On non-FIFO
registers, 8 and 16 bit accesses can be done interchangably, but the
low byte should be used and the high byte ignored.  Important MACE
register addresses (double the actual MACE ADD values, due to the
dropping of bit 0):

Mnemonic	Address(hex)	Description
RCVFIFO		0		Receive FIFO.  8 or 16 bit R/W access.
XMTFIFO		2		Transmit FIFO.  8 or 16 bit R/W access.

XMTFS		6		Transmit Frame Status.  R only.  Read once
					after a frame transmits (after XMTSV
					is set in PR)

RCVFS		C		Receive Frame Status.  R only.  Read four
					times after a frame is received by
					the host.

PR		14		Poll Register.  Non-zero bits are as follows:
					7	XMTSV indicates you should
							read XMTFS
					6	TDTREQ indicates space in
							Xmit FIFO
					5	RDTREQ indicates data in
							Recv FIFO

FIFOCC		18		FIFO Configuration Control.  Contains controls
					for FIFO watermarks and burst setting.
					Default watermarks are 8 bytes for
					transmit and 64 bytes for receive.

MACCC		1A		MAC Configuration Control.

PLSCC		1C		PLS Configuration.  Controls modes.

IAC		24		Internal Address Configuration.  Controls
					access to LADRF and PADR.  Set a
					bit here to request to change, and
					test bit 0 to get the acknowledgement.

PADR		2A		Physical Address.  Write 6 times after
					frobbing IAC to set.


-------------------------------------------------------------------------------
Initialization Sequence (should be carried out once for each MACE)

Write 0x2 to PLSCC(0x1C) to select 10baseT
Write 0x84 to IAC(0x24) to change physical address.
Repeatedly read IAC(0x24) until bit 7 is a 0 to be sure the MACE is ready.
Write PADR(0x2A) 6 times with the 48-bit physical address.
Write 0x3 to MACCC(0x1A) to enable transmit and receive.

-------------------------------------------------------------------------------
Receiving

Interrupt handler pseudocode:
	Wait for RDTREQ to assert (i.e. for the ISR to be called)
	allow other interrupts to interrupt this one (since it's long)
rbegin:	if (this is the beginning of a new packet)
		do 32 word reads from RCVFIFO(0x0) into a new current buffer
		decode packet size and header
		if(we don't need this packet)
			point current buffer at /dev/null
		do end of receive stuff
	else if (this is a packet with less than 64 bytes left)
		do as many reads as necessary (the last should be a byte
			read for odd bytes, or can be a word read but the
			top byte will be garbage)
		do end of receive stuff
	else
		do 32 word reads from RCVFIFO into current buffer
	read PR(0x14) and mask out RDTREQ
	if(RDTREQ)
		loop to rbegin
	return from interrupt

End of receive stuff:
	do 4 reads of RCVFS(0xC)
	if(we need this packet)
		send packet to forwarding code
	make a new queue slot for the next receive

-------------------------------------------------------------------------------
Transmitting

Polling loop (need to be done once for each MACE):
	Read PR(0x14) and mask out XMTSV and TDTREQ
	if(XMTSV)
		do a read from XMTFS
	if(TDTREQ)
		if(there's nothing in the queue)
			do nothing
		if(the current packet has more than 8 bytes left)
			do 4 word writes to XMTFIFO(0x2)
		else
			do all but the last write as word writes
			do the last write as a word or byte, with the EOF
				bit asserted
			increment the transmit queue

-------------------------------------------------------------------------------
