config_hardware() {
        Write 0x2 to PLSCC(0x1C) to select 10baseT
        Write 0x84 to IAC(0x24) to change physical address.
        Repeatedly read IAC(0x24) until bit 7 is a 0 to be sure the MACE is ready.
        Write PADR(0x2A) 6 times with the 48-bit physical address.
        Write 0x3 to MACCC(0x1A) to enable transmit and receive.
}

read_eth() {
rbegin: if (this is the beginning of a new packet)
                do 32 word reads from RCVFIFO(0x0) into a new current buffer
                decode packet size and header
                if(we don't need this packet)
                        point current buffer at /dev/null
                do end of receive stuff
        else if (this is a packet with less than 64 bytes left)
                do as many reads as necessary (the last should be a byte
                        read for odd bytes, or can be a word read but the
                        top byte will be garbage)
                do end of receive stuff
        else
                do 32 word reads from RCVFIFO into current buffer
        read PR(0x14) and mask out RDTREQ
        if(RDTREQ)
                loop to rbegin
        return from interrupt

End of receive stuff:
        do 4 reads of RCVFS(0xC)
        if(we need this packet)
                send packet to forwarding code
        make a new queue slot for the next receive
}

send_packet() {
Polling loop (need to be done once for each MACE):
        Read PR(0x14) and mask out XMTSV and TDTREQ
        if(XMTSV)
                do a read from XMTFS
        if(TDTREQ)
                if(the current packet has more than 8 bytes left)
                        do 4 word writes to XMTFIFO(0x2)
                else
                        do all but the last write as word writes
                        do the last write as a word or byte, with the EOF
                                bit asserted
}
