User's Guide to the 6.111 C Simulator

Author:

Mark W. Eichin

• Introduction
• How to create a simulation
• Building Submodules
• Simulator data files
• Standard Circuit Element Library

Introduction

How to create a simulation

\begin{figure} \begin{frepcode}{../src/mysim.c}\end{frepcode} \caption{mysim.c --- Boilerplate Simulation File} \end{figure}

You should leave the template file unchanged above and below the lines

Simple circuit.

Let's begin with the simple circuit pictured in this figure. First, trace out each run of wire that is electrically connected. Insert a declaration

• they have to begin with a letter, though they may contain numbers (they obey the same rules as C identifiers.)
• any wires that are external inputs or outputs should be labelled the way you want to see them in the input or output files (see Chapter "Simulator data files" for more details.)

Now that all the wires have been declared, they should be connected to the circuit. Start by looking up function names for the simulations of each of the circuit elements. If any of them are not in the predefined table, you will have to break them down into existing elements, or define a new C procedure to simulate them (see chapter "Building Submodules".)

Then, using the function for each element, create a connection, as follows:

• Make sure that you have not left out the semicolons after the commands used. Semicolons separate commands, newlines are ignored.
• Make sure that you have spelled and capitalized the commands correctly. C is both case and spelling sensitive.
• Make sure that you gave the right arguments to the function (check the table again if you are not sure.)
• Make sure that the wire name you used was created in advance (with the MAKEWIRE command). Also be sure that it is spelled correctly.

Complete user code for simulation

Once you have successfully compiled the simulation (that is, once make runs through and prints only the compilation commands, and no error messages or ``Stopped'' messages) you can run it. Typing

• make_binop(op, c, a, b) creates a node of circuit element op that has arguments c, a, and b, but only depends on a and b. This is used for and, or, xor, delay, and tristate.
• make_unop(op, b, a) creates a node of circuit element op that has arguments b and a, but only needs to run when a changes. This is used for the not primitive.
• make_tracer(op, line) creates a node which runs the procedure op when line changes state. This is used by the output primitive, and as an obvious way to implement LED's or other indicator devices.
• make_anop(opcount, oparguments, argcount, arguments) is the generic construction macro with arguments of
  • opcount: the number of arguments in the oparguments list. The valid range is currently 0 through 9.
  • oparguments: the list of the arguments that should cause the procedure to run.
  • argcount: the number of arguments in the real arguments list. The valid range is currently 0 through 10.
  • arguments: the real arguments, which are passed as a generic list to the procedure which is the first element in the list. By design, the first element of this list must be the procedure to call to process the circuit changes; by convention, the next elements are the output lines, followed by the input (driving) lines.

• STATE to declare variables that hold the current values of wires.
• Wire for variables which actually hold wires.

• SAVEOUTWIRE(argumentlist, wirename) saves the current wire in the list of arguments into the wire called wirename (which must be declared above.) It then advances the argumentlist to the next argument.
• READNEXTSTATE(argumentlist, statename) saves the state of the current wire in the list of arguments into the state variable called statename (which must be declared above.) It also advances the argumentlist to the next argument.
• READNEXTSTATETIME(argumentlist, statename, timeval) saves the state of the current wire in the list of arguments into the state variable called statename (which must be declared above) and the time at which the change will occur into the variable called timeval. It also advances the argumentlist to the next argument.
• SETOUTPUT(wirename, statename, timeval) sets the write named wirename to the value of the state variable called statename at the value of the time expression timeval. timeval is often in the form globaltime+MY_DELAY.
• READNEXTTIME(argumentlist, timevariable) saves a time value from the argument list and stores it into timevariable. It advances the argumentlist to the next argument. (This is used in the DELAY primitive, and is included as an example of other argument choices.)

The input file format consists of lines which are either assignments or wait statements. An assignment consists of a wire name followed by a space and then a value, which is one of

Tag

Meaning

1

Logic High

0

Logic Low

U

Undefined

X

Tristate

C

Contention

Sample input waveform.

Sample input wave file

Output simulator waveform

Output of simulator run.

These files can be read in by the C simulator, the Lisp Simulator, or the Digital Oscilloscope. The Oscilloscope can also build these input files.

Appendix: Standard Circuit Element Library

Table from page 5-22, TI databook, for 7474:
|------------------------------------------------|
|              INPUTS            |    OUTPUTS    |
|--------------------------------+---------------|
| preset | clear | clock |   D   |   Q   |  Q'   |
|--------+-------+-------+-------+-------+-------|
|   L    |   H   |   X   |   X   |   H   |  L    |
|   H    |   L   |   X   |   X   |   L   |  H    |
|   L    |   L   |   X   |   X   |   H*  |  H*   |
|   H    |   H   |   ^   |   H   |   H   |  L    |
|   H    |   H   |   ^   |   L   |   L   |  H    |
|   H    |   H   |   L   |   X   |   Q0  |  Q'0  |
|--------+-------+-------+-------+-------+-------|
|                                   *unstable.   |
|------------------------------------------------|