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| United States Patent |
5,939,924
|
|
Visocchi
, et al.
|
August 17, 1999
|
Integrating circuit having high time constant, low bandwidth feedback
loop arrangements
Abstract
This invention relates to an integrating circuit and finds application in
high time constant low bandwidth feedback loop arrangements, e.g. in phase
locked loop circuits. A well-known form of integrator is the Miller
integrator, as used in Phase Lock Loop circuits (PLL) which are frequently
used in communication systems, and are employed, for example, in clock
extraction circuits in optical fiber receivers. With the advent of Passive
Optical Networks (PON) becoming a means of providing fiber to the home
very accurate timing information is required, to allow the outstation
optical transmitter to send data within its designated time slot. The
timing source at the base station needs to have a narrow jitter bandwidth
of no more than, typically, 0.1 Hz, which cannot be realized with known
phase lock loop circuits. The present invention seeks to provide an
improved integrator which allows the fabrication of such timing circuits
using standard components.
| Inventors:
|
Visocchi; Pasqualino Michele (Middlesex, GB);
Butson; Richard (Essex, GB)
|
| Assignee:
|
Northern Telecom Limited (Montreal, CA)
|
| Appl. No.:
|
729099 |
| Filed:
|
October 11, 1996 |
Foreign Application Priority Data
| Current U.S. Class: |
327/336; 327/156; 327/345; 327/552 |
| Intern'l Class: |
H03K 004/08 |
| Field of Search: |
327/336,341,344,345,362,363,590,552,558,156,147
331/17
|
References Cited [Referenced By]
U.S. Patent Documents
| 4064406 | Dec., 1977 | Tiemeijer | 327/336.
|
| 5376892 | Dec., 1994 | Gata | 327/336.
|
| Foreign Patent Documents |
| 139466 | Jan., 1980 | NL | 327/345.
|
Other References
Huelsman, "Basic Circuit Theory", 3rd edition, pp. 596-599, 1972.
|
Primary Examiner: Callahan; Timothy P.
Assistant Examiner: Shin; Eunja
Attorney, Agent or Firm: Lee, Mann, Smith, McWilliams, Sweeney & Ohlson
Claims
We claim:
1. An integrating circuit including a first and a second operational
amplifier, each said operational amplifier having a non-inverting input,
an inverting input and an output, the output of the first amplifier being
coupled via an attenuating T network to the inverting input of the second
amplifier, the first amplifier having a direct connection between its
output and its inverting input, the second amplifier being configured as a
Miller integrator, with the feedback acting on the inverting input of the
second amplifier, the output of the second amplifier being connected to
the non-inverting input of the first amplifier, wherein the integrating
circuit receives an input signal through an input terminal connected to
the non-inverting input of the first amplifier.
2. An integrating circuit according to claim 1 wherein, the attenuating T
network comprises first and third resistors R1, R3 and the inverting input
of the second amplifier is coupled via first and second resistors R1, R2
to ground.
3. An integrating circuit according to claim 1 wherein the non-inverting
input of the second amplifier is connected to ground.
4. An integrating circuit according to claim 1 having a plurality of signal
input terminals connected to the non-inverting input of the first
amplifier via respective input resistances.
5. An integrating circuit according to claim 1 wherein the feedback of the
Miller integrator arrangement comprises a resistance Rz.
6. An integrating circuit including first and second operational
amplifiers, each said operational amplifier having a non-inverting input,
an inverting input, and an output,
the output of the first amplifier A.sub.1 being coupled via an attenuating
network to the inverting input of the second amplifier A.sub.2 and via an
attenuating network to ground,
the first amplifier having a feedback connection between its output and its
inverting input,
the second amplifier being configured as a Miller integrator, with the
feedback acting on the inverting input of the second amplifier,
the output of the second amplifier being connected to the non-inverting
input of the first amplifier,
wherein the integrating circuit has two signal inputs being at the
non-inverting input of the first amplifier,
wherein a first signal input terminal is connected via a first input
resistance to the non-inverting input of the first amplifier and a second
input terminal is connected via a second input resistance to the
non-inverting input of the first amplifier.
7. An integrating circuit according to claim 6 wherein the feedback of the
Miller integrator arrangement comprises a resistance Rz.
8. An integrating circuit including first and second operational
amplifiers,
an output of the first amplifier A.sub.1 being coupled via an attenuating
network to an inverting input of the second amplifier A.sub.2 and via an
attenuating network to ground,
the first amplifier having an inverting input which is connected to its
output,
the second amplifier being configured as a Miller integrator, with the
feedback acting on the inverting input of the second amplifier,
an output of the second amplifier being connected to the non-inverting
input of the first amplifier,
signal input(s) IP.sub.1, IP.sub.2 to the integrating circuit being at a
non-inverting input of the first amplifier,
wherein the attenuating network from the first amplifier A.sub.1 to an
inverting input of the second amplifier A2 comprises first and third
resistors R1, R3 and a resistor R4 which lies intermediate the output of
the first amplifier and the first and third resistors and the inverting
input of the second amplifier is coupled via first and second resistors
R1, R2 to ground; and wherein the feedback of the Miller integrator
comprises a first capacitor Cf which is connected to both the inverting
input of the second amplifier and a further capacitor Cz, the further
capacitor being connected at its second terminal between the intermediate
resistor R4 and the first resistor R1.
9. An integrating circuit according to claim 8 wherein a feedback loop for
the inverting input of the first amplifier comprises a resistor R5, and
wherein the feedback loop of the first amplifier and the grounding
resistor R2 are connected to ground via respective switching circuits
operable to reduce the integrating time constants.
10. An integrating circuit according to claim 8 wherein a feedback loop for
the inverting input of the first amplifier comprises a resistor R5, and
wherein the feedback loop of the first amplifier and the grounding
resistor R2 are connected to ground via respective switching circuits
operable to reduce the integrating time constants and wherein the
switching circuits comprise FET switching circuits Q1 and Q2.
11. A method of operating an integrating circuit including first and second
operational amplifiers, wherein an output of the first amplifier A.sub.1
is coupled via an attenuating network to an inverting input of the second
amplifier A.sub.2 and via an attenuating network to ground,
the first amplifier having an inverting input which has a feedback
connection to its output,
the second amplifier being configured as a Miller integrator, with the
feedback acting on the inverting input of the second amplifier,
an output of the second amplifier being connected to the non-inverting
input of the first amplifier,
signal input(s) IP.sub.1, IP.sub.2 to the integrating circuit being at the
non-inverting input of the first amplifier,
the method comprising the steps of inputting signals at the signal input(s)
IP.sub.1, IP.sub.2 to the integrating circuit and feeding a signal to the
first amplifier and its non-inverting input,
feeding back a signal between the output of the first amplifier and its
inverting input, coupling the output of the first amplifier A.sub.1 via an
attenuating network to an inverting input of the second amplifier A.sub.2
and to ground,
feeding back a signal from the output of the second amplifier and its
inverting input, whereby a modulated output is produced dependent upon the
relative phase of the input signals.
Description
FIELD OF THE INVENTION
This invention relates to an integrating circuit and finds application in
high time constant low bandwidth feedback loop arrangements, such as
temperature control circuits and in phase locked loop circuits.
BACKGROUND TO THE INVENTION
A well-known form of integrator is the Miller integrator. The Miller
integrator incorporates an active device, e.g. a transistor amplifier, in
order to improve the linearity of the output from a source such as a pulse
generator. A capacitance connected between the input and the output of the
amplifier results in an apparent increase in the capacitance across the
input terminals of the amplifier. With current technology the amplifier is
conveniently configured as an operational amplifier.
A Phase Lock Loop (PLL) is a frequently used circuit in communication
systems, and is employed, for example, in radio tuning circuits and clock
extraction circuits in optical fibre receivers for timing references.
The basic structure of a PLL is shown in FIG. 1. The main components
consist of a phase detector 10, a loop filter 12, a voltage controlled
oscillator 14 and a feed back loop 16 which typically incorporates a
divider 18. The PLL compares an incoming signal, such as a clock signal,
with its feedback clock.
The difference between these two signals generates an error signal
proportional to the gain of the phase detector, Kd, which error signal is
applied to the loop filter. The loop filter typically consists of an
active single pole-zero filter such as a typical Miller integrator with a
compensating zero, providing both high dc gain, which reduces input phase
error (usually the gain of the filter, G is not less than 40 dB) and low
frequency bandwidth. The output of this active filter adjusts a Voltage
Controlled Oscillator (VCO) or a crystal VCO (VCXO) to lock the output
signal to the input signal. The VCO however may have a centre frequency
(f.sub.o) at a much higher frequency (depending on system requirements)
and a therefore a divide down counter may be placed within the feedback
path, which completes the loop.
As with all second order feedback circuits (not just PLL) the PLL has two
distinct characteristics
The Natural Frequency, .omega..sub.n =2.pi.f.sub.n =(K.sub.o K.sub.d
G/t.sub.1 N).sup.1/2 ; and
the Damping Factor, .zeta.=(1/2.omega.t.sub.1)+(.omega..sub.n t.sub.2 /2)
These two parameters are determined by, inter alia, the characteristics of
the loop filter.
The 3 dB bandwidth of the PLL is known as the Jitter Bandwidth (f.sub.jb)
which is defined as:
##EQU1##
To prevent a jitter gain of greater than 0.5 dB; the damping factor,
.zeta., needs to be greater than or equal to 1.76.
With the advent of Passive Optical Networks (PON) becoming a means of
providing fibre to the home with the ability to allow householders to
become interactive (i.e. providing facilities such as video on demand,
home shopping etc.) the optical transmitter at the home (outstation)
requires very accurate timing information. This timing information can be
derived from the down stream source (the broadcast base station
transmitter). This timing information is provided to allow the outstation
optical transmitter to send data within its designated time slot. The
timing source at the base station is provided by a primary PLL which needs
to have a jitter bandwidth of no more than, typically, 0.1 Hz, for 50 Mb/s
transmission. This jitter bandwidth requires that the natural frequency of
the PLL must be in the order of 0.025 Hz.
If a standard Miller integrator of the type shown in FIG. 2 were used to
provide a jitter bandwidth of 0.025 Hz while maintaining a damping factor
equal to 1.76, then;
i) the first (pole) time constant, t.sub.1, would need to be
14.99.times.10.sup.3 sec; and
ii) the second (zero) time constant, t.sub.2, would need to be 21.55 sec
##EQU2##
Since t.sub.1 =Cf Rf
t.sub.2 =Cf Rz and
G=-Rf/Rs
Thus, if a standard Miller integrator were to be employed to provide such a
stringent PLL jitter bandwidth, the values of the resistors that would be
required would be of the order of tens of G.OMEGA.. Resistors of this
rating are, however, not be realisable when used with standard sizes of
low leakage, non-electrolytic capacitors.
An alternative type of Miller integrator is known from GB2220092B, and an
example of such is shown in FIG. 3. This type of circuit has the potential
to provide enhanced time constants: whilst this integrator effectively
multiplies the value of the integrating resistor by the gain G, the value
of R is still required to be of the order of M.OMEGA. which is
unrealisable in some practical circuits.
OBJECT OF THE INVENTION
The present invention seeks to provide an improved form of integrating
network wherein the values of the components employed in the circuit can
be both easily and economically obtained.
SUMMARY OF THE INVENTION
In accordance one aspect of the present invention, there is provided an
integrating circuit including first and second operational amplifiers, the
output of the first amplifier being coupled via an attenuation network to
an inverting input of the second amplifier and to ground, the first
amplifier having a feedback connection between its output and its
inverting input, the second amplifier being configured as a Miller
integrator, with the feedback acting on the inverting input of the second
amplifier, the output of the second amplifier being coupled to the
non-inverting input of the first amplifier by a part of the feedback loop,
the signal input(s) to the integrating circuit being at the non-inverting
inputs of the amplifiers.
In accordance with one embodiment, the output of the first amplifier is
coupled via first and third resistors to an inverting input of the second
amplifier and via first and second resistors to ground. The non-inverting
input of one amplifier can be connected to ground. A plurality of signal
input terminals can be connected to the non-inverting input of the first
amplifier via respective input resistances.
A plurality of signal input terminals can be connected to the non-inverting
input of one amplifier via respective input resistances.
The feedback circuit of the Miller integrator arrangement can further
comprise a resistor.
In accordance with another aspect of the present invention, there is
provided an integrating circuit including first and second operational
amplifiers, the output of the first amplifier being coupled via an
attenuating network to an inverting input of the second amplifier and to
ground, the first amplifier having a feedback connection between its
output and its inverting input, the second amplifier being configured as a
Miller integrator, with the feedback acting on the inverting input of the
second amplifier, the output of the second amplifier being connected to
the non-inverting input of the first amplifier, the signal inputs to the
integrating circuit being at the non-inverting inputs of the amplifiers,
wherein the output of the first amplifier is coupled via an intermediate
resistor and first and third resistors to an inverting input of the second
amplifier and the inverting input of the second amplifier is coupled via
first and second resistors to ground; and wherein the feedback loop of the
Miller integrator comprises a first capacitor which is connected to both
the non-inverting input of the second amplifier and a further capacitor,
the further capacitor being connected at its second terminal between the
intermediate resistor and the first resistor.
Preferably, the feedback loop for the inverting input of the first
amplifier comprises a resistor, and wherein the feedback loop of the first
amplifier and the grounding resistor are connected to ground via
respective switching circuits operable to reduce the integrating time
constants.
More preferably, the feedback loop for the inverting input of the first
amplifier comprises a resistor, and wherein the feedback loop of the first
amplifier and the grounding resistor are connected to ground via
respective switching circuits operable to reduce the integrating time
constants, and wherein the switching circuits comprise FET switching
circuits.
In accordance with a further aspect of the invention, there is provided a
method of operating an integrating circuit including first and second
operational amplifiers, wherein the output of the first amplifier is
coupled via an attenuating network to an inverting input of the second
amplifier and to ground, the first amplifier having a feedback connection
between its output and its inverting input, the second amplifier being
configured as a Miller integrator, with the feedback acting on the
inverting input of the second amplifier, the output of the second
amplifier being connected to the non-inverting input of the first
amplifier, the signal inputs to the integrating circuit being at the
non-inverting inputs of the amplifiers; the method comprising the steps of
inputting signals at the signal input ports to the integrating circuit and
feeding a signal to the first amplifier and its non-inverting input,
feeding back a signal between the output of the first amplifier and its
inverting input, coupling the output of the first amplifier via an
attenuating network to an inverting input of the second amplifier and to
ground, feeding back a signal from the output of the second amplifier and
its inverting input, whereby a modulated output is produced dependent upon
the relative phase of the input signals.
An integrating circuit in accordance with the present invention can be
designed to provide the required time constants t.sub.1 & t.sub.2 needed
for the primary phase locked loop for passive optical networks using
practical component values.
BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments of the invention will now be described with reference to the
accompanying drawings, wherein:
FIG. 1 depicts a basic phase lock loop layout;
FIG. 2 is a standard Miller integrator with a compensating zero;
FIG. 3 is a known Miller integrating circuit;
FIG. 4 is a first integrator made in accordance with the invention;
FIG. 5 is a second integrator made in accordance with the invention; and
FIG. 6 is a modified version of the second integrator shown in FIG. 5;
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Referring now to FIG. 4, there is shown one embodiment of the present
invention. The circuit comprises first and second operational amplifiers
A.sub.1, A.sub.2, with signal input terminals at IP.sub.1 to IP.sub.n and
an output at OP. A plurality of signal input terminals can be connected to
the non-inverting input of one amplifier via respective input resistances
Rs to Rsn. For convenience, the remainder of the description will refer to
only one input resistor Rs. The output of the first amplifier A.sub.1 is
connected via first and second resistors R1, R2 to ground and via first
and third resistors R1, R3 to an inverting input of the second amplifier.
The first amplifier has a feedback connection between its output and its
inverting input; the second amplifier is configured as a Miller
integrator. The Miller arrangement comprising a feedback acting on the
inverting input of the second amplifier. The feedback is shown as
comprising a capacitor Cf and resistor Rz in series, but the resistor need
not be present for certain designs. The output of the second amplifier is
connected via a fourth resistor Rf to the non-inverting input of the first
amplifier.
The timing constant, t.sub.1, can be calculated as follows:
t.sub.1 =Cf(R((1+Rf/Rs)/A)+Rz)
Since
t.sub.2 =Cf.Rz
A=R2/(R1+R2)
R=R3+(R1.R2/(R1+R2))
G=-Rf/Rs
It can be shown that the values of components can be:
Cf=3 .mu.F
Rs=1 K.OMEGA.
Rf=100 K.OMEGA.
Rz=7.2 K.OMEGA.
R1=48.5 K.OMEGA.
R2=1 K.OMEGA.
R3=1 M.OMEGA.
The effect of placing an attenuation network formed by R1 & R2 within the
feedback path of the two op-amps, multiplies the effect of the source
resistance which is modelled by R. If the parallel combination of R1 & R2
are small in comparison to R3, then R.about.R3. The effect on R is
multiplied by (1+G) but with the addition of only two resistors which
provide an attenuated signal, the multiplication is thus enhanced to
(1+G)/A.
This effect is also beneficial if an application calls for a low value of
gain G but a high time constant t.sub.1. If for example the circuit shown
in FIG. 3 were used to provide an integrating function with unity gain and
no zero (i.e. Rz=0), then t.sub.1 =2 C R which provides little advantage
over the standard Miller integrator. However, in the embodiment shown, the
time constant, t.sub.1 =2 C R/A, and A could be small to make the time
constant large.
Whilst the value of the capacitance Cf has been reduced to a more
manageable 3 .mu.F, the compensating resistor, Rz (zero compensation) is
required to be 7.2 M.OMEGA.. Such large resistances can be implemented
fairly easily using a number of smaller value resistors, but take up
expensive board space. Obviously, all surface mounted components take up
board space, which is usually at a premium, and a small number of surface
mount components is preferred. To overcome this requirement, it would be
possible to place an additional capacitance parallel with resistances R1
and R3 and placing an additional resistance, R4 between the first
amplifier and the resistance R1. This utilises the effective large
resistance formed by the T network of resistances R1, R2 and R3. This is
illustrated in FIG. 5.
It can be shown that the values of components can be:
Cf=1 .mu.F
Cz=150 nF
Rs=1 K.OMEGA.
Rf=100 K.OMEGA.
R1=120 K.OMEGA.
R2=820 K.OMEGA.
R3=1 M.OMEGA.
R4=10 K.OMEGA.
Since
t.sub.1 =Cf(R((1+Rf/Rs)/A)+Rz)
t.sub.2 =Cz.Rz
A=R2/(R1+R2)
R=R3+(R1.R2/(R1+R2))
Rz=R1+R3(1+R1/R2); assuming R4<<R1
G=-Rf/Rs
As shown by FIG. 5 and the above equations, the introduction of a
compensation capacitance in parallel with the T network, produces a large
time constant of 22 s using a small capacitance of 150 nF. An additional
resistor R4 is required to provide a resistive load for stability of the
unity gain operational amplifier.
The use of the loop filters shown in FIGS. 4 and 5 within a PLL would
require an unreasonable amount of time to provide a locked output clock.
This severe problem may be overcome by increasing the PLL jitter bandwidth
to provide a rapid lock-in time. Once in lock, the PLL would revert to its
intended low jitter bandwidth. One implementation of this technique is
shown in FIG. 6. In this case, FET switches are provided, which operate to
reduce the time constants t1 and t2 in a lock-in mode. A digital lock
detection circuit is required (not shown) to detect the state of lock, and
these can easily be implemented using one of several well known
techniques.
The FET switches are formed by transistors Q1 and Q2, which are
respectively connected to diodes D1 and D2 with resistors R7 and R8
connecting the link from the diodes to the gates of the transistors to
ground. In fast lock mode, Q1 is switched on and Q2 is switched off,
whereby the first op-amp is configured as a high gain stage K=R5/(Ron Q1),
which is approximately 2000 (i.e. 66 dB). At this time Q2 would be off and
thus the T network would have an effective resistance determined by the
sum of R1, R3 and R4, equal to 1.13 M.OMEGA..
The new time constants under fast lock conditions are determined by the
following equations:
t.sub.1 =Cf((R4+R1+R3)(1+Rf/Rs)/K))
t.sub.2 =Cz(R4+R1+R3)
A=1
K=R5/RonQ1
It can be shown, for component values as follows:
Cf=1 .mu.F
Rs=1 K.OMEGA.
Rf=100 K.OMEGA.
Cz=150 nF
R1=120 K.OMEGA.
R2=820 K.OMEGA.
R3=1 M.OMEGA.
R4=10 K.OMEGA.
R5=200 K.OMEGA.
R6=1 M.OMEGA.
R7=10 K.OMEGA.
R8=10 K.OMEGA.
that the fast lock can be determined from the following equation:
##EQU3##
and that slow lock can be determined from the following equation:
##EQU4##
It follows that the time constants are reduced: t1 from 15000 S to 57 mS
and t2 from 22 S to 168 mS. Once the output clock from the PLL is locked
to the incoming reference clock, an in-lock detector (not shown) would
provide an appropriate control signal to the FET switches to revert to the
PLL's ultra-low jitter bandwidth mode.
Although the modified Miller integrator shown in FIG. 5 has been employed
to provide a very long time constant using discrete technology, the same
circuit can be employed to provide long time constants for Integrated
monolithic Circuits (ICs). Typical IC fabrication techniques can only
provide monolithic capacitors of the order of tens of pico farads.
Accordingly, if large integrating time constants are required, such as
typically required in the case of monolithic PLLs, this can be only be
achieved by using separate, large external capacitances. By the use of the
techniques described above, however, a fully integrated PLL would be
possible.
* * * * *
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