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[Search a list of Patent Appplications for class 257]  Class   257ACTIVE SOLID-STATE DEVICES (E.G., TRANSISTORS, SOLID-STATE DIODES)
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When placing a mandatory classification in Class 257, a cross-reference classification is normally made in at least one of the appended E-subclasses.
[List of Patents for class 257 subclass 1]  1           BULK EFFECT DEVICE
[List of Patents for class 257 subclass 2]  2           Subclass 2 indent level is 1 Bulk effect switching in amorphous material
[List of Patents for class 257 subclass 3]  3           Subclass 3 indent level is 2 With means to localize region of conduction (e.g., "pore" structure)
[List of Patents for class 257 subclass 4]  4           Subclass 4 indent level is 2 With specified electrode composition or configuration
[List of Patents for class 257 subclass 5]  5           Subclass 5 indent level is 2 In array
[List of Patents for class 257 subclass 6]  6           Subclass 6 indent level is 1 Intervalley transfer (e.g., Gunn effect)
[List of Patents for class 257 subclass 7]  7           Subclass 7 indent level is 2 In monolithic integrated circuit
[List of Patents for class 257 subclass 8]  8           Subclass 8 indent level is 2 Three or more terminal device
[List of Patents for class 257 subclass 9]  9           THIN ACTIVE PHYSICAL LAYER WHICH IS (1) AN ACTIVE POTENTIAL WELL LAYER THIN ENOUGH TO ESTABLISH DISCRETE QUANTUM ENERGY LEVELS OR (2) AN ACTIVE BARRIER LAYER THIN ENOUGH TO PERMIT QUANTUM MECHANICAL TUNNELING OR (3) AN ACTIVE LAYER THIN ENOUGH TO PERMIT CARRIER TRANSMISSION WITH SUBSTANTIALLY NO SCATTERING (E.G., SUPERLATTICE QUANTUM WELL, OR BALLISTIC TRANSPORT DEVICE)
[List of Patents for class 257 subclass 10]  10           Subclass 10 indent level is 1 Low workfunction layer for electron emission (e.g., photocathode electron emissive layer)
[List of Patents for class 257 subclass 11]  11           Subclass 11 indent level is 2 Combined with a heterojunction involving a III-V compound
[List of Patents for class 257 subclass 12]  12           Subclass 12 indent level is 1 Heterojunction
[List of Patents for class 257 subclass 13]  13           Subclass 13 indent level is 2 Incoherent light emitter
[List of Patents for class 257 subclass 14]  14           Subclass 14 indent level is 2 Quantum well
[List of Patents for class 257 subclass 15]  15           Subclass 15 indent level is 3 Superlattice
[List of Patents for class 257 subclass 16]  16           Subclass 16 indent level is 4 Of amorphous semiconductor material
[List of Patents for class 257 subclass 17]  17           Subclass 17 indent level is 4 With particular barrier dimension
[List of Patents for class 257 subclass 18]  18           Subclass 18 indent level is 4 Strained layer superlattice
[List of Patents for class 257 subclass 19]  19           Subclass 19 indent level is 5 Si x Ge 1-x
[List of Patents for class 257 subclass 20]  20           Subclass 20 indent level is 4 Field effect device
[List of Patents for class 257 subclass 21]  21           Subclass 21 indent level is 4 Light responsive structure
[List of Patents for class 257 subclass 22]  22           Subclass 22 indent level is 4 With specified semiconductor materials
[List of Patents for class 257 subclass 23]  23           Subclass 23 indent level is 3 Current flow across well
[List of Patents for class 257 subclass 24]  24           Subclass 24 indent level is 3 Field effect device
[List of Patents for class 257 subclass 25]  25           Subclass 25 indent level is 3 Employing resonant tunneling
[List of Patents for class 257 subclass 26]  26           Subclass 26 indent level is 2 Ballistic transport device
[List of Patents for class 257 subclass 27]  27           Subclass 27 indent level is 3 Field effect transistor
[List of Patents for class 257 subclass 28]  28           Subclass 28 indent level is 1 Non-heterojunction superlattice (e.g., doping superlattice or alternating metal and insulator layers)
[List of Patents for class 257 subclass 29]  29           Subclass 29 indent level is 1 Ballistic transport device (e.g., hot electron transistor)
[List of Patents for class 257 subclass 30]  30           Subclass 30 indent level is 1 Tunneling through region of reduced conductivity
[List of Patents for class 257 subclass 31]  31           Subclass 31 indent level is 2 Josephson
[List of Patents for class 257 subclass 32]  32           Subclass 32 indent level is 3 Particular electrode material
[List of Patents for class 257 subclass 33]  33           Subclass 33 indent level is 4 High temperature (i.e., >30o Kelvin)
[List of Patents for class 257 subclass 34]  34           Subclass 34 indent level is 3 Weak link (e.g., narrowed portion of superconductive line)
[List of Patents for class 257 subclass 35]  35           Subclass 35 indent level is 3 Particular barrier material
[List of Patents for class 257 subclass 36]  36           Subclass 36 indent level is 3 With additional electrode to control conductive state of Josephson junction
[List of Patents for class 257 subclass 37]  37           Subclass 37 indent level is 2 At least one electrode layer of semiconductor material
[List of Patents for class 257 subclass 38]  38           Subclass 38 indent level is 3 Three or more electrode device
[List of Patents for class 257 subclass 39]  39           Subclass 39 indent level is 2 Three or more electrode device
[List of Patents for class 257 subclass 40]  40           ORGANIC SEMICONDUCTOR MATERIAL
[List of Patents for class 257 subclass 41]  41           POINT CONTACT DEVICE
[List of Patents for class 257 subclass 42]  42           SEMICONDUCTOR IS SELENIUM OR TELLURIUM IN ELEMENTAL FORM
[List of Patents for class 257 subclass 43]  43           SEMICONDUCTOR IS AN OXIDE OF A METAL (E.G., CUO, ZNO) OR COPPER SULFIDE
[List of Patents for class 257 subclass 44]  44           WITH METAL CONTACT ALLOYED TO ELEMENTAL SEMICONDUCTOR TYPE PN JUNCTION IN NONREGENERATIVE STRUCTURE
[List of Patents for class 257 subclass 45]  45           Subclass 45 indent level is 1 Elongated alloyed region (e.g., thermal gradient zone melting, TGZM)
[List of Patents for class 257 subclass 46]  46           Subclass 46 indent level is 1 In pn junction tunnel diode (Esaki diode)
[List of Patents for class 257 subclass 47]  47           Subclass 47 indent level is 1 In bipolar transistor structure
[List of Patents for class 257 subclass 48]  48           TEST OR CALIBRATION STRUCTURE
[List of Patents for class 257 subclass 49]  49           NON-SINGLE CRYSTAL, OR RECRYSTALLIZED, SEMICONDUCTOR MATERIAL FORMS PART OF ACTIVE JUNCTION (INCLUDING FIELD-INDUCED ACTIVE JUNCTION)
[List of Patents for class 257 subclass 50]  50           Subclass 50 indent level is 1 Non-single crystal, or recrystallized, active junction adapted to be electrically shorted (e.g., "anti-fuse" element)
[List of Patents for class 257 subclass 51]  51           Subclass 51 indent level is 1 Non-single crystal, or recrystallized, material forms active junction with single crystal material (e.g., monocrystal to polycrystal pn junction or heterojunction)
[List of Patents for class 257 subclass 52]  52           Subclass 52 indent level is 1 Amorphous semiconductor material
[List of Patents for class 257 subclass 53]  53           Subclass 53 indent level is 2 Responsive to nonelectrical external signals (e.g., light)
[List of Patents for class 257 subclass 54]  54           Subclass 54 indent level is 3 With Schottky barrier to amorphous material
[List of Patents for class 257 subclass 55]  55           Subclass 55 indent level is 3 Amorphous semiconductor is alloy or contains material to change band gap (e.g., Si x Ge 1-x , SiN y )
[List of Patents for class 257 subclass 56]  56           Subclass 56 indent level is 3 With impurity other than hydrogen to passivate dangling bonds (e.g., halide)
[List of Patents for class 257 subclass 57]  57           Subclass 57 indent level is 2 Field effect device in amorphous semiconductor material
[List of Patents for class 257 subclass 58]  58           Subclass 58 indent level is 3 With impurity other than hydrogen to passivate dangling bonds (e.g., halide)
[List of Patents for class 257 subclass 59]  59           Subclass 59 indent level is 3 In array having structure for use as imager or display, or with transparent electrode
[List of Patents for class 257 subclass 60]  60           Subclass 60 indent level is 3 With field electrode under or on a side edge of amorphous semiconductor material (e.g., vertical current path)
[List of Patents for class 257 subclass 61]  61           Subclass 61 indent level is 3 With heavily doped regions contacting amorphous semiconductor material (e.g., heavily doped source and drain)
[List of Patents for class 257 subclass 62]  62           Subclass 62 indent level is 2 With impurity other than hydrogen to passivate dangling bonds (e.g., halide)
[List of Patents for class 257 subclass 63]  63           Subclass 63 indent level is 2 Amorphous semiconductor is alloy or contains material to change band gap (e.g., Si x Ge 1-x , SiN y )
[List of Patents for class 257 subclass 64]  64           Subclass 64 indent level is 1 Non-single crystal, or recrystallized, material with specified crystal structure (e.g., specified crystal size or orientation)
[List of Patents for class 257 subclass 65]  65           Subclass 65 indent level is 1 Non-single crystal, or recrystallized, material containing non-dopant additive, or alloy of semiconductor materials (e.g., Ge x Si 1- x, polycrystalline silicon with dangling bond modifier)
[List of Patents for class 257 subclass 66]  66           Subclass 66 indent level is 1 Field effect device in non-single crystal, or recrystallized, Semiconductor material
[List of Patents for class 257 subclass 67]  67           Subclass 67 indent level is 2 In combination with device formed in single crystal semiconductor material (e.g., stacked FETs)
[List of Patents for class 257 subclass 68]  68           Subclass 68 indent level is 3 Capacitor element in single crystal semiconductor (e.g., DRAM)
[List of Patents for class 257 subclass 69]  69           Subclass 69 indent level is 3 Field effect transistor in single crystal material, complementary to that in non-single crystal, or recrystallized, material (e.g., CMOS)
[List of Patents for class 257 subclass 70]  70           Subclass 70 indent level is 3 Recrystallized semiconductor material
[List of Patents for class 257 subclass 71]  71           Subclass 71 indent level is 2 In combination with capacitor element (e.g., DRAM)
[List of Patents for class 257 subclass 72]  72           Subclass 72 indent level is 2 In array having structure for use as imager or display, or with transparent electrode
[List of Patents for class 257 subclass 73]  73           Subclass 73 indent level is 1 Schottky barrier to polycrystalline semiconductor material
[List of Patents for class 257 subclass 74]  74           Subclass 74 indent level is 1 Plural recrystallized semiconductor layers (e.g., "3-dimensional integrated circuit")
[List of Patents for class 257 subclass 75]  75           Subclass 75 indent level is 1 Recrystallized semiconductor material
[List of Patents for class 257 subclass 76]  76           SPECIFIED WIDE BAND GAP (1.5EV) SEMICONDUCTOR MATERIAL OTHER THAN GAASP OR GAALAS
[List of Patents for class 257 subclass 77]  77           Subclass 77 indent level is 1 Diamond or silicon carbide
[List of Patents for class 257 subclass 78]  78           Subclass 78 indent level is 1 II-VI compound
[List of Patents for class 257 subclass 79]  79           INCOHERENT LIGHT EMITTER STRUCTURE
[List of Patents for class 257 subclass 80]  80           Subclass 80 indent level is 1 In combination with or also constituting light responsive device
[List of Patents for class 257 subclass 81]  81           Subclass 81 indent level is 2 With specific housing or contact structure
[List of Patents for class 257 subclass 82]  82           Subclass 82 indent level is 3 Discrete light emitting and light responsive devices
[List of Patents for class 257 subclass 83]  83           Subclass 83 indent level is 2 Light coupled transistor structure
[List of Patents for class 257 subclass 84]  84           Subclass 84 indent level is 2 Combined in integrated structure
[List of Patents for class 257 subclass 85]  85           Subclass 85 indent level is 3 With heterojunction
[List of Patents for class 257 subclass 86]  86           Subclass 86 indent level is 1 Active layer of indirect band gap semiconductor
[List of Patents for class 257 subclass 87]  87           Subclass 87 indent level is 2 With means to facilitate electron-hole recombination (e.g., isoelectronic traps such as nitrogen in GaP)
[List of Patents for class 257 subclass 88]  88           Subclass 88 indent level is 1 Plural light emitting devices (e.g., matrix, 7-segment array)
[List of Patents for class 257 subclass 89]  89           Subclass 89 indent level is 2 Multi-color emission
[List of Patents for class 257 subclass 90]  90           Subclass 90 indent level is 3 With heterojunction
[List of Patents for class 257 subclass 91]  91           Subclass 91 indent level is 2 With shaped contacts or opaque masking
[List of Patents for class 257 subclass 92]  92           Subclass 92 indent level is 2 Alphanumeric segmented array
[List of Patents for class 257 subclass 93]  93           Subclass 93 indent level is 2 With electrical isolation means in integrated circuit structure
[List of Patents for class 257 subclass 94]  94           Subclass 94 indent level is 1 With heterojunction
[List of Patents for class 257 subclass 95]  95           Subclass 95 indent level is 2 With contoured external surface (e.g., dome shape to facilitate light emission)
[List of Patents for class 257 subclass 96]  96           Subclass 96 indent level is 2 Plural heterojunctions in same device
[List of Patents for class 257 subclass 97]  97           Subclass 97 indent level is 3 More than two heterojunctions in same device
[List of Patents for class 257 subclass 98]  98           Subclass 98 indent level is 1 With reflector, opaque mask, or optical element (e.g., lens, optical fiber, index of refraction matching layer, luminescent material layer, filter) integral with device or device enclosure or package
[List of Patents for class 257 subclass 99]  99           Subclass 99 indent level is 1 With housing or contact structure
[List of Patents for class 257 subclass 100]  100           Subclass 100 indent level is 1 Encapsulated
[List of Patents for class 257 subclass 101]  101           Subclass 101 indent level is 1 With particular dopant concentration or concentration profile (e.g., graded junction)
[List of Patents for class 257 subclass 102]  102           Subclass 102 indent level is 1 With particular dopant material (e.g., zinc as dopant in GaAs)
[List of Patents for class 257 subclass 103]  103           Subclass 103 indent level is 1 With particular semiconductor material
[List of Patents for class 257 subclass 104]  104           TUNNELING PN JUNCTION (E.G., ESAKI DIODE) DEVICE
[List of Patents for class 257 subclass 105]  105           Subclass 105 indent level is 1 In three or more terminal device
[List of Patents for class 257 subclass 106]  106           Subclass 106 indent level is 1 Reverse bias tunneling structure (e.g., "backward" diode, true Zener diode)
[List of Patents for class 257 subclass 107]  107           REGENERATIVE TYPE SWITCHING DEVICE (E.G., SCR, COMFET, THYRISTOR)
[List of Patents for class 257 subclass 108]  108           Subclass 108 indent level is 1 Controlled by nonelectrical, nonoptical external signal (e.g., magnetic field, pressure, thermal)
[List of Patents for class 257 subclass 109]  109           Subclass 109 indent level is 1 Having only two terminals and no control electrode (gate), e.g., Shockley diode
[List of Patents for class 257 subclass 110]  110           Subclass 110 indent level is 2 More than four semiconductor layers of alternating conductivity types (e.g., pnpnpn structure, 5 layer bidirectional diacs, etc.)
[List of Patents for class 257 subclass 111]  111           Subclass 111 indent level is 2 Triggered by V BO overvoltage means
[List of Patents for class 257 subclass 112]  112           Subclass 112 indent level is 2 With highly-doped breakdown diode trigger
[List of Patents for class 257 subclass 113]  113           Subclass 113 indent level is 1 With light activation
[List of Patents for class 257 subclass 114]  114           Subclass 114 indent level is 2 With separate light detector integrated on chip with regenerative switching device
[List of Patents for class 257 subclass 115]  115           Subclass 115 indent level is 2 With electrical trigger signal amplification means (e.g., amplified gate, "pilot thyristor", etc.)
[List of Patents for class 257 subclass 116]  116           Subclass 116 indent level is 2 With light conductor means (e.g., light fiber or light pipe) integral with device or device enclosure or package
[List of Patents for class 257 subclass 117]  117           Subclass 117 indent level is 3 In groove or with thinned semiconductor portion
[List of Patents for class 257 subclass 118]  118           Subclass 118 indent level is 2 With groove or thinned light sensitive portion
[List of Patents for class 257 subclass 119]  119           Subclass 119 indent level is 1 Bidirectional rectifier with control electrode (gate) (e.g., Triac)
[List of Patents for class 257 subclass 120]  120           Subclass 120 indent level is 2 Six or more semiconductor layers of alternating conductivity types (e.g., npnpnpn structure)
[List of Patents for class 257 subclass 121]  121           Subclass 121 indent level is 2 With diode or transistor in reverse path
[List of Patents for class 257 subclass 122]  122           Subclass 122 indent level is 2 Lateral
[List of Patents for class 257 subclass 123]  123           Subclass 123 indent level is 2 With trigger signal amplification (e.g., amplified gate)
[List of Patents for class 257 subclass 124]  124           Subclass 124 indent level is 2 Combined with field effect transistor structure
[List of Patents for class 257 subclass 125]  125           Subclass 125 indent level is 3 Controllable emitter shunting
[List of Patents for class 257 subclass 126]  126           Subclass 126 indent level is 2 With means to separate a device into sections having different conductive polarity
[List of Patents for class 257 subclass 127]  127           Subclass 127 indent level is 3 Guard ring or groove
[List of Patents for class 257 subclass 128]  128           Subclass 128 indent level is 2 Having overlapping sections of different conductive polarity
[List of Patents for class 257 subclass 129]  129           Subclass 129 indent level is 2 With means to increase reverse breakdown voltage
[List of Patents for class 257 subclass 130]  130           Subclass 130 indent level is 2 Switching speed enhancement means
[List of Patents for class 257 subclass 131]  131           Subclass 131 indent level is 3 Recombination centers or deep level dopants
[List of Patents for class 257 subclass 132]  132           Subclass 132 indent level is 1 Five or more layer unidirectional structure
[List of Patents for class 257 subclass 133]  133           Subclass 133 indent level is 1 Combined with field effect transistor
[List of Patents for class 257 subclass 134]  134           Subclass 134 indent level is 2 J-FET (junction field effect transistor)
[List of Patents for class 257 subclass 135]  135           Subclass 135 indent level is 3 Vertical (i.e., where the source is located above the drain or vice versa)
[List of Patents for class 257 subclass 136]  136           Subclass 136 indent level is 4 Enhancement mode (e.g., so-called SITs)
[List of Patents for class 257 subclass 137]  137           Subclass 137 indent level is 2 Having controllable emitter shunt
[List of Patents for class 257 subclass 138]  138           Subclass 138 indent level is 3 Having gate turn off (GTO) feature
[List of Patents for class 257 subclass 139]  139           Subclass 139 indent level is 2 With extended latchup current level (e.g., COMFET device)
[List of Patents for class 257 subclass 140]  140           Subclass 140 indent level is 3 Combined with other solid-state active device in integrated structure
[List of Patents for class 257 subclass 141]  141           Subclass 141 indent level is 3 Lateral structure, i.e., current flow parallel to main device surface
[List of Patents for class 257 subclass 142]  142           Subclass 142 indent level is 3 Having impurity doping for gain reduction
[List of Patents for class 257 subclass 143]  143           Subclass 143 indent level is 3 Having anode shunt means
[List of Patents for class 257 subclass 144]  144           Subclass 144 indent level is 3 Cathode emitter or cathode electrode feature
[List of Patents for class 257 subclass 145]  145           Subclass 145 indent level is 3 Low impedance channel contact extends below surface
[List of Patents for class 257 subclass 146]  146           Subclass 146 indent level is 1 Combined with other solid-state active device in integrated structure
[List of Patents for class 257 subclass 147]  147           Subclass 147 indent level is 1 With extended latchup current level (e.g., gate turn off "GTO" device)
[List of Patents for class 257 subclass 148]  148           Subclass 148 indent level is 2 Having impurity doping for gain reduction
[List of Patents for class 257 subclass 149]  149           Subclass 149 indent level is 2 Having anode shunt means
[List of Patents for class 257 subclass 150]  150           Subclass 150 indent level is 2 With specified housing or external terminal
[List of Patents for class 257 subclass 151]  151           Subclass 151 indent level is 3 External gate terminal structure or composition
[List of Patents for class 257 subclass 152]  152           Subclass 152 indent level is 2 Cathode emitter or cathode electrode feature
[List of Patents for class 257 subclass 153]  153           Subclass 153 indent level is 2 Gate region or electrode feature
[List of Patents for class 257 subclass 154]  154           Subclass 154 indent level is 1 With resistive region connecting separate sections of device
[List of Patents for class 257 subclass 155]  155           Subclass 155 indent level is 1 With switching speed enhancement means (e.g., Schottky contact)
[List of Patents for class 257 subclass 156]  156           Subclass 156 indent level is 2 Having deep level dopants or recombination centers
[List of Patents for class 257 subclass 157]  157           Subclass 157 indent level is 1 With integrated trigger signal amplification means (e.g., amplified gate, "pilot thyristor", etc.)
[List of Patents for class 257 subclass 158]  158           Subclass 158 indent level is 2 Three or more amplification stages
[List of Patents for class 257 subclass 159]  159           Subclass 159 indent level is 2 Transistor as amplifier
[List of Patents for class 257 subclass 160]  160           Subclass 160 indent level is 2 With distributed amplified current
[List of Patents for class 257 subclass 161]  161           Subclass 161 indent level is 2 With a turn-off diode
[List of Patents for class 257 subclass 162]  162           Subclass 162 indent level is 1 Lateral structure
[List of Patents for class 257 subclass 163]  163           Subclass 163 indent level is 1 Emitter region feature
[List of Patents for class 257 subclass 164]  164           Subclass 164 indent level is 2 Multi-emitter region (e.g., emitter geometry or emitter ballast resistor)
[List of Patents for class 257 subclass 165]  165           Subclass 165 indent level is 3 Laterally symmetric regions
[List of Patents for class 257 subclass 166]  166           Subclass 166 indent level is 3 Radially symmetric regions
[List of Patents for class 257 subclass 167]  167           Subclass 167 indent level is 1 Having at least four external electrodes
[List of Patents for class 257 subclass 168]  168           Subclass 168 indent level is 1 With means to increase breakdown voltage
[List of Patents for class 257 subclass 169]  169           Subclass 169 indent level is 2 High resistivity base layer
[List of Patents for class 257 subclass 170]  170           Subclass 170 indent level is 2 Surface feature (e.g., guard ring, groove, mesa, etc.)
[List of Patents for class 257 subclass 171]  171           Subclass 171 indent level is 3 Edge feature (e.g., beveled edge)
[List of Patents for class 257 subclass 172]  172           Subclass 172 indent level is 1 With means to lower "ON" voltage drop
[List of Patents for class 257 subclass 173]  173           Subclass 173 indent level is 1 Device protection (e.g., from overvoltage)
[List of Patents for class 257 subclass 174]  174           Subclass 174 indent level is 2 Rate of rise of current (e.g., dI/dt)
[List of Patents for class 257 subclass 175]  175           Subclass 175 indent level is 1 With means to control triggering (e.g., gate electrode configuration, Zener diode firing, dV/Dt control, transient control by ferrite bead, etc.)
[List of Patents for class 257 subclass 176]  176           Subclass 176 indent level is 2 Located in an emitter-gate region
[List of Patents for class 257 subclass 177]  177           Subclass 177 indent level is 1 With housing or external electrode
[List of Patents for class 257 subclass 178]  178           Subclass 178 indent level is 2 With means to avoid stress between electrode and active device (e.g., thermal expansion matching of electrode to semiconductor)
[List of Patents for class 257 subclass 179]  179           Subclass 179 indent level is 3 With malleable electrode (e.g., silver electrode layer)
[List of Patents for class 257 subclass 180]  180           Subclass 180 indent level is 2 Stud mount
[List of Patents for class 257 subclass 181]  181           Subclass 181 indent level is 2 With large area flexible electrodes in press contact with opposite sides of active semiconductor chip and surrounded by an insulating element, (e.g., ring)
[List of Patents for class 257 subclass 182]  182           Subclass 182 indent level is 3 With lead feedthrough means on side of housing
[List of Patents for class 257 subclass 183]  183           HETEROJUNCTION DEVICE
[List of Patents for class 257 subclass 183.1]  183.1           Subclass 183.1 indent level is 1 Charge transfer device
[List of Patents for class 257 subclass 184]  184           Subclass 184 indent level is 1 Light responsive structure
[List of Patents for class 257 subclass 185]  185           Subclass 185 indent level is 2 Staircase (including graded composition) device
[List of Patents for class 257 subclass 186]  186           Subclass 186 indent level is 2 Avalanche photodetection structure
[List of Patents for class 257 subclass 187]  187           Subclass 187 indent level is 2 Having transistor structure
[List of Patents for class 257 subclass 188]  188           Subclass 188 indent level is 2 Having narrow energy band gap (<<1eV) layer (e.g., PbSnTe, HgCdTe, etc.)
[List of Patents for class 257 subclass 189]  189           Subclass 189 indent level is 3 Layer is a group III-V semiconductor compound
[List of Patents for class 257 subclass 190]  190           Subclass 190 indent level is 1 With lattice constant mismatch (e.g., with buffer layer to accommodate mismatch)
[List of Patents for class 257 subclass 191]  191           Subclass 191 indent level is 1 Having graded composition
[List of Patents for class 257 subclass 192]  192           Subclass 192 indent level is 1 Field effect transistor
[List of Patents for class 257 subclass 194]  194           Subclass 194 indent level is 2 Doping on side of heterojunction with lower carrier affinity (e.g., high electron mobility transistor (HEMT))
[List of Patents for class 257 subclass 195]  195           Subclass 195 indent level is 3 Combined with diverse type device
[List of Patents for class 257 subclass 196]  196           Subclass 196 indent level is 1 Both semiconductors of the heterojunction are the same conductivity type (i.e., either n or p)
[List of Patents for class 257 subclass 197]  197           Subclass 197 indent level is 1 Bipolar transistor
[List of Patents for class 257 subclass 198]  198           Subclass 198 indent level is 2 Wide band gap emitter
[List of Patents for class 257 subclass 199]  199           Subclass 199 indent level is 1 Avalanche diode (e.g., so-called "Zener" diode having breakdown voltage greater than 6 volts, including heterojunction IMPATT type microwave diodes)
[List of Patents for class 257 subclass 200]  200           Subclass 200 indent level is 1 Heterojunction formed between semiconductor materials which differ in that they belong to different periodic table groups (e.g., Ge (group IV) - GaAs (group III-V) or InP (group III-V) - CdTe (group II-VI))
[List of Patents for class 257 subclass 201]  201           Subclass 201 indent level is 1 Between different group IV-VI or II-VI or III-V compounds other than GaAs/GaAlAs
[List of Patents for class 257 subclass 202]  202           GATE ARRAYS
[List of Patents for class 257 subclass 203]  203           Subclass 203 indent level is 1 With particular chip input/output means
[List of Patents for class 257 subclass 204]  204           Subclass 204 indent level is 1 Having specific type of active device (e.g., CMOS)
[List of Patents for class 257 subclass 205]  205           Subclass 205 indent level is 2 With bipolar transistors or with FETs of only one channel conductivity type (e.g., enhancement-depletion FETs)
[List of Patents for class 257 subclass 206]  206           Subclass 206 indent level is 2 Particular layout of complementary FETs with regard to each other
[List of Patents for class 257 subclass 207]  207           Subclass 207 indent level is 1 With particular power supply distribution means
[List of Patents for class 257 subclass 208]  208           Subclass 208 indent level is 1 With particular signal path connections
[List of Patents for class 257 subclass 209]  209           Subclass 209 indent level is 2 Programmable signal paths (e.g., with fuse elements, laser programmable, etc)
[List of Patents for class 257 subclass 210]  210           Subclass 210 indent level is 2 With wiring channel area
[List of Patents for class 257 subclass 211]  211           Subclass 211 indent level is 2 Multi-level metallization
[List of Patents for class 257 subclass 212]  212           CONDUCTIVITY MODULATION DEVICE (E.G., UNIJUNCTION TRANSISTOR, DOUBLE-BASE DIODE, CONDUCTIVITY-MODULATED TRANSISTOR)
[List of Patents for class 257 subclass 213]  213           FIELD EFFECT DEVICE
[List of Patents for class 257 subclass 214]  214           Subclass 214 indent level is 1 Charge injection device
[List of Patents for class 257 subclass 215]  215           Subclass 215 indent level is 1 Charge transfer device
[List of Patents for class 257 subclass 216]  216           Subclass 216 indent level is 2 Majority signal carrier (e.g., buried or bulk channel, or peristaltic)
[List of Patents for class 257 subclass 217]  217           Subclass 217 indent level is 3 Having a conductive means in direct contact with channel (e.g., non-insulated gate)
[List of Patents for class 257 subclass 218]  218           Subclass 218 indent level is 3 High resistivity channel (e.g., accumulation mode) or surface channel (e.g., transfer of signal charge occurs at the surface of the semiconductor) or minority carriers at input (i.e., surface channel input)
[List of Patents for class 257 subclass 219]  219           Subclass 219 indent level is 3 Impurity concentration variation
[List of Patents for class 257 subclass 220]  220           Subclass 220 indent level is 4 Vertically within channel (e.g., profiled)
[List of Patents for class 257 subclass 221]  221           Subclass 221 indent level is 4 Along the length of the channel (e.g., doping variations for transfer directionality)
[List of Patents for class 257 subclass 222]  222           Subclass 222 indent level is 3 Responsive to non-electrical external signal (e.g., imager)
[List of Patents for class 257 subclass 223]  223           Subclass 223 indent level is 4 Having structure to improve output signal (e.g., antiblooming drain)
[List of Patents for class 257 subclass 224]  224           Subclass 224 indent level is 3 Channel confinement
[List of Patents for class 257 subclass 225]  225           Subclass 225 indent level is 2 Non-electrical input responsive (e.g., light responsive imager, input programmed by size of storage sites for use as a read-only memory, etc.)
[List of Patents for class 257 subclass 226]  226           Subclass 226 indent level is 3 Sensor element and charge transfer device are of different materials or on different substrates (e.g., "hybrid")
[List of Patents for class 257 subclass 227]  227           Subclass 227 indent level is 3 With specified dopant (e.g., photoionizable, "extrinsic" detectors for infrared)
[List of Patents for class 257 subclass 228]  228           Subclass 228 indent level is 3 Light responsive, back illuminated
[List of Patents for class 257 subclass 229]  229           Subclass 229 indent level is 3 Having structure to improve output signal (e.g., exposure control structure)
[List of Patents for class 257 subclass 230]  230           Subclass 230 indent level is 4 With blooming suppression structure
[List of Patents for class 257 subclass 231]  231           Subclass 231 indent level is 3 2-dimensional area architecture
[List of Patents for class 257 subclass 232]  232           Subclass 232 indent level is 4 Having alternating strips of sensor structures and register structures (e.g., interline imager)
[List of Patents for class 257 subclass 233]  233           Subclass 233 indent level is 4 Sensors not overlaid by electrode (e.g., photodiodes)
[List of Patents for class 257 subclass 234]  234           Subclass 234 indent level is 3 Single strip of sensors (e.g., linear imager)
[List of Patents for class 257 subclass 235]  235           Subclass 235 indent level is 2 Electrical input
[List of Patents for class 257 subclass 236]  236           Subclass 236 indent level is 3 Signal applied to field effect electrode
[List of Patents for class 257 subclass 237]  237           Subclass 237 indent level is 4 Charge-presetting/linear input type (e.g., fill and spill)
[List of Patents for class 257 subclass 238]  238           Subclass 238 indent level is 3 Input signal responsive to signal charge in charge transfer device (e.g., regeneration or feedback)
[List of Patents for class 257 subclass 239]  239           Subclass 239 indent level is 2 Signal charge detection type (e.g., floating diffusion or floating gate non-destructive output)
[List of Patents for class 257 subclass 240]  240           Subclass 240 indent level is 2 Changing width or direction of channel (e.g., meandering channel)
[List of Patents for class 257 subclass 241]  241           Subclass 241 indent level is 2 Multiple channels (e.g., converging or diverging or parallel channels)
[List of Patents for class 257 subclass 242]  242           Subclass 242 indent level is 2 Vertical charge transfer
[List of Patents for class 257 subclass 243]  243           Subclass 243 indent level is 2 Channel confinement
[List of Patents for class 257 subclass 244]  244           Subclass 244 indent level is 2 Comprising a groove
[List of Patents for class 257 subclass 245]  245           Subclass 245 indent level is 2 Structure for applying electric field into device (e.g., resistive electrode, acoustic traveling wave in channel)
[List of Patents for class 257 subclass 246]  246           Subclass 246 indent level is 3 Phase structure (e.g., doping variations to provide asymmetry for 2-phase operation; more than four phases or "electrode per bit")
[List of Patents for class 257 subclass 247]  247           Subclass 247 indent level is 4 Uniphase or virtual phase structure
[List of Patents for class 257 subclass 248]  248           Subclass 248 indent level is 4 2-phase
[List of Patents for class 257 subclass 249]  249           Subclass 249 indent level is 3 Electrode structures or materials
[List of Patents for class 257 subclass 250]  250           Subclass 250 indent level is 4 Plural gate levels
[List of Patents for class 257 subclass 251]  251           Subclass 251 indent level is 2 Substantially incomplete signal charge transfer (e.g., bucket brigade)
[List of Patents for class 257 subclass 252]  252           Subclass 252 indent level is 1 Responsive to non-optical, non-electrical signal
[List of Patents for class 257 subclass 253]  253           Subclass 253 indent level is 2 Chemical (e.g., ISFET, CHEMFET)
[List of Patents for class 257 subclass 254]  254           Subclass 254 indent level is 2 Physical deformation (e.g., strain sensor, acoustic wave detector)
[List of Patents for class 257 subclass 255]  255           Subclass 255 indent level is 1 With current flow along specified crystal axis (e.g., axis of maximum carrier mobility)
[List of Patents for class 257 subclass 256]  256           Subclass 256 indent level is 1 Junction field effect transistor (unipolar transistor)
[List of Patents for class 257 subclass 257]  257           Subclass 257 indent level is 2 Light responsive or combined with light responsive device
[List of Patents for class 257 subclass 258]  258           Subclass 258 indent level is 3 In imaging array
[List of Patents for class 257 subclass 259]  259           Subclass 259 indent level is 2 Elongated active region acts as transmission line or distributed active element (e.g., "transmission line" field effect transistor)
[List of Patents for class 257 subclass 260]  260           Subclass 260 indent level is 2 Same channel controlled by both junction and insulated gate electrodes, or by both Schottky barrier and pn junction gates (e.g., "taper isolated" memory cell)
[List of Patents for class 257 subclass 261]  261           Subclass 261 indent level is 2 Junction gate region free of direct electrical connection (e.g., floating junction gate memory cell structure)
[List of Patents for class 257 subclass 262]  262           Subclass 262 indent level is 2 Combined with insulated gate field effect transistor (IGFET)
[List of Patents for class 257 subclass 263]  263           Subclass 263 indent level is 2 Vertical controlled current path
[List of Patents for class 257 subclass 264]  264           Subclass 264 indent level is 3 Enhancement mode or with high resistivity channel (e.g., doping of 10 15 cm -3 or less)
[List of Patents for class 257 subclass 265]  265           Subclass 265 indent level is 3 In integrated circuit
[List of Patents for class 257 subclass 266]  266           Subclass 266 indent level is 3 With multiple parallel current paths (e.g., grid gate)
[List of Patents for class 257 subclass 267]  267           Subclass 267 indent level is 4 With Schottky barrier gate
[List of Patents for class 257 subclass 268]  268           Subclass 268 indent level is 2 Enhancement mode
[List of Patents for class 257 subclass 269]  269           Subclass 269 indent level is 3 With means to adjust barrier height (e.g., doping profile)
[List of Patents for class 257 subclass 270]  270           Subclass 270 indent level is 2 Plural, separately connected, gates control same channel region
[List of Patents for class 257 subclass 271]  271           Subclass 271 indent level is 2 Load element or constant current source (e.g., with source to gate connection)
[List of Patents for class 257 subclass 272]  272           Subclass 272 indent level is 2 Junction field effect transistor in integrated circuit
[List of Patents for class 257 subclass 273]  273           Subclass 273 indent level is 3 With bipolar device
[List of Patents for class 257 subclass 274]  274           Subclass 274 indent level is 3 Complementary junction field effect transistors
[List of Patents for class 257 subclass 275]  275           Subclass 275 indent level is 3 Microwave integrated circuit (e.g., microstrip type)
[List of Patents for class 257 subclass 276]  276           Subclass 276 indent level is 4 With contact or heat sink extending through hole in semiconductor substrate, or with electrode suspended over substrate (e.g., air bridge)
[List of Patents for class 257 subclass 277]  277           Subclass 277 indent level is 4 With capacitive or inductive elements
[List of Patents for class 257 subclass 278]  278           Subclass 278 indent level is 3 With devices vertically spaced in different layers of semiconductor material (e.g., "3-dimensional" integrated circuit)
[List of Patents for class 257 subclass 279]  279           Subclass 279 indent level is 2 Pn junction gate in compound semiconductor material (e.g., GaAs)
[List of Patents for class 257 subclass 280]  280           Subclass 280 indent level is 2 With Schottky gate
[List of Patents for class 257 subclass 281]  281           Subclass 281 indent level is 3 Schottky gate to silicon semiconductor
[List of Patents for class 257 subclass 282]  282           Subclass 282 indent level is 3 Gate closely aligned to source region
[List of Patents for class 257 subclass 283]  283           Subclass 283 indent level is 4 With groove or overhang for alignment
[List of Patents for class 257 subclass 284]  284           Subclass 284 indent level is 3 Schottky gate in groove
[List of Patents for class 257 subclass 285]  285           Subclass 285 indent level is 2 With profiled channel dopant concentration or profiled gate region dopant concentration (e.g., maximum dopant concentration below surface)
[List of Patents for class 257 subclass 286]  286           Subclass 286 indent level is 2 With non-uniform channel thickness or width
[List of Patents for class 257 subclass 287]  287           Subclass 287 indent level is 2 With multiple channels or channel segments connected in parallel, or with channel much wider than length between source and drain (e.g., power JFET)
[List of Patents for class 257 subclass 288]  288           Subclass 288 indent level is 1 Having insulated electrode (e.g., MOSFET, MOS diode)
[List of Patents for class 257 subclass 289]  289           Subclass 289 indent level is 2 Significant semiconductor chemical compound in bulk crystal (e.g., GaAs)
[List of Patents for class 257 subclass 290]  290           Subclass 290 indent level is 2 Light responsive or combined with light responsive device
[List of Patents for class 257 subclass 291]  291           Subclass 291 indent level is 3 Imaging array
[List of Patents for class 257 subclass 292]  292           Subclass 292 indent level is 4 Photodiodes accessed by FETs
[List of Patents for class 257 subclass 293]  293           Subclass 293 indent level is 4 Photoresistors accessed by FETs, or photodetectors separate from FET chip
[List of Patents for class 257 subclass 294]  294           Subclass 294 indent level is 4 With shield, filter, or lens
[List of Patents for class 257 subclass 295]  295           Subclass 295 indent level is 2 With ferroelectric material layer
[List of Patents for class 257 subclass 296]  296           Subclass 296 indent level is 2 Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell)
[List of Patents for class 257 subclass 297]  297           Subclass 297 indent level is 3 With means for preventing charge leakage due to minority carrier generation (e.g., alpha generated soft error protection or "dark current" leakage protection)
[List of Patents for class 257 subclass 298]  298           Subclass 298 indent level is 3 Capacitor for signal storage in combination with non-volatile storage means
[List of Patents for class 257 subclass 299]  299           Subclass 299 indent level is 3 Structure configured for voltage converter (e.g., charge pump, substrate bias generator)
[List of Patents for class 257 subclass 300]  300           Subclass 300 indent level is 3 Capacitor coupled to, or forms gate of, insulated gate field effect transistor (e.g., non-destructive readout dynamic memory cell structure)
[List of Patents for class 257 subclass 301]  301           Subclass 301 indent level is 3 Capacitor in trench
[List of Patents for class 257 subclass 302]  302           Subclass 302 indent level is 4 Vertical transistor
[List of Patents for class 257 subclass 303]  303           Subclass 303 indent level is 4 Stacked capacitor
[List of Patents for class 257 subclass 304]  304           Subclass 304 indent level is 4 Storage node isolated by dielectric from semiconductor substrate
[List of Patents for class 257 subclass 305]  305           Subclass 305 indent level is 4 With means to insulate adjacent storage nodes (e.g., channel stops or field oxide)
[List of Patents for class 257 subclass 306]  306           Subclass 306 indent level is 3 Stacked capacitor
[List of Patents for class 257 subclass 307]  307           Subclass 307 indent level is 4 Parallel interleaved capacitor electrode pairs (e.g., interdigitized)
[List of Patents for class 257 subclass 308]  308           Subclass 308 indent level is 5 With capacitor electrodes connection portion located centrally thereof (e.g., fin electrodes with central post)
[List of Patents for class 257 subclass 309]  309           Subclass 309 indent level is 4 With increased effective electrode surface area (e.g., tortuous path, corrugated, or textured electrodes)
[List of Patents for class 257 subclass 310]  310           Subclass 310 indent level is 3 With high dielectric constant insulator (e.g., Ta 2 O 5 )
[List of Patents for class 257 subclass 311]  311           Subclass 311 indent level is 3 Storage Node isolated by dielectric from semiconductor substrate
[List of Patents for class 257 subclass 312]  312           Subclass 312 indent level is 3 Voltage variable capacitor (i. e., capacitance varies with applied voltage)
[List of Patents for class 257 subclass 313]  313           Subclass 313 indent level is 3 Inversion layer capacitor
[List of Patents for class 257 subclass 314]  314           Subclass 314 indent level is 2 Variable threshold (e.g., floating gate memory device)
[List of Patents for class 257 subclass 315]  315           Subclass 315 indent level is 3 With floating gate electrode
[List of Patents for class 257 subclass 316]  316           Subclass 316 indent level is 4 With additional contacted control electrode
[List of Patents for class 257 subclass 317]  317           Subclass 317 indent level is 5 With irregularities on electrode to facilitate charging or discharging of floating electrode
[List of Patents for class 257 subclass 318]  318           Subclass 318 indent level is 5 Additional control electrode is doped region in semiconductor substrate
[List of Patents for class 257 subclass 319]  319           Subclass 319 indent level is 5 Plural additional contacted control electrodes
[List of Patents for class 257 subclass 320]  320           Subclass 320 indent level is 6 Separate control electrodes for charging and for discharging floating electrode
[List of Patents for class 257 subclass 321]  321           Subclass 321 indent level is 5 With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling
[List of Patents for class 257 subclass 322]  322           Subclass 322 indent level is 5 With charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction)
[List of Patents for class 257 subclass 323]  323           Subclass 323 indent level is 4 With means to facilitate light erasure
[List of Patents for class 257 subclass 324]  324           Subclass 324 indent level is 3 Multiple insulator layers (e.g., MNOS structure)
[List of Patents for class 257 subclass 325]  325           Subclass 325 indent level is 4 Non-homogeneous composition insulator layer (e.g., graded composition layer or layer with inclusions)
[List of Patents for class 257 subclass 326]  326           Subclass 326 indent level is 4 With additional, non-memory control electrode or channel portion (e.g., accessing field effect transistor structure)
[List of Patents for class 257 subclass 327]  327           Subclass 327 indent level is 2 Short channel insulated gate field effect transistor
[List of Patents for class 257 subclass 328]  328           Subclass 328 indent level is 3 Vertical channel or double diffused insulated gate field effect device provided with means to protect against excess voltage (e.g., gate protection diode)
[List of Patents for class 257 subclass 329]  329           Subclass 329 indent level is 3 Gate controls vertical charge flow portion of channel (e.g., VMOS device)
[List of Patents for class 257 subclass 330]  330           Subclass 330 indent level is 4 Gate electrode in groove
[List of Patents for class 257 subclass 331]  331           Subclass 331 indent level is 5 Plural gate electrodes or grid shaped gate electrode
[List of Patents for class 257 subclass 332]  332           Subclass 332 indent level is 5 Gate electrode self-aligned with groove
[List of Patents for class 257 subclass 333]  333           Subclass 333 indent level is 5 With thick insulator to reduce gate capacitance in non-channel areas (e.g., thick oxide over source or drain region)
[List of Patents for class 257 subclass 334]  334           Subclass 334 indent level is 5 In integrated circuit structure
[List of Patents for class 257 subclass 335]  335           Subclass 335 indent level is 3 Active channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused device, DMOS transistor)
[List of Patents for class 257 subclass 336]  336           Subclass 336 indent level is 4 With lightly doped portion of drain region adjacent channel (e.g., LDD structure)
[List of Patents for class 257 subclass 337]  337           Subclass 337 indent level is 4 In integrated circuit structure
[List of Patents for class 257 subclass 338]  338           Subclass 338 indent level is 5 With complementary field effect transistor
[List of Patents for class 257 subclass 339]  339           Subclass 339 indent level is 4 With means to increase breakdown voltage
[List of Patents for class 257 subclass 340]  340           Subclass 340 indent level is 4 With means (other than self-alignment of the gate electrode) to decrease gate capacitance (e.g., shield electrode)
[List of Patents for class 257 subclass 341]  341           Subclass 341 indent level is 4 Plural sections connected in parallel (e.g., power MOSFET)
[List of Patents for class 257 subclass 342]  342           Subclass 342 indent level is 5 With means to reduce ON resistance
[List of Patents for class 257 subclass 343]  343           Subclass 343 indent level is 4 All contacts on same surface (e.g., lateral structure)
[List of Patents for class 257 subclass 344]  344           Subclass 344 indent level is 3 With lightly doped portion of drain region adjacent channel (e.g., LDD structure)
[List of Patents for class 257 subclass 345]  345           Subclass 345 indent level is 3 With means to prevent sub-surface currents, or with non-uniform channel doping
[List of Patents for class 257 subclass 346]  346           Subclass 346 indent level is 3 Gate electrode overlaps the source or drain by no more than depth of source or drain (e.g., self-aligned gate)
[List of Patents for class 257 subclass 347]  347           Subclass 347 indent level is 2 Single crystal semiconductor layer on insulating substrate (SOI)
[List of Patents for class 257 subclass 348]  348           Subclass 348 indent level is 3 Depletion mode field effect transistor
[List of Patents for class 257 subclass 349]  349           Subclass 349 indent level is 3 With means (e.g., a buried channel stop layer) to prevent leakage current along the interface of the semiconductor layer and the insulating substrate
[List of Patents for class 257 subclass 350]  350           Subclass 350 indent level is 3 Insulated electrode device is combined with diverse type device (e.g., complementary MOSFETs, FET with resistor, etc.)
[List of Patents for class 257 subclass 351]  351           Subclass 351 indent level is 4 Complementary field effect transistor structures only (i.e., not including bipolar transistors, resistors, or other components)
[List of Patents for class 257 subclass 352]  352           Subclass 352 indent level is 3 Substrate is single crystal insulator (e.g., sapphire or spinel)
[List of Patents for class 257 subclass 353]  353           Subclass 353 indent level is 4 Single crystal islands of semiconductor layer containing only one active device
[List of Patents for class 257 subclass 354]  354           Subclass 354 indent level is 5 Including means to eliminate island edge effects (e.g., insulating filling between islands, or ions in island edges)
[List of Patents for class 257 subclass 355]  355           Subclass 355 indent level is 2 With overvoltage protective means
[List of Patents for class 257 subclass 356]  356           Subclass 356 indent level is 3 For protecting against gate insulator breakdown
[List of Patents for class 257 subclass 357]  357           Subclass 357 indent level is 4 In complementary field effect transistor integrated circuit
[List of Patents for class 257 subclass 358]  358           Subclass 358 indent level is 5 Including resistor element
[List of Patents for class 257 subclass 359]  359           Subclass 359 indent level is 6 As thin film structure (e.g., polysilicon resistor)
[List of Patents for class 257 subclass 360]  360           Subclass 360 indent level is 4 Protection device includes insulated gate transistor structure (e.g., combined with resistor element)
[List of Patents for class 257 subclass 361]  361           Subclass 361 indent level is 5 For operation as bipolar or punchthrough element
[List of Patents for class 257 subclass 362]  362           Subclass 362 indent level is 4 Punchthrough or bipolar element
[List of Patents for class 257 subclass 363]  363           Subclass 363 indent level is 4 Including resistor element
[List of Patents for class 257 subclass 364]  364           Subclass 364 indent level is 2 With resistive gate electrode
[List of Patents for class 257 subclass 365]  365           Subclass 365 indent level is 2 With plural, separately connected, gate electrodes in same device
[List of Patents for class 257 subclass 366]  366           Subclass 366 indent level is 3 Overlapping gate electrodes
[List of Patents for class 257 subclass 367]  367           Subclass 367 indent level is 2 Insulated gate controlled breakdown of pn junction (e.g., field plate diode)
[List of Patents for class 257 subclass 368]  368           Subclass 368 indent level is 2 Insulated gate field effect transistor in integrated circuit
[List of Patents for class 257 subclass 369]  369           Subclass 369 indent level is 3 Complementary insulated gate field effect transistors
[List of Patents for class 257 subclass 370]  370           Subclass 370 indent level is 4 Combined with bipolar transistor
[List of Patents for class 257 subclass 371]  371           Subclass 371 indent level is 4 Complementary transistors in wells of opposite conductivity types more heavily doped than the substrate region in which they are formed, e.g., twin wells
[List of Patents for class 257 subclass 372]  372           Subclass 372 indent level is 4 With means to prevent latchup or parasitic conduction channels
[List of Patents for class 257 subclass 373]  373           Subclass 373 indent level is 4 With pn junction to collect injected minority carriers to prevent parasitic bipolar transistor action
[List of Patents for class 257 subclass 374]  374           Subclass 374 indent level is 5 Dielectric isolation means (e.g., dielectric layer in vertical grooves)
[List of Patents for class 257 subclass 375]  375           Subclass 375 indent level is 5 With means to reduce substrate spreading resistance (e.g., heavily doped substrate)
[List of Patents for class 257 subclass 376]  376           Subclass 376 indent level is 5 With barrier region of reduced minority carrier lifetime (e.g., heavily doped P+ region to reduce electron minority carrier lifetime, or containing deep level impurity or crystal damage), or with region of high threshold voltage (e.g., heavily doped channel stop region)
[List of Patents for class 257 subclass 377]  377           Subclass 377 indent level is 4 With polysilicon interconnections to source or drain regions (e.g., polysilicon laminated with silicide)
[List of Patents for class 257 subclass 378]  378           Subclass 378 indent level is 3 Combined with bipolar transistor
[List of Patents for class 257 subclass 379]  379           Subclass 379 indent level is 3 Combined with passive components (e.g., resistors)
[List of Patents for class 257 subclass 380]  380           Subclass 380 indent level is 4 Polysilicon resistor
[List of Patents for class 257 subclass 381]  381           Subclass 381 indent level is 4 With multiple levels of polycrystalline silicon
[List of Patents for class 257 subclass 382]  382           Subclass 382 indent level is 3 With contact to source or drain region of refractory material (e.g., polysilicon, tungsten, or silicide)
[List of Patents for class 257 subclass 383]  383           Subclass 383 indent level is 4 Contact of refractory or platinum group metal (e.g., molybdenum, tungsten, or titanium)
[List of Patents for class 257 subclass 384]  384           Subclass 384 indent level is 4 Including silicide
[List of Patents for class 257 subclass 385]  385           Subclass 385 indent level is 4 Multiple polysilicon layers
[List of Patents for class 257 subclass 386]  386           Subclass 386 indent level is 3 With means to reduce parasitic capacitance
[List of Patents for class 257 subclass 387]  387           Subclass 387 indent level is 4 Gate electrode overlaps at least one of source or drain by no more than depth of source or drain (e.g., self-aligned gate)
[List of Patents for class 257 subclass 388]  388           Subclass 388 indent level is 5 Gate electrode consists of refractory or platinum group metal or silicide
[List of Patents for class 257 subclass 389]  389           Subclass 389 indent level is 4 With thick insulator over source or drain region
[List of Patents for class 257 subclass 390]  390           Subclass 390 indent level is 3 Matrix or array of field effect transistors (e.g., array of FETs only some of which are completed, or structure for mask programmed read-only memory (ROM))
[List of Patents for class 257 subclass 391]  391           Subclass 391 indent level is 4 Selected groups of complete field effect devices having different threshold voltages (e.g., different channel dopant concentrations)
[List of Patents for class 257 subclass 392]  392           Subclass 392 indent level is 3 Insulated gate field effect transistors of different threshold voltages in same integrated circuit (e.g., enhancement and depletion mode)
[List of Patents for class 257 subclass 393]  393           Subclass 393 indent level is 3 Insulated gate field effect transistor adapted to function as load element for switching insulated gate field effect transistor
[List of Patents for class 257 subclass 394]  394           Subclass 394 indent level is 3 With means to prevent parasitic conduction channels
[List of Patents for class 257 subclass 395]  395           Subclass 395 indent level is 4 Thick insulator portion
[List of Patents for class 257 subclass 396]  396           Subclass 396 indent level is 5 Recessed into semiconductor surface
[List of Patents for class 257 subclass 397]  397           Subclass 397 indent level is 6 In vertical-walled groove
[List of Patents for class 257 subclass 398]  398           Subclass 398 indent level is 6 Combined with heavily doped channel stop portion
[List of Patents for class 257 subclass 399]  399           Subclass 399 indent level is 5 Combined with heavily doped channel stop portion
[List of Patents for class 257 subclass 400]  400           Subclass 400 indent level is 4 With heavily doped channel stop portion
[List of Patents for class 257 subclass 401]  401           Subclass 401 indent level is 3 With specified physical layout (e.g., ring gate, source/drain regions shared between plural FETs, plural sections connected in parallel to form power MOSFET)
[List of Patents for class 257 subclass 402]  402           Subclass 402 indent level is 2 With permanent threshold adjustment (e.g., depletion mode)
[List of Patents for class 257 subclass 403]  403           Subclass 403 indent level is 3 With channel conductivity dopant same type as that of source and drain
[List of Patents for class 257 subclass 404]  404           Subclass 404 indent level is 4 Non-uniform channel doping
[List of Patents for class 257 subclass 405]  405           Subclass 405 indent level is 3 With gate insulator containing specified permanent charge
[List of Patents for class 257 subclass 406]  406           Subclass 406 indent level is 4 Plural gate insulator layers
[List of Patents for class 257 subclass 407]  407           Subclass 407 indent level is 3 With gate electrode of controlled workfunction material (e.g., low workfunction gate material)
[List of Patents for class 257 subclass 408]  408           Subclass 408 indent level is 2 Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device)
[List of Patents for class 257 subclass 409]  409           Subclass 409 indent level is 2 With means to increase breakdown voltage (e.g., field shield electrode, guard ring, etc.)
[List of Patents for class 257 subclass 410]  410           Subclass 410 indent level is 2 Gate insulator includes material (including air or vacuum) other than SiO 2
[List of Patents for class 257 subclass 411]  411           Subclass 411 indent level is 3 Composite or layered gate insulator (e.g., mixture such as silicon oxynitride)
[List of Patents for class 257 subclass 412]  412           Subclass 412 indent level is 2 Gate electrode of refractory material (e.g., polysilicon or a silicide of a refractory or platinum group metal)
[List of Patents for class 257 subclass 413]  413           Subclass 413 indent level is 3 Polysilicon laminated with silicide
[List of Patents for class 257 subclass 414]  414           RESPONSIVE TO NON-ELECTRICAL SIGNAL (E.G., CHEMICAL, STRESS, LIGHT, OR MAGNETIC FIELD SENSORS)
[List of Patents for class 257 subclass 415]  415           Subclass 415 indent level is 1 Physical deformation
[List of Patents for class 257 subclass 416]  416           Subclass 416 indent level is 2 Acoustic wave
[List of Patents for class 257 subclass 417]  417           Subclass 417 indent level is 2 Strain sensors
[List of Patents for class 257 subclass 418]  418           Subclass 418 indent level is 3 With means to concentrate stress
[List of Patents for class 257 subclass 419]  419           Subclass 419 indent level is 4 With thinned central active portion of semiconductor surrounded by thick insensitive portion (e.g. diaphragm type strain gauge)
[List of Patents for class 257 subclass 420]  420           Subclass 420 indent level is 2 Means to reduce sensitivity to physical deformation
[List of Patents for class 257 subclass 421]  421           Subclass 421 indent level is 1 Magnetic field
[List of Patents for class 257 subclass 422]  422           Subclass 422 indent level is 2 With magnetic field directing means (e.g., shield, pole piece, etc.)
[List of Patents for class 257 subclass 423]  423           Subclass 423 indent level is 2 Bipolar transistor magnetic field sensor (e.g., lateral bipolar transistor)
[List of Patents for class 257 subclass 424]  424           Subclass 424 indent level is 2 Sensor with region of high carrier recombination (e.g., magnetodiode with carriers deflected to recombination region by magnetic field)
[List of Patents for class 257 subclass 425]  425           Subclass 425 indent level is 2 Magnetic field detector using compound semiconductor material (e.g., GaAs, InSb, etc.)
[List of Patents for class 257 subclass 426]  426           Subclass 426 indent level is 2 Differential output (e.g., with offset adjustment means or with means to reduce temperature sensitivity)
[List of Patents for class 257 subclass 427]  427           Subclass 427 indent level is 2 Magnetic field sensor in integrated circuit (e.g., in bipolar transistor integrated circuit)
[List of Patents for class 257 subclass 428]  428           Subclass 428 indent level is 1 Electromagnetic or particle radiation
[List of Patents for class 257 subclass 429]  429           Subclass 429 indent level is 2 Charged or elementary particles
[List of Patents for class 257 subclass 430]  430           Subclass 430 indent level is 3 With active region having effective impurity concentration less than 10 12 atoms/cm 3
[List of Patents for class 257 subclass 431]  431           Subclass 431 indent level is 2 Light
[List of Patents for class 257 subclass 432]  432           Subclass 432 indent level is 3 With optical element
[List of Patents for class 257 subclass 433]  433           Subclass 433 indent level is 3 With housing or encapsulation
[List of Patents for class 257 subclass 434]  434           Subclass 434 indent level is 4 With window means
[List of Patents for class 257 subclass 435]  435           Subclass 435 indent level is 3 With optical shield or mask means
[List of Patents for class 257 subclass 436]  436           Subclass 436 indent level is 3 With means for increasing light absorption (e.g., redirection of unabsorbed light)
[List of Patents for class 257 subclass 437]  437           Subclass 437 indent level is 4 Antireflection coating
[List of Patents for class 257 subclass 438]  438           Subclass 438 indent level is 3 Avalanche junction
[List of Patents for class 257 subclass 439]  439           Subclass 439 indent level is 3 Containing dopant adapted for photoionization
[List of Patents for class 257 subclass 440]  440           Subclass 440 indent level is 3 With different sensor portions responsive to different wavelengths (e.g., color imager)
[List of Patents for class 257 subclass 441]  441           Subclass 441 indent level is 3 Narrow band gap semiconductor (<<1eV) (e.g., PbSnTe)
[List of Patents for class 257 subclass 442]  442           Subclass 442 indent level is 4 II-VI compound semiconductor (e.g., HgCdTe)
[List of Patents for class 257 subclass 443]  443           Subclass 443 indent level is 3 Matrix or array (e.g., single line arrays)
[List of Patents for class 257 subclass 444]  444           Subclass 444 indent level is 4 Light sensor elements overlie active switching elements in integrated circuit (e.g., where the sensor elements are deposited on an integrated circuit)
[List of Patents for class 257 subclass 445]  445           Subclass 445 indent level is 4 With antiblooming means
[List of Patents for class 257 subclass 446]  446           Subclass 446 indent level is 4 With specific isolation means in integrated circuit
[List of Patents for class 257 subclass 447]  447           Subclass 447 indent level is 4 With backside illumination (e.g., having a thinned central area or a non-absorbing substrate)
[List of Patents for class 257 subclass 448]  448           Subclass 448 indent level is 4 With particular electrode configuration
[List of Patents for class 257 subclass 449]  449           Subclass 449 indent level is 3 Schottky barrier (e.g., a transparent Schottky metallic layer or a Schottky barrier containing at least one of indium or tin (e.g., SnO 2 , indium tin oxide))
[List of Patents for class 257 subclass 450]  450           Subclass 450 indent level is 4 With doping profile to adjust barrier height
[List of Patents for class 257 subclass 451]  451           Subclass 451 indent level is 4 Responsive to light having lower energy (i.e., longer wavelength) than forbidden band gap energy of semiconductor (e.g., by excitation of carriers from metal into semiconductor)
[List of Patents for class 257 subclass 452]  452           Subclass 452 indent level is 4 With edge protection, e.g., doped guard ring or mesa structure
[List of Patents for class 257 subclass 453]  453           Subclass 453 indent level is 4 With specified Schottky metallic layer
[List of Patents for class 257 subclass 454]  454           Subclass 454 indent level is 5 Schottky metallic layer is a silicide
[List of Patents for class 257 subclass 455]  455           Subclass 455 indent level is 6 Silicide of Platinum group metal
[List of Patents for class 257 subclass 456]  456           Subclass 456 indent level is 6 Silicide of refractory metal
[List of Patents for class 257 subclass 457]  457           Subclass 457 indent level is 4 With particular contact geometry (e.g., ring or grid)
[List of Patents for class 257 subclass 458]  458           Subclass 458 indent level is 3 PIN detector, including combinations with non-light responsive active devices
[List of Patents for class 257 subclass 459]  459           Subclass 459 indent level is 3 With particular contact geometry (e.g., ring or grid, or bonding pad arrangement)
[List of Patents for class 257 subclass 460]  460           Subclass 460 indent level is 3 With backside illumination (e.g., with a thinned central area or non-absorbing substrate)
[List of Patents for class 257 subclass 461]  461           Subclass 461 indent level is 3 Light responsive pn junction
[List of Patents for class 257 subclass 462]  462           Subclass 462 indent level is 4 Phototransistor
[List of Patents for class 257 subclass 463]  463           Subclass 463 indent level is 4 With particular doping concentration
[List of Patents for class 257 subclass 464]  464           Subclass 464 indent level is 4 With particular layer thickness (e.g., layer less than light absorption depth)
[List of Patents for class 257 subclass 465]  465           Subclass 465 indent level is 4 Geometric configuration of junction (e.g., fingers)
[List of Patents for class 257 subclass 466]  466           Subclass 466 indent level is 3 External physical configuration of semiconductor (e.g., mesas, grooves)
[List of Patents for class 257 subclass 467]  467           Subclass 467 indent level is 1 Temperature
[List of Patents for class 257 subclass 468]  468           Subclass 468 indent level is 2 Semiconductor device operated at cryogenic temperature
[List of Patents for class 257 subclass 469]  469           Subclass 469 indent level is 2 With means to reduce temperature sensitivity (e.g., reduction of temperature sensitivity of junction breakdown voltage by using a compensating element)
[List of Patents for class 257 subclass 470]  470           Subclass 470 indent level is 2 Pn junction adapted as temperature sensor
[List of Patents for class 257 subclass 471]  471           SCHOTTKY BARRIER
[List of Patents for class 257 subclass 472]  472           Subclass 472 indent level is 1 To compound semiconductor
[List of Patents for class 257 subclass 473]  473           Subclass 473 indent level is 2 With specified Schottky metal
[List of Patents for class 257 subclass 474]  474           Subclass 474 indent level is 1 As active junction in bipolar transistor (e.g., Schottky collector)
[List of Patents for class 257 subclass 475]  475           Subclass 475 indent level is 1 With doping profile to adjust barrier height
[List of Patents for class 257 subclass 476]  476           Subclass 476 indent level is 1 In integrated structure
[List of Patents for class 257 subclass 477]  477           Subclass 477 indent level is 2 With bipolar transistor
[List of Patents for class 257 subclass 478]  478           Subclass 478 indent level is 3 Plural Schottky barriers with different barrier heights
[List of Patents for class 257 subclass 479]  479           Subclass 479 indent level is 3 Connected across base-collector junction of transistor (e.g., Baker clamp)
[List of Patents for class 257 subclass 480]  480           Subclass 480 indent level is 1 In voltage variable capacitance diode
[List of Patents for class 257 subclass 481]  481           Subclass 481 indent level is 1 Avalanche diode (e.g., so-called "Zener" diode having breakdown voltage greater than 6 volts)
[List of Patents for class 257 subclass 482]  482           Subclass 482 indent level is 2 Microwave transit time device (e.g., IMPATT diode)
[List of Patents for class 257 subclass 483]  483           Subclass 483 indent level is 1 With means to prevent edge breakdown
[List of Patents for class 257 subclass 484]  484           Subclass 484 indent level is 2 Guard ring
[List of Patents for class 257 subclass 485]  485           Subclass 485 indent level is 1 Specified materials
[List of Patents for class 257 subclass 486]  486           Subclass 486 indent level is 2 Layered (e.g., a diffusion barrier material layer or a silicide layer or a precious metal layer)
[List of Patents for class 257 subclass 487]  487           WITH MEANS TO INCREASE BREAKDOWN VOLTAGE THRESHOLD
[List of Patents for class 257 subclass 488]  488           Subclass 488 indent level is 1 Field relief electrode
[List of Patents for class 257 subclass 489]  489           Subclass 489 indent level is 2 Resistive
[List of Patents for class 257 subclass 490]  490           Subclass 490 indent level is 2 Combined with floating pn junction guard region
[List of Patents for class 257 subclass 491]  491           Subclass 491 indent level is 1 In integrated circuit
[List of Patents for class 257 subclass 492]  492           Subclass 492 indent level is 2 With electric field controlling semiconductor layer having a low enough doping level in relationship to its thickness to be fully depleted prior to avalanche breakdown (e.g., RESURF devices)
[List of Patents for class 257 subclass 493]  493           Subclass 493 indent level is 1 With electric field controlling semiconductor layer having a low enough doping level in relationship to its thickness to be fully depleted prior to avalanche breakdown (e.g., RESURF devices)
[List of Patents for class 257 subclass 494]  494           Subclass 494 indent level is 1 Reverse-biased pn junction guard region
[List of Patents for class 257 subclass 495]  495           Subclass 495 indent level is 1 Floating pn junction guard region
[List of Patents for class 257 subclass 496]  496           Subclass 496 indent level is 1 With physical configuration of semiconductor surface to reduce electric field (e.g., reverse bevels, double bevels, stepped mesas, etc.)
[List of Patents for class 257 subclass 497]  497           PUNCHTHROUGH STRUCTURE DEVICE (E.G., PUNCHTHROUGH TRANSISTOR, CAMEL BARRIER DIODE)
[List of Patents for class 257 subclass 498]  498           Subclass 498 indent level is 1 Punchthrough region fully depleted at zero external applied bias voltage (e.g., camel barrier or planar doped barrier devices, or so-called "Bipolar SIT" devices)
[List of Patents for class 257 subclass 499]  499           INTEGRATED CIRCUIT STRUCTURE WITH ELECTRICALLY ISOLATED COMPONENTS
[List of Patents for class 257 subclass 500]  500           Subclass 500 indent level is 1 Including high voltage or high power devices isolated from low voltage or low power devices in the same integrated circuit
[List of Patents for class 257 subclass 501]  501           Subclass 501 indent level is 2 Including dielectric isolation means
[List of Patents for class 257 subclass 502]  502           Subclass 502 indent level is 2 High power or high voltage device extends completely through semiconductor substrate (e.g., backside collector contact)
[List of Patents for class 257 subclass 503]  503           Subclass 503 indent level is 1 With contact or metallization configuration to reduce parasitic coupling (e.g., separate ground pads for different parts of integrated circuit)
[List of Patents for class 257 subclass 504]  504           Subclass 504 indent level is 1 Including means for establishing a depletion region throughout a semiconductor layer for isolating devices in different portions of the layer (e.g., "JFET" isolation)
[List of Patents for class 257 subclass 505]  505           Subclass 505 indent level is 1 With polycrystalline semiconductor isolation region in direct contact with single crystal active semiconductor material
[List of Patents for class 257 subclass 506]  506           Subclass 506 indent level is 1 Including dielectric isolation means
[List of Patents for class 257 subclass 507]  507           Subclass 507 indent level is 2 With single crystal insulating substrate (e.g., sapphire)
[List of Patents for class 257 subclass 508]  508           Subclass 508 indent level is 2 With metallic conductor within isolating dielectric or between semiconductor and isolating dielectric (e.g., metal shield layer or internal connection layer)
[List of Patents for class 257 subclass 509]  509           Subclass 509 indent level is 2 Combined with pn junction isolation (e.g., isoplanar, LOCOS)
[List of Patents for class 257 subclass 510]  510           Subclass 510 indent level is 3 Dielectric in groove
[List of Patents for class 257 subclass 511]  511           Subclass 511 indent level is 4 With complementary (npn and pnp) bipolar transistor structures
[List of Patents for class 257 subclass 512]  512           Subclass 512 indent level is 5 Complementary devices share common active region (e.g., integrated injection logic, I 2 L)
[List of Patents for class 257 subclass 513]  513           Subclass 513 indent level is 4 Vertical walled groove
[List of Patents for class 257 subclass 514]  514           Subclass 514 indent level is 5 With active junction abutting groove (e.g., "walled emitter")
[List of Patents for class 257 subclass 515]  515           Subclass 515 indent level is 4 With active junction abutting groove (e.g., "walled emitter")
[List of Patents for class 257 subclass 516]  516           Subclass 516 indent level is 4 With passive component (e.g., resistor, capacitor, etc.)
[List of Patents for class 257 subclass 517]  517           Subclass 517 indent level is 4 With bipolar transistor structure
[List of Patents for class 257 subclass 518]  518           Subclass 518 indent level is 5 With polycrystalline connecting region (e.g., polysilicon base contact)
[List of Patents for class 257 subclass 519]  519           Subclass 519 indent level is 4 Including heavily doped channel stop region adjacent groove
[List of Patents for class 257 subclass 520]  520           Subclass 520 indent level is 4 Conductive filling in dielectric-lined groove (e.g., polysilicon backfill)
[List of Patents for class 257 subclass 521]  521           Subclass 521 indent level is 4 Sides of grooves along major crystal planes (e.g., (111), (100) planes, etc.)
[List of Patents for class 257 subclass 522]  522           Subclass 522 indent level is 2 Air isolation (e.g., beam lead supported semiconductor islands)
[List of Patents for class 257 subclass 523]  523           Subclass 523 indent level is 2 Isolation by region of intrinsic (undoped) semiconductor material (e.g., including region physically damaged by proton bombardment)
[List of Patents for class 257 subclass 524]  524           Subclass 524 indent level is 2 Full dielectric isolation with polycrystalline semiconductor substrate
[List of Patents for class 257 subclass 525]  525           Subclass 525 indent level is 3 With complementary (npn and pnp) bipolar transistor structures
[List of Patents for class 257 subclass 526]  526           Subclass 526 indent level is 2 With bipolar transistor structure
[List of Patents for class 257 subclass 527]  527           Subclass 527 indent level is 3 Sides of isolated semiconductor islands along major crystal planes (e.g., (111), (100) planes, etc.)
[List of Patents for class 257 subclass 528]  528           Subclass 528 indent level is 1 Passive components in ICs
[List of Patents for class 257 subclass 529]  529           Subclass 529 indent level is 2 Including programmable passive component (e.g., fuse)
[List of Patents for class 257 subclass 530]  530           Subclass 530 indent level is 3 Anti-fuse
[List of Patents for class 257 subclass 531]  531           Subclass 531 indent level is 2 Including inductive element
[List of Patents for class 257 subclass 532]  532           Subclass 532 indent level is 2 Including capacitor component
[List of Patents for class 257 subclass 533]  533           Subclass 533 indent level is 3 Combined with resistor to form RC filter structure
[List of Patents for class 257 subclass 534]  534           Subclass 534 indent level is 3 With means to increase surface area (e.g., grooves, ridges, etc.)
[List of Patents for class 257 subclass 535]  535           Subclass 535 indent level is 3 Both terminals of capacitor isolated from substrate
[List of Patents for class 257 subclass 536]  536           Subclass 536 indent level is 2 Including resistive element
[List of Patents for class 257 subclass 537]  537           Subclass 537 indent level is 3 Using specific resistive material
[List of Patents for class 257 subclass 538]  538           Subclass 538 indent level is 4 Polycrystalline silicon (doped or undoped)
[List of Patents for class 257 subclass 539]  539           Subclass 539 indent level is 3 Combined with bipolar transistor
[List of Patents for class 257 subclass 540]  540           Subclass 540 indent level is 4 With compensation for non-linearity (e.g., dynamic isolation pocket bias)
[List of Patents for class 257 subclass 541]  541           Subclass 541 indent level is 4 Pinch resistor
[List of Patents for class 257 subclass 542]  542           Subclass 542 indent level is 4 Resistor has same doping as emitter or collector of bipolar transistor
[List of Patents for class 257 subclass 543]  543           Subclass 543 indent level is 4 Lightly doped junction isolated resistor (e.g., ion implanted resistor)
[List of Patents for class 257 subclass 544]  544           Subclass 544 indent level is 1 With pn junction isolation
[List of Patents for class 257 subclass 545]  545           Subclass 545 indent level is 2 With means to control isolation junction capacitance (e.g., lightly doped layer at isolation junction to increase depletion layer width)
[List of Patents for class 257 subclass 546]  546           Subclass 546 indent level is 2 With structural means to protect against excess or reversed polarity voltage
[List of Patents for class 257 subclass 547]  547           Subclass 547 indent level is 2 With structural means to control parasitic transistor action or leakage current
[List of Patents for class 257 subclass 548]  548           Subclass 548 indent level is 2 At least three regions of alternating conductivity types with dopant concentration gradients decreasing from surface of semiconductor (e.g., "triple-diffused" integrated circuit)
[List of Patents for class 257 subclass 549]  549           Subclass 549 indent level is 2 With substrate and lightly doped surface layer of same conductivity type, separated by subsurface heavily doped region of opposite conductivity type (e.g., "collector diffused isolation" integrated circuit)
[List of Patents for class 257 subclass 550]  550           Subclass 550 indent level is 2 With lightly doped surface layer of one conductivity type on substrate of opposite conductivity type, having plural heavily doped portions of the one conductivity type between the layer and substrate, different ones of the heavily doped portions having differing depths or physical extent
[List of Patents for class 257 subclass 551]  551           Subclass 551 indent level is 2 Including voltage reference element (e.g., avalanche diode, so-called "Zener diode" with breakdown voltage greater than 6 volts or with positive temperature coefficient of breakdown voltage)
[List of Patents for class 257 subclass 552]  552           Subclass 552 indent level is 2 With bipolar transistor structure
[List of Patents for class 257 subclass 553]  553           Subclass 553 indent level is 3 Transistors of same conductivity type (e.g., npn) having different current gain or different operating voltage characteristics
[List of Patents for class 257 subclass 554]  554           Subclass 554 indent level is 3 With connecting region made of polycrystalline semiconductor material (e.g., polysilicon base contact)
[List of Patents for class 257 subclass 555]  555           Subclass 555 indent level is 3 Complementary bipolar transistor structures (e.g., integrated injection logic, I 2 L)
[List of Patents for class 257 subclass 556]  556           Subclass 556 indent level is 4 Including lateral bipolar transistor structure
[List of Patents for class 257 subclass 557]  557           Subclass 557 indent level is 1 Lateral bipolar transistor structure
[List of Patents for class 257 subclass 558]  558           Subclass 558 indent level is 2 With base region doping concentration step or gradient or with means to increase current gain
[List of Patents for class 257 subclass 559]  559           Subclass 559 indent level is 2 With active region formed along groove or exposed edge in semiconductor
[List of Patents for class 257 subclass 560]  560           Subclass 560 indent level is 2 With multiple collectors or emitters
[List of Patents for class 257 subclass 561]  561           Subclass 561 indent level is 3 With different emitter to collector spacings or facing areas
[List of Patents for class 257 subclass 562]  562           Subclass 562 indent level is 3 With auxiliary collector/re-emitter between emitter and output collector (e.g., "Current Hogging Logic" device)
[List of Patents for class 257 subclass 563]  563           Subclass 563 indent level is 1 With multiple separately connected emitter, collector, or base regions in same transistor structure
[List of Patents for class 257 subclass 564]  564           Subclass 564 indent level is 2 Multiple base or collector regions
[List of Patents for class 257 subclass 565]  565           BIPOLAR TRANSISTOR STRUCTURE
[List of Patents for class 257 subclass 566]  566           Subclass 566 indent level is 1 Plural non-isolated transistor structures in same structure
[List of Patents for class 257 subclass 567]  567           Subclass 567 indent level is 2 Darlington configuration (i.e., emitter to collector current of input transistor supplied to base region of output transistor)
[List of Patents for class 257 subclass 568]  568           Subclass 568 indent level is 3 More than two Darlington-connected transistors
[List of Patents for class 257 subclass 569]  569           Subclass 569 indent level is 3 Complementary Darlington-connected transistors
[List of Patents for class 257 subclass 570]  570           Subclass 570 indent level is 3 With active components in addition to Darlington transistors (e.g., antisaturation diode, bleeder diode connected antiparallel to input transistor base-emitter junction, etc.)
[List of Patents for class 257 subclass 571]  571           Subclass 571 indent level is 3 Non-planar structure (e.g., mesa emitter, or having a groove to define resistor)
[List of Patents for class 257 subclass 572]  572           Subclass 572 indent level is 3 With resistance means connected between transistor base regions
[List of Patents for class 257 subclass 573]  573           Subclass 573 indent level is 3 With housing or contact structure or configuration
[List of Patents for class 257 subclass 574]  574           Subclass 574 indent level is 2 Complementary transistors share common active region (e.g., integrated injection logic, I 2 L)
[List of Patents for class 257 subclass 575]  575           Subclass 575 indent level is 3 Including lateral bipolar transistor structure
[List of Patents for class 257 subclass 576]  576           Subclass 576 indent level is 4 With contacts of refractory material (e.g., polysilicon, silicide of refractory or platinum group metal)
[List of Patents for class 257 subclass 577]  577           Subclass 577 indent level is 1 Including additional component in same, non-isolated structure (e.g., transistor with diode, transistor with resistor, etc.)
[List of Patents for class 257 subclass 578]  578           Subclass 578 indent level is 1 With enlarged emitter area (e.g., power device)
[List of Patents for class 257 subclass 579]  579           Subclass 579 indent level is 2 With separate emitter areas connected in parallel
[List of Patents for class 257 subclass 580]  580           Subclass 580 indent level is 3 With current ballasting means (e.g., emitter ballasting resistors or base current ballasting means)
[List of Patents for class 257 subclass 581]  581           Subclass 581 indent level is 4 Thin film ballasting means (e.g., polysilicon resistor)
[List of Patents for class 257 subclass 582]  582           Subclass 582 indent level is 2 With current ballasting means (e.g., emitter ballasting resistors or base current ballasting resistors)
[List of Patents for class 257 subclass 583]  583           Subclass 583 indent level is 2 With means to reduce transistor action in selected portions of transistor (e.g., heavy base region doping under central web of emitter to prevent secondary breakdown)
[List of Patents for class 257 subclass 584]  584           Subclass 584 indent level is 2 With housing or contact (i.e., electrode) means
[List of Patents for class 257 subclass 585]  585           Subclass 585 indent level is 1 With means to increase inverse gain
[List of Patents for class 257 subclass 586]  586           Subclass 586 indent level is 1 With non-planar semiconductor surface (e.g., groove, mesa, bevel, etc.)
[List of Patents for class 257 subclass 587]  587           Subclass 587 indent level is 1 With specified electrode means
[List of Patents for class 257 subclass 588]  588           Subclass 588 indent level is 2 Including polycrystalline semiconductor as connection
[List of Patents for class 257 subclass 589]  589           Subclass 589 indent level is 1 Avalanche transistor
[List of Patents for class 257 subclass 590]  590           Subclass 590 indent level is 1 With means to reduce minority carrier lifetime (e.g., region of deep level dopant or region of crystal damage)
[List of Patents for class 257 subclass 591]  591           Subclass 591 indent level is 1 With emitter region having specified doping concentration profile (e.g., high-low concentration step)
[List of Patents for class 257 subclass 592]  592           Subclass 592 indent level is 1 With base region having specified doping concentration profile or specified configuration (e.g., inactive base more heavily doped than active base or base region has constant doping concentration portion (e.g., epitaxial base))
[List of Patents for class 257 subclass 593]  593           Subclass 593 indent level is 1 With means to increase current gain or operating frequency
[List of Patents for class 257 subclass 594]  594           WITH GROOVE TO DEFINE PLURAL DIODES
[List of Patents for class 257 subclass 595]  595           VOLTAGE VARIABLE CAPACITANCE DEVICE
[List of Patents for class 257 subclass 596]  596           Subclass 596 indent level is 1 With specified dopant profile
[List of Patents for class 257 subclass 597]  597           Subclass 597 indent level is 2 Retrograde dopant profile (e.g., dopant concentration decreases with distance from rectifying junction)
[List of Patents for class 257 subclass 598]  598           Subclass 598 indent level is 1 With plural junctions whose depletion regions merge to vary voltage dependence
[List of Patents for class 257 subclass 599]  599           Subclass 599 indent level is 1 With means to increase active junction area (e.g., grooved or convoluted surface)
[List of Patents for class 257 subclass 600]  600           Subclass 600 indent level is 1 With physical configuration to vary voltage dependence (e.g., mesa)
[List of Patents for class 257 subclass 601]  601           Subclass 601 indent level is 1 Plural diodes in same non-isolated structure, or device having three or more terminals
[List of Patents for class 257 subclass 602]  602           Subclass 602 indent level is 1 With specified housing or contact
[List of Patents for class 257 subclass 603]  603           AVALANCHE DIODE (E.G., SO-CALLED "ZENER" DIODE HAVING BREAKDOWN VOLTAGE GREATER THAN 6 VOLTS)
[List of Patents for class 257 subclass 604]  604           Subclass 604 indent level is 1 Microwave transit time device (e.g., IMPATT diode)
[List of Patents for class 257 subclass 605]  605           Subclass 605 indent level is 1 With means to limit area of breakdown (e.g., guard ring having higher breakdown voltage)
[List of Patents for class 257 subclass 606]  606           Subclass 606 indent level is 2 Subsurface breakdown
[List of Patents for class 257 subclass 607]  607           WITH SPECIFIED DOPANT (E.G., PLURAL DOPANTS OF SAME CONDUCTIVITY IN SAME REGION)
[List of Patents for class 257 subclass 608]  608           Subclass 608 indent level is 1 Switching device based on filling and emptying of deep energy levels
[List of Patents for class 257 subclass 609]  609           Subclass 609 indent level is 1 For compound semiconductor (e.g., deep level dopant)
[List of Patents for class 257 subclass 610]  610           Subclass 610 indent level is 1 Deep level dopant
[List of Patents for class 257 subclass 611]  611           Subclass 611 indent level is 2 With specified distribution (e.g., laterally localized, with specified concentration distribution or gradient)
[List of Patents for class 257 subclass 612]  612           Subclass 612 indent level is 2 Deep level dopant other than gold or platinum
[List of Patents for class 257 subclass 613]  613           INCLUDING SEMICONDUCTOR MATERIAL OTHER THAN SILICON OR GALLIUM ARSENIDE (GAAS) (E.G., PB X SN 1-X TE)
[List of Patents for class 257 subclass 614]  614           Subclass 614 indent level is 1 Group II-VI compound (e.g., CdTe, Hg x Cd 1-x Te)
[List of Patents for class 257 subclass 615]  615           Subclass 615 indent level is 1 Group III-V compound (e.g., InP)
[List of Patents for class 257 subclass 616]  616           Subclass 616 indent level is 1 Containing germanium, Ge
[List of Patents for class 257 subclass 617]  617           INCLUDING REGION CONTAINING CRYSTAL DAMAGE
[List of Patents for class 257 subclass 618]  618           PHYSICAL CONFIGURATION OF SEMICONDUCTOR (E.G., MESA, BEVEL, GROOVE, ETC.)
[List of Patents for class 257 subclass 619]  619           Subclass 619 indent level is 1 With thin active central semiconductor portion surrounded by thicker inactive shoulder (e.g., for mechanical support)
[List of Patents for class 257 subclass 620]  620           Subclass 620 indent level is 1 With peripheral feature due to separation of smaller semiconductor chip from larger wafer (e.g., scribe region, or means to prevent edge effects such as leakage current at peripheral chip separation area)
[List of Patents for class 257 subclass 621]  621           Subclass 621 indent level is 1 With electrical contact in hole in semiconductor (e.g., lead extends through semiconductor body)
[List of Patents for class 257 subclass 622]  622           Subclass 622 indent level is 1 Groove
[List of Patents for class 257 subclass 623]  623           Subclass 623 indent level is 1 Mesa structure (e.g., including undercut or stepped mesa configuration or having constant slope taper)
[List of Patents for class 257 subclass 624]  624           Subclass 624 indent level is 2 With low resistance ohmic connection means along exposed mesa edge (e.g., contact or heavily doped region along exposed mesa to reduce "skin effect" losses in microwave diode)
[List of Patents for class 257 subclass 625]  625           Subclass 625 indent level is 2 Semiconductor body including mesa is intimately bonded to thick electrical and/or thermal conductor member of larger lateral extent than semiconductor body (e.g., "plated heat sink" microwave diode)
[List of Patents for class 257 subclass 626]  626           Subclass 626 indent level is 2 Combined with passivating coating
[List of Patents for class 257 subclass 627]  627           Subclass 627 indent level is 1 With specified crystal plane or axis
[List of Patents for class 257 subclass 628]  628           Subclass 628 indent level is 2 Major crystal plane or axis other than (100), (110), or (111) (e.g., (731) axis, crystal plane several degrees from (100) toward (011), etc.)
[List of Patents for class 257 subclass 629]  629           WITH MEANS TO CONTROL SURFACE EFFECTS
[List of Patents for class 257 subclass 630]  630           Subclass 630 indent level is 1 With inversion-preventing shield electrode
[List of Patents for class 257 subclass 631]  631           Subclass 631 indent level is 1 In compound semiconductor material (e.g., GaAs)
[List of Patents for class 257 subclass 632]  632           Subclass 632 indent level is 1 Insulating coating
[List of Patents for class 257 subclass 633]  633           Subclass 633 indent level is 2 With thermal expansion compensation (e.g., thermal expansion of glass passivant matched to that of semiconductor)
[List of Patents for class 257 subclass 634]  634           Subclass 634 indent level is 2 Insulating coating of glass composition containing component to adjust melting or softening temperature (e.g., low melting point glass)
[List of Patents for class 257 subclass 635]  635           Subclass 635 indent level is 2 Multiple layers
[List of Patents for class 257 subclass 636]  636           Subclass 636 indent level is 3 At least one layer of semi-insulating material
[List of Patents for class 257 subclass 637]  637           Subclass 637 indent level is 3 Three or more insulating layers
[List of Patents for class 257 subclass 638]  638           Subclass 638 indent level is 3 With discontinuous or varying thickness layer (e.g., layer covers only selected portions of semiconductor)
[List of Patents for class 257 subclass 639]  639           Subclass 639 indent level is 3 At least one layer of silicon oxynitride
[List of Patents for class 257 subclass 640]  640           Subclass 640 indent level is 3 At least one layer of silicon nitride
[List of Patents for class 257 subclass 641]  641           Subclass 641 indent level is 4 Combined with glass layer
[List of Patents for class 257 subclass 642]  642           Subclass 642 indent level is 3 At least one layer of organic material
[List of Patents for class 257 subclass 643]  643           Subclass 643 indent level is 4 Polyimide or polyamide
[List of Patents for class 257 subclass 644]  644           Subclass 644 indent level is 3 At least one layer of glass
[List of Patents for class 257 subclass 645]  645           Subclass 645 indent level is 3 Insulating layer containing specified electrical charge (e.g., net negative electrical charge)
[List of Patents for class 257 subclass 646]  646           Subclass 646 indent level is 2 Coating of semi-insulating material (e.g., amorphous silicon or silicon-rich silicon oxide)
[List of Patents for class 257 subclass 647]  647           Subclass 647 indent level is 2 Insulating layer recessed into semiconductor surface (e.g., LOCOS oxide)
[List of Patents for class 257 subclass 648]  648           Subclass 648 indent level is 3 Combined with channel stop region in semiconductor
[List of Patents for class 257 subclass 649]  649           Subclass 649 indent level is 2 Insulating layer of silicon nitride or silicon oxynitride
[List of Patents for class 257 subclass 650]  650           Subclass 650 indent level is 2 Insulating layer of glass
[List of Patents for class 257 subclass 651]  651           Subclass 651 indent level is 2 Details of insulating layer electrical charge (e.g., negative insulator layer charge)
[List of Patents for class 257 subclass 652]  652           Subclass 652 indent level is 1 Channel stop layer
[List of Patents for class 257 subclass 653]  653           WITH SPECIFIED SHAPE OF PN JUNCTION
[List of Patents for class 257 subclass 654]  654           Subclass 654 indent level is 1 Interdigitated pn junction or more heavily doped side of junction is concave
[List of Patents for class 257 subclass 655]  655           WITH SPECIFIED IMPURITY CONCENTRATION GRADIENT
[List of Patents for class 257 subclass 656]  656           Subclass 656 indent level is 1 With high resistivity (e.g., "intrinsic") layer between P and N layers (e.g., PIN diode)
[List of Patents for class 257 subclass 657]  657           Subclass 657 indent level is 1 Stepped profile
[List of Patents for class 257 subclass 658]  658           PLATE TYPE RECTIFIER ARRAY
[List of Patents for class 257 subclass 659]  659           WITH SHIELDING (E.G., ELECTRICAL OR MAGNETIC SHIELDING, OR FROM ELECTROMAGNETIC RADIATION OR CHARGED PARTICLES)
[List of Patents for class 257 subclass 660]  660           Subclass 660 indent level is 1 With means to shield device contained in housing or package from charged particles (e.g., alpha particles) or highly ionizing radiation (i.e., hard X-rays or shorter wavelength)
[List of Patents for class 257 subclass 661]  661           SUPERCONDUCTIVE CONTACT OR LEAD
[List of Patents for class 257 subclass 662]  662           Subclass 662 indent level is 1 Transmission line or shielded
[List of Patents for class 257 subclass 663]  663           Subclass 663 indent level is 1 On integrated circuit
[List of Patents for class 257 subclass 664]  664           TRANSMISSION LINE LEAD (E.G., STRIPLINE, COAX, ETC.)
[List of Patents for class 257 subclass 665]  665           CONTACTS OR LEADS INCLUDING FUSIBLE LINK MEANS OR NOISE SUPPRESSION MEANS
[List of Patents for class 257 subclass 666]  666           LEAD FRAME
[List of Patents for class 257 subclass 667]  667           Subclass 667 indent level is 1 With dam or vent for encapsulant
[List of Patents for class 257 subclass 668]  668           Subclass 668 indent level is 1 On insulating carrier other than a printed circuit board
[List of Patents for class 257 subclass 669]  669           Subclass 669 indent level is 1 With stress relief
[List of Patents for class 257 subclass 670]  670           Subclass 670 indent level is 1 With separate tie bar element or plural tie bars
[List of Patents for class 257 subclass 671]  671           Subclass 671 indent level is 2 Of insulating material
[List of Patents for class 257 subclass 672]  672           Subclass 672 indent level is 1 Small lead frame (e.g., "spider" frame) for connecting a large lead frame to a semiconductor chip
[List of Patents for class 257 subclass 673]  673           Subclass 673 indent level is 1 With bumps on ends of lead fingers to connect to semiconductor
[List of Patents for class 257 subclass 674]  674           Subclass 674 indent level is 1 With means for controlling lead tension
[List of Patents for class 257 subclass 675]  675           Subclass 675 indent level is 1 With heat sink means
[List of Patents for class 257 subclass 676]  676           Subclass 676 indent level is 1 With structure for mounting semiconductor chip to lead frame (e.g., configuration of die bonding flag, absence of a die bonding flag, recess for LED)
[List of Patents for class 257 subclass 677]  677           Subclass 677 indent level is 1 Of specified material other than copper (e.g., Kovar (T.M.))
[List of Patents for class 257 subclass 678]  678           HOUSING OR PACKAGE
[List of Patents for class 257 subclass 679]  679           Subclass 679 indent level is 1 Smart (e.g., credit) card package
[List of Patents for class 257 subclass 680]  680           Subclass 680 indent level is 1 With window means
[List of Patents for class 257 subclass 681]  681           Subclass 681 indent level is 2 For erasing EPROM
[List of Patents for class 257 subclass 682]  682           Subclass 682 indent level is 1 With desiccant, getter, or gas filling
[List of Patents for class 257 subclass 683]  683           Subclass 683 indent level is 1 With means to prevent explosion of package
[List of Patents for class 257 subclass 684]  684           Subclass 684 indent level is 1 With semiconductor element forming part (e.g., base, of housing)
[List of Patents for class 257 subclass 685]  685           Subclass 685 indent level is 1 Multiple housings
[List of Patents for class 257 subclass 686]  686           Subclass 686 indent level is 2 Stacked arrangement
[List of Patents for class 257 subclass 687]  687           Subclass 687 indent level is 1 Housing or package filled with solid or liquid electrically insulating material
[List of Patents for class 257 subclass 688]  688           Subclass 688 indent level is 1 With large area flexible electrodes in press contact with opposite sides of active semiconductor chip and surrounded by an insulating element, e.g., ring
[List of Patents for class 257 subclass 689]  689           Subclass 689 indent level is 2 Rigid electrode portion
[List of Patents for class 257 subclass 690]  690           Subclass 690 indent level is 1 With contact or lead
[List of Patents for class 257 subclass 691]  691           Subclass 691 indent level is 2 Having power distribution means (e.g., bus structure)
[List of Patents for class 257 subclass 692]  692           Subclass 692 indent level is 2 With particular lead geometry
[List of Patents for class 257 subclass 693]  693           Subclass 693 indent level is 3 External connection to housing
[List of Patents for class 257 subclass 694]  694           Subclass 694 indent level is 4 Axial leads
[List of Patents for class 257 subclass 695]  695           Subclass 695 indent level is 4 Fanned/radial leads
[List of Patents for class 257 subclass 696]  696           Subclass 696 indent level is 4 Bent (e.g., J-shaped) lead
[List of Patents for class 257 subclass 697]  697           Subclass 697 indent level is 4 Pin grid type
[List of Patents for class 257 subclass 698]  698           Subclass 698 indent level is 2 With specific electrical feedthrough structure
[List of Patents for class 257 subclass 699]  699           Subclass 699 indent level is 3 Housing entirely of metal except for feedthrough structure
[List of Patents for class 257 subclass 700]  700           Subclass 700 indent level is 2 Multiple contact layers separated from each other by insulator means and forming part of a package or housing (e.g., plural ceramic layer package)
[List of Patents for class 257 subclass 701]  701           Subclass 701 indent level is 1 Insulating material
[List of Patents for class 257 subclass 702]  702           Subclass 702 indent level is 2 Of insulating material other than ceramic
[List of Patents for class 257 subclass 703]  703           Subclass 703 indent level is 2 Composite ceramic, or single ceramic with metal
[List of Patents for class 257 subclass 704]  704           Subclass 704 indent level is 2 Cap or lid
[List of Patents for class 257 subclass 705]  705           Subclass 705 indent level is 2 Of high thermal conductivity ceramic (e.g., BeO)
[List of Patents for class 257 subclass 706]  706           Subclass 706 indent level is 2 With heat sink
[List of Patents for class 257 subclass 707]  707           Subclass 707 indent level is 3 Directly attached to semiconductor device
[List of Patents for class 257 subclass 708]  708           Subclass 708 indent level is 1 Entirely of metal except for feedthrough
[List of Patents for class 257 subclass 709]  709           Subclass 709 indent level is 2 With specified insulator to isolate device from housing
[List of Patents for class 257 subclass 710]  710           Subclass 710 indent level is 2 With specified means (e.g., lip) to seal base to cap
[List of Patents for class 257 subclass 711]  711           Subclass 711 indent level is 2 With raised portion of base for mounting semiconductor chip
[List of Patents for class 257 subclass 712]  712           Subclass 712 indent level is 1 With provision for cooling the housing or its contents
[List of Patents for class 257 subclass 713]  713           Subclass 713 indent level is 2 For integrated circuit
[List of Patents for class 257 subclass 714]  714           Subclass 714 indent level is 2 Liquid coolant
[List of Patents for class 257 subclass 715]  715           Subclass 715 indent level is 3 Boiling (evaporative) liquid
[List of Patents for class 257 subclass 716]  716           Subclass 716 indent level is 3 Cryogenic liquid coolant
[List of Patents for class 257 subclass 717]  717           Subclass 717 indent level is 2 Isolation of cooling means (e.g., heat sink) by an electrically insulating element (e.g., spacer)
[List of Patents for class 257 subclass 718]  718           Subclass 718 indent level is 2 Heat dissipating element held in place by clamping or spring means
[List of Patents for class 257 subclass 719]  719           Subclass 719 indent level is 3 Pressed against semiconductor element
[List of Patents for class 257 subclass 720]  720           Subclass 720 indent level is 2 Heat dissipating element has high thermal conductivity insert (e.g., copper slug in aluminum heat sink)
[List of Patents for class 257 subclass 721]  721           Subclass 721 indent level is 2 With gas coolant
[List of Patents for class 257 subclass 722]  722           Subclass 722 indent level is 3 With fins
[List of Patents for class 257 subclass 723]  723           Subclass 723 indent level is 1 For plural devices
[List of Patents for class 257 subclass 724]  724           Subclass 724 indent level is 2 With discrete components
[List of Patents for class 257 subclass 725]  725           Subclass 725 indent level is 2 With electrical isolation means
[List of Patents for class 257 subclass 726]  726           Subclass 726 indent level is 3 Devices held in place by clamping
[List of Patents for class 257 subclass 727]  727           Subclass 727 indent level is 1 Device held in place by clamping
[List of Patents for class 257 subclass 728]  728           Subclass 728 indent level is 1 For high frequency (e.g., microwave) device
[List of Patents for class 257 subclass 729]  729           Subclass 729 indent level is 1 Portion of housing of specific materials
[List of Patents for class 257 subclass 730]  730           Subclass 730 indent level is 1 Outside periphery of package having specified shape or configuration
[List of Patents for class 257 subclass 731]  731           Subclass 731 indent level is 1 With housing mount
[List of Patents for class 257 subclass 732]  732           Subclass 732 indent level is 2 Flanged mount
[List of Patents for class 257 subclass 733]  733           Subclass 733 indent level is 2 Stud mount
[List of Patents for class 257 subclass 734]  734           COMBINED WITH ELECTRICAL CONTACT OR LEAD
[List of Patents for class 257 subclass 735]  735           Subclass 735 indent level is 1 Beam leads (i.e., leads that extend beyond the ends or sides of a chip component)
[List of Patents for class 257 subclass 736]  736           Subclass 736 indent level is 2 Layered
[List of Patents for class 257 subclass 737]  737           Subclass 737 indent level is 1 Bump leads
[List of Patents for class 257 subclass 738]  738           Subclass 738 indent level is 2 Ball shaped
[List of Patents for class 257 subclass 739]  739           Subclass 739 indent level is 1 With textured surface
[List of Patents for class 257 subclass 740]  740           Subclass 740 indent level is 1 With means to prevent contact from penetrating shallow PN junction (e.g., prevention of aluminum "spiking")
[List of Patents for class 257 subclass 741]  741           Subclass 741 indent level is 1 Of specified material other than unalloyed aluminum
[List of Patents for class 257 subclass 742]  742           Subclass 742 indent level is 2 With a semiconductor conductivity substitution type dopant (e.g., germanium in the case of a gallium arsenide semiconductor) in a contact metal)
[List of Patents for class 257 subclass 743]  743           Subclass 743 indent level is 3 For compound semiconductor material
[List of Patents for class 257 subclass 744]  744           Subclass 744 indent level is 2 For compound semiconductor material
[List of Patents for class 257 subclass 745]  745           Subclass 745 indent level is 3 Contact for III-V material
[List of Patents for class 257 subclass 746]  746           Subclass 746 indent level is 2 Composite material (e.g., fibers or strands embedded in solid matrix)
[List of Patents for class 257 subclass 747]  747           Subclass 747 indent level is 2 With thermal expansion matching of contact or lead material to semiconductor active device
[List of Patents for class 257 subclass 748]  748           Subclass 748 indent level is 3 Plural layers of specified contact or lead material
[List of Patents for class 257 subclass 749]  749           Subclass 749 indent level is 2 At least portion of which is transparent to ultraviolet, visible or infrared light
[List of Patents for class 257 subclass 750]  750           Subclass 750 indent level is 2 Layered
[List of Patents for class 257 subclass 751]  751           Subclass 751 indent level is 3 At least one layer forms a diffusion barrier
[List of Patents for class 257 subclass 752]  752           Subclass 752 indent level is 3 Planarized to top of insulating layer
[List of Patents for class 257 subclass 753]  753           Subclass 753 indent level is 3 With adhesion promoting means (e.g., layer of material) to promote adhesion of contact to an insulating layer
[List of Patents for class 257 subclass 754]  754           Subclass 754 indent level is 3 At least one layer of silicide or polycrystalline silicon
[List of Patents for class 257 subclass 755]  755           Subclass 755 indent level is 4 Polysilicon laminated with silicide
[List of Patents for class 257 subclass 756]  756           Subclass 756 indent level is 4 Multiple polysilicon layers
[List of Patents for class 257 subclass 757]  757           Subclass 757 indent level is 4 Silicide of refractory or platinum group metal
[List of Patents for class 257 subclass 758]  758           Subclass 758 indent level is 3 Multiple metal levels on semiconductor, separated by insulating layer (e.g., multiple level metallization for integrated circuit)
[List of Patents for class 257 subclass 759]  759           Subclass 759 indent level is 4 Including organic insulating material between metal levels
[List of Patents for class 257 subclass 760]  760           Subclass 760 indent level is 4 Separating insulating layer is laminate or composite of plural insulating materials (e.g., silicon oxide on silicon nitride, silicon oxynitride)
[List of Patents for class 257 subclass 761]  761           Subclass 761 indent level is 3 At least one layer containing vanadium, hafnium, niobium, zirconium, or tantalum
[List of Patents for class 257 subclass 762]  762           Subclass 762 indent level is 3 At least one layer containing silver or copper
[List of Patents for class 257 subclass 763]  763           Subclass 763 indent level is 3 At least one layer of molybdenum, titanium, or tungsten
[List of Patents for class 257 subclass 764]  764           Subclass 764 indent level is 4 Alloy containing molybdenum, titanium, or tungsten
[List of Patents for class 257 subclass 765]  765           Subclass 765 indent level is 3 At least one layer of an alloy containing aluminum
[List of Patents for class 257 subclass 766]  766           Subclass 766 indent level is 3 At least one layer containing chromium or nickel
[List of Patents for class 257 subclass 767]  767           Subclass 767 indent level is 2 Resistive to electromigration or diffusion of the contact or lead material
[List of Patents for class 257 subclass 768]  768           Subclass 768 indent level is 2 Refractory or platinum group metal or alloy or silicide thereof
[List of Patents for class 257 subclass 769]  769           Subclass 769 indent level is 3 Platinum group metal or silicide thereof
[List of Patents for class 257 subclass 770]  770           Subclass 770 indent level is 3 Molybdenum, tungsten, or titanium or their silicides
[List of Patents for class 257 subclass 771]  771           Subclass 771 indent level is 2 Alloy containing aluminum
[List of Patents for class 257 subclass 772]  772           Subclass 772 indent level is 2 Solder composition
[List of Patents for class 257 subclass 773]  773           Subclass 773 indent level is 1 Of specified configuration
[List of Patents for class 257 subclass 774]  774           Subclass 774 indent level is 2 Via (interconnection hole) shape
[List of Patents for class 257 subclass 775]  775           Subclass 775 indent level is 2 Varying width or thickness of conductor
[List of Patents for class 257 subclass 776]  776           Subclass 776 indent level is 2 Cross-over arrangement, component or structure
[List of Patents for class 257 subclass 777]  777           Subclass 777 indent level is 1 Chip mounted on chip
[List of Patents for class 257 subclass 778]  778           Subclass 778 indent level is 1 Flip chip
[List of Patents for class 257 subclass 779]  779           Subclass 779 indent level is 1 Solder wettable contact, lead, or bond
[List of Patents for class 257 subclass 780]  780           Subclass 780 indent level is 1 Ball or nail head type contact, lead, or bond
[List of Patents for class 257 subclass 781]  781           Subclass 781 indent level is 2 Layered contact, lead or bond
[List of Patents for class 257 subclass 782]  782           Subclass 782 indent level is 1 Die bond
[List of Patents for class 257 subclass 783]  783           Subclass 783 indent level is 2 With adhesive means
[List of Patents for class 257 subclass 784]  784           Subclass 784 indent level is 1 Wire contact, lead, or bond
[List of Patents for class 257 subclass 785]  785           Subclass 785 indent level is 1 By pressure alone
[List of Patents for class 257 subclass 786]  786           Subclass 786 indent level is 1 Configuration or pattern of bonds
[List of Patents for class 257 subclass 787]  787           ENCAPSULATED
[List of Patents for class 257 subclass 788]  788           Subclass 788 indent level is 1 With specified encapsulant
[List of Patents for class 257 subclass 789]  789           Subclass 789 indent level is 2 With specified filler material
[List of Patents for class 257 subclass 790]  790           Subclass 790 indent level is 2 Plural encapsulating layers
[List of Patents for class 257 subclass 791]  791           Subclass 791 indent level is 2 Including polysiloxane (e.g., silicone resin)
[List of Patents for class 257 subclass 792]  792           Subclass 792 indent level is 2 Including polyimide
[List of Patents for class 257 subclass 793]  793           Subclass 793 indent level is 2 Including epoxide
[List of Patents for class 257 subclass 794]  794           Subclass 794 indent level is 2 Including glass
[List of Patents for class 257 subclass 795]  795           Subclass 795 indent level is 1 With specified filler material
[List of Patents for class 257 subclass 796]  796           Subclass 796 indent level is 1 With heat sink embedded in encapsulant
[List of Patents for class 257 subclass 797]  797           ALIGNMENT MARKS
[List of Patents for class 257 subclass 798]  798           MISCELLANEOUS
 
E-SUBCLASSES
 
The following subclasses beginning with the letter E are E-subclasses. Each E-subclass corresponds to a classification in the European Classification system (ECLA). The ECLA classification is parenthesized at the end of the title. E-subclasses contain both U.S. and foreign documents. New U.S. documents are classified here by the USPTO, and European foreign by the EPO. E-subclasses may contain subject matter outside the scope of this class. Consult their definitions, or the documents themselves to clarify or interpret titles.
   E47.001          BULK NEGATIVE RESISTANCE EFFECT DEVICES, E.G., GUNN-EFFECT DEVICES, PROCESSES, OR APPARATUS PECULIAR TO MANUFACTURE OR TREATMENT OF SUCH DEVICES, OR OF PARTS THEREOF (EPO)
   E47.002          Subclass E47.002 indent level is 1 Gunn-effect devices or transferred electron devices (EPO)
   E47.003          Subclass E47.003 indent level is 2 Controlled by electromagnetic radiation (EPO)
   E47.004          Subclass E47.004 indent level is 2 Gunn diodes (EPO)
   E47.005          Subclass E47.005 indent level is 1 Processes or apparatus peculiar to manufacture or treatment of these devices or of parts thereof (EPO)
   E39.001          DEVICES USING SUPERCONDUCTIVITY, PROCESSES, OR APPARATUS PECULIAR TO MANUFACTURE OR TREATMENT OF SUCH DEVICES, OR OF PARTS THEREOF (EPO)
   E39.002          Subclass E39.002 indent level is 1 Containers or mountings (EPO)
   E39.003          Subclass E39.003 indent level is 2 For Josephson devices (EPO)
   E39.004          Subclass E39.004 indent level is 1 Characterized by current path (EPO)
   E39.005          Subclass E39.005 indent level is 1 Characterized by shape of element (EPO)
   E39.006          Subclass E39.006 indent level is 1 Characterized by material (EPO)
   E39.007          Subclass E39.007 indent level is 2 Organic materials (EPO)
   E39.008          Subclass E39.008 indent level is 3 Fullerene superconductors, e.g., soccerball-shaped allotrope of carbon, e.g., C60, C94 (EPO)
   E39.009          Subclass E39.009 indent level is 2 Ceramic materials (EPO)
   E39.01          Subclass E39.01 indent level is 3 Comprising copper oxide (EPO)
   E39.011          Subclass E39.011 indent level is 4 Multilayered structures, e.g., super lattices (EPO)
   E39.012          Subclass E39.012 indent level is 1 Devices comprising junction of dissimilar materials, e.g., Josephson-effect devices (EPO)
   E39.013          Subclass E39.013 indent level is 2 Single electron tunnelling devices (EPO)
   E39.014          Subclass E39.014 indent level is 2 Josephson-effect devices (EPO)
   E39.015          Subclass E39.015 indent level is 3 Comprising high Tc ceramic materials (EPO)
   E39.016          Subclass E39.016 indent level is 2 Three or more electrode devices, e.g., transistor-like structures (EPO)
   E39.017          Subclass E39.017 indent level is 1 Permanent superconductor devices (EPO)
   E39.018          Subclass E39.018 indent level is 2 Comprising high Tc ceramic materials (EPO)
   E39.019          Subclass E39.019 indent level is 2 Three or more electrode devices (EPO)
   E39.02          Subclass E39.02 indent level is 3 Field-effect devices (EPO)
   E51.001          ORGANIC SOLID STATE DEVICES, PROCESSES OR APPARATUS PECULIAR TO MANUFACTURE OR TREATMENT OF SUCH DEVICES OR OF PARTS THEREOF
   E51.002          Subclass E51.002 indent level is 1 Structural detail of device (EPO)
   E51.003          Subclass E51.003 indent level is 2 Organic solid-state device adapted for rectifying, amplifying, oscillating, or switching, or capacitors or resistors with potential or surface barrier (EPO)
   E51.004          Subclass E51.004 indent level is 3 Controllable by only signal applied to control electrode (e.g., base of bipolar transistor, gate of field-effect transistor) (EPO)
   E51.005          Subclass E51.005 indent level is 4 Field-effect device (e.g., TFT, FET) (EPO)
   E51.006          Subclass E51.006 indent level is 5 Insulated gate field-effect transistor (EPO)
   E51.007          Subclass E51.007 indent level is 6 Comprising organic gate dielectric (EPO)
   E51.008          Subclass E51.008 indent level is 3 Controllable only by variation of electric current supplied or only electric potential applied to electrode carrying current to be rectified, amplified, oscillated, or switched (e.g., two terminal device) (EPO)
   E51.009          Subclass E51.009 indent level is 4 Comprising Schottky junction (EPO)
   E51.01          Subclass E51.01 indent level is 4 Comprising organic/organic junction (e.g., heterojunction) (EPO)
   E51.011          Subclass E51.011 indent level is 4 Comprising organic/inorganic heterojunction (EPO)
   E51.012          Subclass E51.012 indent level is 2 Radiation-sensitive organic solid-state device (EPO)
   E51.013          Subclass E51.013 indent level is 3 Metal-organic semiconductor-metal device (EPO)
   E51.014          Subclass E51.014 indent level is 3 Comprising bulk heterojunction (EPO)
   E51.015          Subclass E51.015 indent level is 3 Comprising organic/inorganic heterojunction (EPO)
   E51.016          Subclass E51.016 indent level is 4 Majority carrier device using sensitization of wide band gap semiconductor (e.g., TiO 2 ) (EPO)
   E51.017          Subclass E51.017 indent level is 3 Comprising organic semiconductor-organic semiconductor heterojunction (EPO)
   E51.018          Subclass E51.018 indent level is 2 Light-emitting organic solid-state device with potential or surface barrier (EPO)
   E51.019          Subclass E51.019 indent level is 3 Electrode (EPO)
   E51.02          Subclass E51.02 indent level is 4 Encapsulation (EPO)
   E51.021          Subclass E51.021 indent level is 4 Arrangements for extracting light from device (e.g., Bragg reflector pair) (EPO)
   E51.022          Subclass E51.022 indent level is 3 Multicolor organic light-emitting device (OLED) (EPO)
   E51.023          Subclass E51.023 indent level is 2 Molecular electronic device (EPO)
   E51.024          Subclass E51.024 indent level is 1 Selection of material for organic solid-state device (EPO)
   E51.025          Subclass E51.025 indent level is 2 For organic solid-state device adapted for rectifying, amplifying, oscillating, or switching, or capacitors or resistors with potential or surface barrier (EPO)
   E51.026          Subclass E51.026 indent level is 2 For radiation-sensitive or light-emitting organic solid-state device with potential or surface barrier (EPO)
   E51.027          Subclass E51.027 indent level is 2 Organic polymer or oligomer (EPO)
   E51.028          Subclass E51.028 indent level is 3 Comprising aromatic, heteroaromatic, or arrylic chains (e.g., polyaniline, polyphenylene, polyphenylene vinylene) (EPO)
   E51.029          Subclass E51.029 indent level is 4 Heteroaromatic compound comprising sulfur or selene (e.g., polythiophene) (EPO)
   E51.03          Subclass E51.03 indent level is 5 Polyethylene dioxythiophene and derivative (EPO)
   E51.031          Subclass E51.031 indent level is 4 Polyphenylenevinylene and derivatives (EPO)
   E51.032          Subclass E51.032 indent level is 4 Polyflurorene and derivative (EPO)
   E51.033          Subclass E51.033 indent level is 3 Comprising aliphatic or olefinic chains (e.g., polyN-vinylcarbazol, PVC, PTFE) (EPO)
   E51.034          Subclass E51.034 indent level is 4 Polyacetylene or derivatives (EPO)
   E51.035          Subclass E51.035 indent level is 4 PolyN-vinylcarbazol and derivative (EPO)
   E51.036          Subclass E51.036 indent level is 3 Copolymers (EPO)
   E51.037          Subclass E51.037 indent level is 3 Ladder-type polymer (EPO)
   E51.038          Subclass E51.038 indent level is 2 Carbon-containing materials (EPO)
   E51.039          Subclass E51.039 indent level is 3 Fullerenes (EPO)
   E51.04          Subclass E51.04 indent level is 3 Carbon nanotubes (EPO)
   E51.041          Subclass E51.041 indent level is 2 Coordination compound (e.g., porphyrin, phthalocyanine, metal(II) polypyridine complexes) (EPO)
   E51.042          Subclass E51.042 indent level is 3 Phthalocyanine (EPO)
   E51.043          Subclass E51.043 indent level is 3 Metal complexes comprising Group IIIB metal (Al, Ga, In, or Ti) (e.g., Tris (8-hydroxyquinoline) aluminium (Alq3)) (EPO)
   E51.044          Subclass E51.044 indent level is 3 Transition metal complexes (e.g., Ru(II) polypyridine complexes) (EPO)
   E51.045          Subclass E51.045 indent level is 2 Biomolecule or macromolecule (e.g., proteins, ATP, chlorophyl, beta-carotene, lipids, enzymes) (EPO)
   E51.046          Subclass E51.046 indent level is 2 Silicon-containing organic semiconductor (EPO)
   E51.047          Subclass E51.047 indent level is 2 Macromolecular system with low molecular weight (e.g., cyanine dyes, coumarine dyes, tetrathiafulvalene) (EPO)
   E51.048          Subclass E51.048 indent level is 3 Charge transfer complexes (EPO)
   E51.049          Subclass E51.049 indent level is 3 Polycondensed aromatic or heteroaromatic compound (e.g., pyrene, perylene, pentacene) (EPO)
   E51.05          Subclass E51.05 indent level is 4 Aromatic compound containing heteroatom (e.g., perylenetetracarboxylic dianhydride, perylene tetracarboxylic diimide) (EPO)
   E51.051          Subclass E51.051 indent level is 3 Amine compound having at least two aryl on amine-nitrogen atom (e.g., triphenylamine) (EPO)
   E51.052          Subclass E51.052 indent level is 2 Langmuir Blodgett film (EPO)
   E43.001          SEMICONDUCTOR OR SOLID-STATE DEVICES USING GALVANO-MAGNETIC OR SIMILAR MAGNETIC EFFECTS, PROCESSES OR APPARATUS PECULIAR TO MANUFACTURE OR TREATMENT OF SUCH DEVICES, OR OF PARTS THEREOF (EPO)
   E43.002          Subclass E43.002 indent level is 1 Hall-effect devices (EPO)
   E43.003          Subclass E43.003 indent level is 2 Semiconductor Hall-effect devices (EPO)
   E43.004          Subclass E43.004 indent level is 1 Magnetic-field-controlled resistors (EPO)
   E43.005          Subclass E43.005 indent level is 1 Selection of materials (EPO)
   E43.006          Subclass E43.006 indent level is 1 Processes or apparatus peculiar to manufacture or treatment of these devices or of parts thereof (EPO)
   E43.007          Subclass E43.007 indent level is 2 For Hall-effect devices (EPO)
   E33.001          LIGHT EMITTING SEMICONDUCTOR DEVICES HAVING A POTENTIAL OR A SURFACE BARRIER, PROCESSES OR APPARATUS PECULIAR TO THE MANUFACTURE OR TREATMENT OF SUCH DEVICES, OR OF PARTS THEREOF
   E33.002          Subclass E33.002 indent level is 1 Device characterized by semiconductor body (EPO)
   E33.003          Subclass E33.003 indent level is 2 Particular crystalline orientation or structure (EPO)
   E33.004          Subclass E33.004 indent level is 3 Comprising amorphous semiconductor (EPO)
   E33.005          Subclass E33.005 indent level is 2 Shape or structure (e.g., shape of epitaxial layer) (EPO)
   E33.006          Subclass E33.006 indent level is 3 Shape of semiconductor body (EPO)
   E33.007          Subclass E33.007 indent level is 3 Shape of potential barrier (EPO)
   E33.008          Subclass E33.008 indent level is 3 Multiple quantum well structure (EPO)
   E33.009          Subclass E33.009 indent level is 4 Including, apart from doping materials or other only impurities, Group IV element (e.g., Si-SiGe superlattice) (EPO)
   E33.01          Subclass E33.01 indent level is 4 Doped superlattice (e.g., nipi superlattice) (EPO)
   E33.011          Subclass E33.011 indent level is 3 For current confinement (EPO)
   E33.012          Subclass E33.012 indent level is 3 Multiple active regions between two electrodes (e.g., stacks) (EPO)
   E33.013          Subclass E33.013 indent level is 2 Material of active region (EPO)
   E33.014          Subclass E33.014 indent level is 3 In different regions (EPO)
   E33.015          Subclass E33.015 indent level is 3 Comprising only Group IV element (EPO)
   E33.016          Subclass E33.016 indent level is 4 With heterojunction (EPO)
   E33.017          Subclass E33.017 indent level is 4 Characterized by doping material (EPO)
   E33.018          Subclass E33.018 indent level is 4 Including porous Si (EPO)
   E33.019          Subclass E33.019 indent level is 3 Comprising only Group II-VI compound (EPO)
   E33.02          Subclass E33.02 indent level is 4 Ternary or quaternary compound (e.g., CdHgTe) (EPO)
   E33.021          Subclass E33.021 indent level is 5 With heterojunction (EPO)
   E33.022          Subclass E33.022 indent level is 4 Characterized by doping material (EPO)
   E33.023          Subclass E33.023 indent level is 3 Comprising only Group III-V compound (EPO)
   E33.024          Subclass E33.024 indent level is 4 Binary compound (e.g., GaAs) (EPO)
   E33.025          Subclass E33.025 indent level is 5 Including nitride (e.g., GaN) (EPO)
   E33.026          Subclass E33.026 indent level is 4 Ternary or quaternary compound (e.g., AlGaAs) (EPO)
   E33.027          Subclass E33.027 indent level is 5 With heterojunction (EPO)
   E33.028          Subclass E33.028 indent level is 5 Including nitride (e.g., AlGaN) (EPO)
   E33.029          Subclass E33.029 indent level is 4 Characterized by doping material (EPO)
   E33.03          Subclass E33.03 indent level is 5 Nitride compound (EPO)
   E33.031          Subclass E33.031 indent level is 4 Including ternary or quaternary compound (e.g., AlGaAs) (EPO)
   E33.032          Subclass E33.032 indent level is 5 With heterojunction (e.g., AlGaAs/GaAs) (EPO)
   E33.033          Subclass E33.033 indent level is 5 Comprising nitride compound (e.g., AlGaN) (EPO)
   E33.034          Subclass E33.034 indent level is 6 With heterojunction (e.g., AlGaN/GaN) (EPO)
   E33.035          Subclass E33.035 indent level is 3 Comprising only Group IV compound (e.g., SiC) (EPO)
   E33.036          Subclass E33.036 indent level is 4 Characterized by doping material (EPO)
   E33.037          Subclass E33.037 indent level is 3 Comprising compound other than Group II-VI, III-V, and IV compound (EPO)
   E33.038          Subclass E33.038 indent level is 4 Comprising only Group IV-VI compound (EPO)
   E33.039          Subclass E33.039 indent level is 4 Comprising only Group II-IV-VI compound (EPO)
   E33.04          Subclass E33.04 indent level is 4 Comprising only Group I-III-VI compound (EPO)
   E33.041          Subclass E33.041 indent level is 4 Characterized by doping material (EPO)
   E33.042          Subclass E33.042 indent level is 4 Comprising only Group IV-VI or II-IV-VI compound (EPO)
   E33.043          Subclass E33.043 indent level is 2 Physical imperfections (e.g., particular concentration or distribution of impurity) (EPO)
   E33.044          Subclass E33.044 indent level is 1 Device characterized by their operation (EPO)
   E33.045          Subclass E33.045 indent level is 2 Having p-n or hi-lo junction (EPO)
   E33.046          Subclass E33.046 indent level is 3 P-I-N device (EPO)
   E33.047          Subclass E33.047 indent level is 3 Having at least two p-n junctions (EPO)
   E33.048          Subclass E33.048 indent level is 2 Having heterojunction or graded gap (EPO)
   E33.049          Subclass E33.049 indent level is 3 Comprising only Group III-V compound (EPO)
   E33.05          Subclass E33.05 indent level is 3 Comprising only Group II-IV compound (EPO)
   E33.051          Subclass E33.051 indent level is 2 Having Schottky barrier (EPO)
   E33.052          Subclass E33.052 indent level is 2 Having MIS barrier layer (EPO)
   E33.053          Subclass E33.053 indent level is 2 Characterized by field-effect operation (EPO)
   E33.054          Subclass E33.054 indent level is 2 Device being superluminescent diode (EPO)
   E33.055          Subclass E33.055 indent level is 1 Detail of nonsemiconductor component other than light-emitting semiconductor device (EPO)
   E33.056          Subclass E33.056 indent level is 2 Packaging (EPO)
   E33.057          Subclass E33.057 indent level is 3 Adapted for surface mounting (EPO)
   E33.058          Subclass E33.058 indent level is 3 Housing (EPO)
   E33.059          Subclass E33.059 indent level is 3 Encapsulation (EPO)
   E33.06          Subclass E33.06 indent level is 2 Coatings (EPO)
   E33.061          Subclass E33.061 indent level is 3 Comprising luminescent material (e.g., fluorescent) (EPO)
   E33.062          Subclass E33.062 indent level is 2 Electrodes (EPO)
   E33.063          Subclass E33.063 indent level is 3 Characterized by material (EPO)
   E33.064          Subclass E33.064 indent level is 4 Comprising transparent conductive layers (e.g., transparent conductive oxides (TCO), indium tin oxide (ITO)) (EPO)
   E33.065          Subclass E33.065 indent level is 3 Characterized by shape (EPO)
   E33.066          Subclass E33.066 indent level is 2 Electrical contact or lead (e.g., lead frame) (EPO)
   E33.067          Subclass E33.067 indent level is 2 Means for light extraction or guiding (EPO)
   E33.068          Subclass E33.068 indent level is 3 Integrated with device (e.g., back surface reflector, lens) (EPO)
   E33.069          Subclass E33.069 indent level is 4 Comprising resonant cavity structure (e.g., Bragg reflector pair) (EPO)
   E33.07          Subclass E33.07 indent level is 4 Comprising window layer (EPO)
   E33.071          Subclass E33.071 indent level is 3 Not integrated with device (EPO)
   E33.072          Subclass E33.072 indent level is 4 Reflective means (EPO)
   E33.073          Subclass E33.073 indent level is 4 Refractive means (e.g., lens) (EPO)
   E33.074          Subclass E33.074 indent level is 3 Scattering means (e.g., surface roughening) (EPO)
   E33.075          Subclass E33.075 indent level is 2 With means for cooling or heating (EPO)
   E33.076          Subclass E33.076 indent level is 2 With means for light detecting (e.g., photodetector) (EPO)
   E33.077          Subclass E33.077 indent level is 2 Monolithic integration with photosensitive device (EPO)
   E31.001          SEMICONDUCTOR DEVICES RESPONSIVE OR SENSITIVE TO ELECTROMAGNETIC RADIATION (E.G., INFRARED RADIATION, ADAPTED FOR CONVERSION OF RADIATION INTO ELECTRICAL ENERGY OR FOR CONTROL OF ELECTRICAL ENERGY BY SUCH RADIATION PROCESSES, OR APPARATUS PECULIAR TO MANUFACTURE OR TREATMENT OF SUCH DEVICES, OR OF PARTS THEREOF) (EPO)
   E31.002          Subclass E31.002 indent level is 1 Characterized by semiconductor body (EPO)
   E31.003          Subclass E31.003 indent level is 2 Characterized by semiconductor body material (EPO)
   E31.004          Subclass E31.004 indent level is 3 Inorganic materials (EPO)
   E31.005          Subclass E31.005 indent level is 4 In different semiconductor regions (e.g., Cu 2 X/CdX heterojunction and X being Group VI element) (EPO)
   E31.006          Subclass E31.006 indent level is 5 Comprising only Cu 2 X/CdX heterojunction and X being Group VI element (EPO)
   E31.007          Subclass E31.007 indent level is 5 Comprising only heterojunction including Group I-III-VI compound (e.g., CdS/CuInSe 2 heterojunction) (EPO)
   E31.008          Subclass E31.008 indent level is 4 Selenium or tellurium (EPO)
   E31.009          Subclass E31.009 indent level is 5 For device having potential or surface barrier (EPO)
   E31.01          Subclass E31.01 indent level is 5 Characterized by doping material (EPO)
   E31.011          Subclass E31.011 indent level is 4 Including, apart from doping material or other impurity, only Group IV element (EPO)
   E31.012          Subclass E31.012 indent level is 5 For device having potential or surface barrier (EPO)
   E31.013          Subclass E31.013 indent level is 5 Comprising porous silicon as part of active layer (EPO)
   E31.014          Subclass E31.014 indent level is 5 Characterized by doping material (EPO)
   E31.015          Subclass E31.015 indent level is 4 Including, apart from doping material or other impurity, only Group II-VI compound (e.g., CdS, ZnS, HgCdTe) (EPO)
   E31.016          Subclass E31.016 indent level is 5 For device having potential or surface barrier (EPO)
   E31.017          Subclass E31.017 indent level is 6 Characterized by doping material (EPO)
   E31.018          Subclass E31.018 indent level is 5 Including ternary compound (e.g., HgCdTe) (EPO)
   E31.019          Subclass E31.019 indent level is 4 Including, apart from doping material or other impurity, only Group III-V compound (EPO)
   E31.02          Subclass E31.02 indent level is 5 For device having potential or surface barrier (EPO)
   E31.021          Subclass E31.021 indent level is 6 Characterized by doping material GaAlAs, InGaAs, InGaAsP (EPO)
   E31.022          Subclass E31.022 indent level is 5 Including ternary or quaternary compound (EPO)
   E31.023          Subclass E31.023 indent level is 4 Including, apart from doping material or other impurity, only Group IV compound (e.g., SiC) (EPO)
   E31.024          Subclass E31.024 indent level is 5 For device having potential or surface barrier (EPO)
   E31.025          Subclass E31.025 indent level is 5 Characterized by doping material (EPO)
   E31.026          Subclass E31.026 indent level is 4 Including, apart from doping material or other impurity, only compound other than Group II-VI, III-V, and IV compound (EPO)
   E31.027          Subclass E31.027 indent level is 5 Comprising only Group I-III-VI chalcopyrite compound (e.g., CuInSe 2 , CuGaSe 2 , CuInGaSe 2 ) (EPO)
   E31.028          Subclass E31.028 indent level is 6 Characterized by doping material (EPO)
   E31.029          Subclass E31.029 indent level is 5 Comprising only Group IV-VI or II-IV-VI chalcogenide compound (e.g., PbSnTe) (EPO)
   E31.03          Subclass E31.03 indent level is 6 Characterized by doping material (EPO)
   E31.031          Subclass E31.031 indent level is 5 Characterized by doping material (EPO)
   E31.032          Subclass E31.032 indent level is 2 Characterized by semiconductor body shape, relative size, or disposition of semiconductor regions (EPO)
   E31.033          Subclass E31.033 indent level is 3 Multiple quantum well structure (EPO)
   E31.034          Subclass E31.034 indent level is 4 Characterized by amorphous semiconductor layer (EPO)
   E31.035          Subclass E31.035 indent level is 4 Including, apart from doping material or other impurity, only Group IV element or compound (e.g., Si-SiGe superlattice) (EPO)
   E31.036          Subclass E31.036 indent level is 4 Doping superlattice (e.g., nipi superlattice) (EPO)
   E31.037          Subclass E31.037 indent level is 3 For device having potential or surface barrier (EPO)
   E31.038          Subclass E31.038 indent level is 4 Shape of body (EPO)
   E31.039          Subclass E31.039 indent level is 4 Shape of potential or surface barrier (EPO)
   E31.04          Subclass E31.04 indent level is 2 Characterized by semiconductor body crystalline structure or plane (EPO)
   E31.041          Subclass E31.041 indent level is 3 Including thin film deposited on metallic or insulating substrate (EPO)
   E31.042          Subclass E31.042 indent level is 4 Including only Group IV element (EPO)
   E31.043          Subclass E31.043 indent level is 3 Including polycrystalline semiconductor (EPO)
   E31.044          Subclass E31.044 indent level is 4 Including only Group IV element (EPO)
   E31.045          Subclass E31.045 indent level is 5 Including microcrystalline silicon ( c-Si) (EPO)
   E31.046          Subclass E31.046 indent level is 5 Including microcrystalline Group IV compound (e.g., c-SiGe, c-SiC) (EPO)
   E31.047          Subclass E31.047 indent level is 3 Including amorphous semiconductor (EPO)
   E31.048          Subclass E31.048 indent level is 4 Including only Group IV element (EPO)
   E31.049          Subclass E31.049 indent level is 5 Including Group IV compound (e.g., SiGe, SiC) (EPO)
   E31.05          Subclass E31.05 indent level is 5 Having light-induced characteristic variation (e.g., Staebler-Wronski effect) (EPO)
   E31.051          Subclass E31.051 indent level is 3 Including other nonmonocrystalline material (e.g., semiconductor particles embedded in insulating material) (EPO)
   E31.052          Subclass E31.052 indent level is 1 Adapted to control current flow through device (e.g., photoresistor) (EPO)
   E31.053          Subclass E31.053 indent level is 2 For device having potential or surface barrier (e.g., phototransistor) (EPO)
   E31.054          Subclass E31.054 indent level is 3 Device sensitive to infrared, visible, or ultraviolet radiation (EPO)
   E31.055          Subclass E31.055 indent level is 4 Characterized by only one potential or surface barrier (EPO)
   E31.056          Subclass E31.056 indent level is 5 Potential barrier being of point contact type (EPO)
   E31.057          Subclass E31.057 indent level is 5 PN homojunction potential barrier (EPO)
   E31.058          Subclass E31.058 indent level is 6 Device comprising active layer formed only by Group II-VI compound (e.g., HgCdTe IR photodiode) (EPO)
   E31.059          Subclass E31.059 indent level is 6 Device comprising active layer formed only by Group III-V compound (EPO)
   E31.06          Subclass E31.06 indent level is 6 Device comprising active layer formed only by Group IV compound (EPO)
   E31.061          Subclass E31.061 indent level is 5 PIN potential barrier (EPO)
   E31.062          Subclass E31.062 indent level is 6 Device comprising Group IV amorphous material (EPO)
   E31.063          Subclass E31.063 indent level is 5 Potential barrier working in avalanche mode (e.g., avalanche photodiode) (EPO)
   E31.064          Subclass E31.064 indent level is 6 Heterostructure (e.g., surface absorption or multiplication (SAM) layer) (EPO)
   E31.065          Subclass E31.065 indent level is 5 Schottky potential barrier (EPO)
   E31.066          Subclass E31.066 indent level is 6 Metal-semiconductor-metal (MSM) Schottky barrier (EPO)
   E31.067          Subclass E31.067 indent level is 5 PN heterojunction potential barrier (EPO)
   E31.068          Subclass E31.068 indent level is 4 Characterized by two potential or surface barriers (EPO)
   E31.069          Subclass E31.069 indent level is 5 Bipolar phototransistor (EPO)
   E31.07          Subclass E31.07 indent level is 4 Characterized by at least three potential barriers (EPO)
   E31.071          Subclass E31.071 indent level is 5 Photothyristor (EPO)
   E31.072          Subclass E31.072 indent level is 6 Static induction type (i.e., SIT device) (EPO)
   E31.073          Subclass E31.073 indent level is 4 Field-effect type (e.g., junction field-effect phototransistor) (EPO)
   E31.074          Subclass E31.074 indent level is 5 With Schottky gate (EPO)
   E31.075          Subclass E31.075 indent level is 6 Charge-coupled device (CCD) (EPO)
   E31.076          Subclass E31.076 indent level is 6 Photo MESFET (EPO)
   E31.077          Subclass E31.077 indent level is 5 With PN homojunction gate (EPO)
   E31.078          Subclass E31.078 indent level is 6 Charge-coupled device (CCD) (EPO)
   E31.079          Subclass E31.079 indent level is 6 Field-effect phototransistor (EPO)
   E31.08          Subclass E31.08 indent level is 5 With PN heterojunction gate (EPO)
   E31.081          Subclass E31.081 indent level is 6 Charge-coupled device (CCD) (EPO)
   E31.082          Subclass E31.082 indent level is 6 Field-effect phototransistor (EPO)
   E31.083          Subclass E31.083 indent level is 5 Conductor-insulator-semiconductor type (EPO)
   E31.084          Subclass E31.084 indent level is 6 Diode or charge-coupled device (CCD) (EPO)
   E31.085          Subclass E31.085 indent level is 6 Metal-insulator-semiconductor field-effect transistor (EPO)
   E31.086          Subclass E31.086 indent level is 3 Device sensitive to very short wavelength (e.g., X-ray, gamma-ray, or corpuscular radiation) (EPO)
   E31.087          Subclass E31.087 indent level is 4 Bulk-effect radiation detector (e.g., Ge-Li compensated PIN gamma-ray detector) (EPO)
   E31.088          Subclass E31.088 indent level is 5 Li-compensated PIN gamma-ray detector (EPO)
   E31.089          Subclass E31.089 indent level is 4 With surface barrier or shallow PN junction (e.g., surface barrier alpha-particle detector) (EPO)
   E31.09          Subclass E31.09 indent level is 5 With shallow PN junction (EPO)
   E31.091          Subclass E31.091 indent level is 4 Field-effect type (e.g., MIS-type detector) (EPO)
   E31.092          Subclass E31.092 indent level is 2 Device being sensitive to very short wavelength (e.g., X-ray, gamma-ray) (EPO)
   E31.093          Subclass E31.093 indent level is 2 Device sensitive to infrared, visible, or ultraviolet radiation (EPO)
   E31.094          Subclass E31.094 indent level is 3 Comprising amorphous semiconductor (EPO)
   E31.095          Subclass E31.095 indent level is 1 Structurally associated with electric light source (e.g., electroluminescent light source) (EPO)
   E31.096          Subclass E31.096 indent level is 2 Hybrid device containing photosensitive and electroluminescent components within one single body (EPO)
   E31.097          Subclass E31.097 indent level is 2 Light source controlled by radiation-sensitive semiconductor device (e.g., image converter, image amplifier, image storage device) (EPO)
   E31.098          Subclass E31.098 indent level is 3 Device without potential or surface barrier (EPO)
   E31.099          Subclass E31.099 indent level is 4 Light source being semiconductor device with potential or surface barrier (e.g., light-emitting diode) (EPO)
   E31.1          Subclass E31.1 indent level is 3 Device with potential or surface barrier (EPO)
   E31.101          Subclass E31.101 indent level is 3 Semiconductor light source and radiation-sensitive semiconductor device both having potential or surface barrier (EPO)
   E31.102          Subclass E31.102 indent level is 4 Formed in or on common substrate (EPO)
   E31.103          Subclass E31.103 indent level is 2 Radiation-sensitive semiconductor device controlled by light source (EPO)
   E31.104          Subclass E31.104 indent level is 3 Radiation-sensitive semiconductor device without potential or surface barrier (e.g., photoresistor) (EPO)
   E31.105          Subclass E31.105 indent level is 4 Light source being semiconductor device having potential or surface barrier (e.g., light-emitting diode) (EPO)
   E31.106          Subclass E31.106 indent level is 4 Optical potentiometer (EPO)
   E31.107          Subclass E31.107 indent level is 3 Radiation-sensitive semiconductor device with potential or surface barrier (EPO)
   E31.108          Subclass E31.108 indent level is 3 Semiconductor light source and radiation-sensitive semiconductor device both having potential or surface barrier (EPO)
   E31.109          Subclass E31.109 indent level is 4 Formed in or on common substrate (EPO)
   E31.11          Subclass E31.11 indent level is 1 Detail of nonsemiconductor component of radiation-sensitive semiconductor device (EPO)
   E31.111          Subclass E31.111 indent level is 2 Input/output circuit of device (EPO)
   E31.112          Subclass E31.112 indent level is 3 For device having potential or surface barrier (EPO)
   E31.113          Subclass E31.113 indent level is 2 Circuit arrangement of general character for device (EPO)
   E31.114          Subclass E31.114 indent level is 3 For device having potential or surface barrier (EPO)
   E31.115          Subclass E31.115 indent level is 4 Position-sensitive and lateral-effect photodetector (e.g., quadrant photodiode) (EPO)
   E31.116          Subclass E31.116 indent level is 4 Device working in avalanche mode (EPO)
   E31.117          Subclass E31.117 indent level is 2 Encapsulation (EPO)
   E31.118          Subclass E31.118 indent level is 3 For device having potential or surface barrier (EPO)
   E31.119          Subclass E31.119 indent level is 2 Coatings (EPO)
   E31.12          Subclass E31.12 indent level is 3 For device having potential or surface barrier (EPO)
   E31.121          Subclass E31.121 indent level is 4 For filtering or shielding light (e.g., multicolor filter for photodetector) (EPO)
   E31.122          Subclass E31.122 indent level is 5 For shielding light (e.g., light-blocking layer, cold shield for infrared detector) (EPO)
   E31.123          Subclass E31.123 indent level is 5 For interference filter (e.g., multilayer dielectric filter) (EPO)
   E31.124          Subclass E31.124 indent level is 2 Electrode (EPO)
   E31.125          Subclass E31.125 indent level is 3 For device having potential or surface barrier (EPO)
   E31.126          Subclass E31.126 indent level is 3 Transparent conductive layer (e.g., transparent conductive oxide (TCO), indium tin oxide (ITO) layer) (EPO)
   E31.127          Subclass E31.127 indent level is 2 Optical element associated with device (EPO)
   E31.128          Subclass E31.128 indent level is 3 Device having potential or surface barrier (EPO)
   E31.129          Subclass E31.129 indent level is 3 Comprising luminescent member (e.g., fluorescent sheet) (EPO)
   E31.13          Subclass E31.13 indent level is 2 Texturized surface (EPO)
   E31.131          Subclass E31.131 indent level is 2 Arrangement for temperature regulation (e.g., cooling, heating, or ventilating) (EPO)
   E27.001          DEVICE CONSISTING OF A PLURALITY OF SEMICONDUCTOR OR OTHER SOLID STATE COMPONENTS FORMED IN OR ON A COMMON SUBSTRATE, E.G., INTEGRATED CIRCUIT DEVICE (EPO)
   E27.002          Subclass E27.002 indent level is 1 Including bulk negative resistance effect component (EPO)
   E27.003          Subclass E27.003 indent level is 2 Including Gunn-effect device (EPO)
   E27.004          Subclass E27.004 indent level is 1 Including solid state component for rectifying, amplifying, or switching without a potential barrier or surface barrier (EPO)
   E27.005          Subclass E27.005 indent level is 1 Including component using galvano-magnetic effects, e.g. Hall effect (EPO)
   E27.006          Subclass E27.006 indent level is 1 Including piezo-electric, electro-resistive, or magneto-resistive component (EPO)
   E27.007          Subclass E27.007 indent level is 1 Including superconducting component (EPO)
   E27.008          Subclass E27.008 indent level is 1 Including thermo-electric or thermo-magnetic component with or without a junction of dissimilar material or thermo-magnetic component (EPO)
   E27.009          Subclass E27.009 indent level is 1 Including semiconductor component with at least one potential barrier or surface barrier adapted for rectifying, oscillating, amplifying, or switching, or Including integrated passive circuit elements (EPO)
   E27.01          Subclass E27.01 indent level is 2 With semiconductor substrate only (EPO)
   E27.011          Subclass E27.011 indent level is 3 Including a plurality of components in a non-repetitive configuration (EPO)
   E27.012          Subclass E27.012 indent level is 4 Made of compound semiconductor material, e.g. III-V material (EPO)
   E27.013          Subclass E27.013 indent level is 4 Integrated circuit having a two-dimensional layout of components without a common active region (EPO)
   E27.014          Subclass E27.014 indent level is 5 Including a field-effect type component (EPO)
   E27.015          Subclass E27.015 indent level is 6 In combination with bipolar transistor (EPO)
   E27.016          Subclass E27.016 indent level is 6 In combination with diode, resistor, or capacitor (EPO)
   E27.017          Subclass E27.017 indent level is 6 In combination with bipolar transistor and diode, resistor, or capacitor (EPO)
   E27.018          Subclass E27.018 indent level is 5 With component other than field-effect type (EPO)
   E27.019          Subclass E27.019 indent level is 6 Bipolar transistor in combination with diode, capacitor, or resistor (EPO)
   E27.02          Subclass E27.02 indent level is 7 Vertical bipolar transistor in combination with diode, capacitor, or resistor (EPO)
   E27.021          Subclass E27.021 indent level is 8 Vertical bipolar transistor in combination with resistor or capacitor only (EPO)
   E27.022          Subclass E27.022 indent level is 8 Vertical bipolar transistor in combination with diode only (EPO)
   E27.023          Subclass E27.023 indent level is 7 Lateral bipolar transistor in combination with diode, capacitor, or resistor (EPO)
   E27.024          Subclass E27.024 indent level is 6 Including combination of diode, capacitor, or resistor (EPO)
   E27.025          Subclass E27.025 indent level is 7 Including combination of capacitor or resistor only (EPO)
   E27.026          Subclass E27.026 indent level is 4 Integrated circuit having a three-dimensional layout (EPO)
   E27.027          Subclass E27.027 indent level is 5 Including components formed on opposite sides of a semiconductor substrate (EPO)
   E27.028          Subclass E27.028 indent level is 4 Including component having an active region in common (EPO)
   E27.029          Subclass E27.029 indent level is 5 Including component of the field-effect type (EPO)
   E27.03          Subclass E27.03 indent level is 6 In combination with bipolar transistor and diode, capacitor, or resistor (EPO)
   E27.031          Subclass E27.031 indent level is 7 In combination with vertical bipolar transistor and diode, capacitor, or resistor (EPO)
   E27.032          Subclass E27.032 indent level is 7 In combination with lateral bipolar transistor and diode, capacitor, or resistor (EPO)
   E27.033          Subclass E27.033 indent level is 6 In combination with diode, capacitor, or resistor (EPO)
   E27.034          Subclass E27.034 indent level is 7 In combination with capacitor only (EPO)
   E27.035          Subclass E27.035 indent level is 7 In combination with resistor only (EPO)
   E27.036          Subclass E27.036 indent level is 5 With component other than field-effect type (EPO)
   E27.037          Subclass E27.037 indent level is 6 Bipolar transistor in combination with diode, capacitor, or resistor (EPO)
   E27.038          Subclass E27.038 indent level is 7 Vertical bipolar transistor in combination with diode, capacitor, or resistor (EPO)
   E27.039          Subclass E27.039 indent level is 8 Vertical bipolar transistor in combination with diode only (EPO)
   E27.04          Subclass E27.04 indent level is 9 With Schottky diode only (EPO)
   E27.041          Subclass E27.041 indent level is 8 Vertical bipolar transistor in combination with resistor only (EPO)
   E27.042          Subclass E27.042 indent level is 8 Vertical bipolar transistor in combination with capacitor only (EPO)
   E27.043          Subclass E27.043 indent level is 7 Lateral bipolar transistor in combination with diode, capacitor, or resistor (EPO)
   E27.044          Subclass E27.044 indent level is 6 Including combination of diode, capacitor, or resistor (EPO)
   E27.045          Subclass E27.045 indent level is 7 Combination of capacitor and resistor (EPO)
   E27.046          Subclass E27.046 indent level is 3 Including only semiconductor components of a single kind, e.g., all bipolar transistors, all diodes, or all CMOS (EPO)
   E27.047          Subclass E27.047 indent level is 4 Resistor only (EPO)
   E27.048          Subclass E27.048 indent level is 4 Capacitor only (EPO)
   E27.049          Subclass E27.049 indent level is 5 Varactor diode (EPO)
   E27.05          Subclass E27.05 indent level is 5 Metal-insulated-semiconductor (MIS) diode (EPO)
   E27.051          Subclass E27.051 indent level is 4 Diode only (EPO)
   E27.052          Subclass E27.052 indent level is 4 Thyristor only (EPO)
   E27.053          Subclass E27.053 indent level is 4 Bipolar component only (EPO)
   E27.054          Subclass E27.054 indent level is 5 Combination of lateral and vertical transistors only (EPO)
   E27.055          Subclass E27.055 indent level is 5 Vertical bipolar transistor only (EPO)
   E27.056          Subclass E27.056 indent level is 6 Vertical direct transistor of the same conductivity type having different characteristics, (e.g. Darlington transistor) (EPO)
   E27.057          Subclass E27.057 indent level is 6 Vertical complementary transistor (EPO)
   E27.058          Subclass E27.058 indent level is 6 Combination of direct and inverse vertical transistors (e.g., collector acts as emitter) (EPO)
   E27.059          Subclass E27.059 indent level is 4 Including field-effect component only (EPO)
   E27.06          Subclass E27.06 indent level is 5 Field-effect transistor with insulated gate (EPO)
   E27.061          Subclass E27.061 indent level is 6 Combination of depletion and enhancement field-effect transistors (EPO)
   E27.062          Subclass E27.062 indent level is 6 Complementary MIS (EPO)
   E27.063          Subclass E27.063 indent level is 7 Means for preventing a parasitic bipolar action between the different transistor regions, e.g. latch-up prevention (EPO)
   E27.064          Subclass E27.064 indent level is 7 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS (EPO)
   E27.065          Subclass E27.065 indent level is 7 Including an N-well only in the substrate (EPO)
   E27.066          Subclass E27.066 indent level is 7 Including a P-well only in the substrate (EPO)
   E27.067          Subclass E27.067 indent level is 7 Including both N- and P- wells in the substrate, e.g. twin-tub (EPO)
   E27.068          Subclass E27.068 indent level is 5 Schottky barrier gate field-effect transistor (EPO)
   E27.069          Subclass E27.069 indent level is 5 PN junction gate field-effect transistor
   E27.07          Subclass E27.07 indent level is 3 Including a plurality of individual components in a repetitive configuration (EPO)
   E27.071          Subclass E27.071 indent level is 4 Including resistor or capacitor only (EPO)
   E27.072          Subclass E27.072 indent level is 4 Including bipolar component (EPO)
   E27.073          Subclass E27.073 indent level is 5 Including diode only (EPO)
   E27.074          Subclass E27.074 indent level is 5 Including bipolar transistor (EPO)
   E27.075          Subclass E27.075 indent level is 6 Bipolar dynamic random access memory structure (EPO)
   E27.076          Subclass E27.076 indent level is 6 Array of single bipolar transistors only, e.g. read only memory structure (EPO)
   E27.077          Subclass E27.077 indent level is 6 Static bipolar memory cell structure (EPO)
   E27.078          Subclass E27.078 indent level is 6 Bipolar electrically programmable memory structure (EPO)
   E27.079          Subclass E27.079 indent level is 5 Thyristor (EPO)
   E27.08          Subclass E27.08 indent level is 5 Unijunction transistor, i.e., three terminal device with only one p-n junction having a negative resistance region in the I-V characteristic (EPO)
   E27.081          Subclass E27.081 indent level is 4 Including field-effect component (EPO)
   E27.082          Subclass E27.082 indent level is 5 Including bucket brigade type charge coupled device (C.C.D) (EPO)
   E27.083          Subclass E27.083 indent level is 5 Including charge coupled device (C.C.D) or charge injection device (C.I.D) (EPO)
   E27.084          Subclass E27.084 indent level is 5 Dynamic random access memory, DRAM, structure (EPO)
   E27.085          Subclass E27.085 indent level is 6 One-transistor memory cell structure, i.e., each memory cell containing only one transistor (EPO)
   E27.086          Subclass E27.086 indent level is 7 Storage electrode stacked over the transistor
   E27.087          Subclass E27.087 indent level is 8 With bit line higher than capacitor (EPO)
   E27.088          Subclass E27.088 indent level is 8 With capacitor higher than bit line level (EPO)
   E27.089          Subclass E27.089 indent level is 8 Storage electrode having multiple wings (EPO)
   E27.09          Subclass E27.09 indent level is 7 Capacitor extending under the transistor (EPO)
   E27.091          Subclass E27.091 indent level is 7 Transistor in trench (EPO)
   E27.092          Subclass E27.092 indent level is 7 Capacitor in trench (EPO)
   E27.093          Subclass E27.093 indent level is 8 Capacitor extending under or around the transistor (EPO)
   E27.094          Subclass E27.094 indent level is 8 Having storage electrode extension stacked over the transistor (EPO)
   E27.095          Subclass E27.095 indent level is 7 Capacitor and transistor in common trench (EPO)
   E27.096          Subclass E27.096 indent level is 8 Vertical transistor (EPO)
   E27.097          Subclass E27.097 indent level is 6 Peripheral structure (EPO)
   E27.098          Subclass E27.098 indent level is 5 Static random access memory, SRAM, structure (EPO)
   E27.099          Subclass E27.099 indent level is 6 Load element being a MOSFET transistor (EPO)
   E27.1          Subclass E27.1 indent level is 7 Load element being a thin film transistor (EPO)
   E27.101          Subclass E27.101 indent level is 6 Load element being a resistor (EPO)
   E27.102          Subclass E27.102 indent level is 5 Read-only memory, ROM, structure (EPO)
   E27.103          Subclass E27.103 indent level is 6 Electrically programmable ROM (EPO)
   E27.104          Subclass E27.104 indent level is 7 Ferroelectric non-volatile memory structure (EPO)
   E27.105          Subclass E27.105 indent level is 4 Masterslice integrated circuit (EPO)
   E27.106          Subclass E27.106 indent level is 5 Using bipolar structure (EPO)
   E27.107          Subclass E27.107 indent level is 5 Using field-effect structure (EPO)
   E27.108          Subclass E27.108 indent level is 6 CMOS gate array (EPO)
   E27.109          Subclass E27.109 indent level is 5 Using combined field-effect/bipolar structure (EPO)
   E27.11          Subclass E27.11 indent level is 5 Input and output buffer/driver (EPO)
   E27.111          Subclass E27.111 indent level is 2 Substrate comprising other than a semiconductor material, e.g. insulating substrate or layered substrate Including a non-semiconductor layer (EPO)
   E27.112          Subclass E27.112 indent level is 3 Including insulator on semiconductor, e.g. SOI (silicon on insulator) (EPO)
   E27.113          Subclass E27.113 indent level is 3 Combined with thin-film or thick-film passive component (EPO)
   E27.114          Subclass E27.114 indent level is 1 Including only passive thin-film or thick-film elements on a common insulating substrate (EPO)
   E27.115          Subclass E27.115 indent level is 2 Thick-film circuits (EPO)
   E27.116          Subclass E27.116 indent level is 2 Thin-film circuits (EPO)
   E27.117          Subclass E27.117 indent level is 1 Including organic material in active region
   E27.118          Subclass E27.118 indent level is 2 Including semiconductor components sensitive to infrared radiation, light, or electromagnetic radiation of a shorter wavelength (EPO)
   E27.119          Subclass E27.119 indent level is 2 Including semiconductor components with at least one potential barrier, surface barrier, or recombination zone adapted for light emission (EPO)
   E27.12          Subclass E27.12 indent level is 1 Including semiconductor component with at least one potential barrier or surface barrier adapted for light emission structurally associated with controlling devices having a variable impedance and not being light sensitive (EPO)
   E27.121          Subclass E27.121 indent level is 2 In a repetitive configuration (EPO)
   E27.122          Subclass E27.122 indent level is 1 Including active semiconductor component sensitive to infrared radiation, light, or electromagnetic radiation of a shorter wavelength (EPO)
   E27.123          Subclass E27.123 indent level is 2 Energy conversion device (EPO)
   E27.124          Subclass E27.124 indent level is 3 In a repetitive configuration, e.g. planar multi-junction solar cells (EPO)
   E27.125          Subclass E27.125 indent level is 4 Including only thin film solar cells deposited on a substrate (EPO)
   E27.126          Subclass E27.126 indent level is 4 Including multiple vertical junction or V-groove junction solar cells formed in a semiconductor substrate (EPO)
   E27.127          Subclass E27.127 indent level is 2 Device controlled by radiation (EPO)
   E27.128          Subclass E27.128 indent level is 3 With at least one potential barrier or surface barrier (EPO)
   E27.129          Subclass E27.129 indent level is 4 In a repetitive configuration (EPO)
   E27.13          Subclass E27.13 indent level is 3 Imager Including structural or functional details of the device (EPO)
   E27.131          Subclass E27.131 indent level is 4 Geometry or disposition of pixel-elements, address-lines, or gate-electrodes (EPO)
   E27.132          Subclass E27.132 indent level is 4 Pixel-elements with integrated switching, control, storage, or amplification elements (EPO)
   E27.133          Subclass E27.133 indent level is 4 Photodiode array or MOS imager (EPO)
   E27.134          Subclass E27.134 indent level is 5 Color imager (EPO)
   E27.135          Subclass E27.135 indent level is 6 Multicolor imager having a stacked pixel-element structure, e.g. npn, npnpn or MQW elements (EPO)
   E27.136          Subclass E27.136 indent level is 5 Infrared imager (EPO)
   E27.137          Subclass E27.137 indent level is 6 Of the hybrid type (e.g., chip-on-chip, bonded substrates) (EPO)
   E27.138          Subclass E27.138 indent level is 6 Multispectral infrared imager having a stacked pixel-element structure, e.g., npn, npnpn or MQW structures (EPO)
   E27.139          Subclass E27.139 indent level is 5 Anti-blooming (EPO)
   E27.14          Subclass E27.14 indent level is 5 X-ray, gamma-ray, or high energy radiation imager (measuring X-, gamma- or corpuscular radiation) (EPO)
   E27.141          Subclass E27.141 indent level is 4 Imager using a photoconductor layer (e.g., single photoconductor layer for all pixels) (EPO)
   E27.142          Subclass E27.142 indent level is 5 Color imager (EPO)
   E27.143          Subclass E27.143 indent level is 5 Infrared imager (EPO)
   E27.144          Subclass E27.144 indent level is 6 Of the hybrid type (e.g., chip-on-chip, bonded substrates) (EPO)
   E27.145          Subclass E27.145 indent level is 5 Anti-blooming (EPO)
   E27.146          Subclass E27.146 indent level is 5 X-ray, gamma-ray, or high energy radiation imagers (EPO)
   E27.147          Subclass E27.147 indent level is 4 Contact-type imager (e.g., contacts document surface) (EPO)
   E27.148          Subclass E27.148 indent level is 4 Junction field effect transistor (JFET) imager or static induction transistor (SIT) imager (EPO)
   E27.149          Subclass E27.149 indent level is 4 Bipolar transistor imager (EPO)
   E27.15          Subclass E27.15 indent level is 4 Charge coupled imager (EPO)
   E27.151          Subclass E27.151 indent level is 5 Structural or functional details (EPO)
   E27.152          Subclass E27.152 indent level is 6 Geometry or disposition of pixel-elements, address lines or gate-electrodes (EPO)
   E27.153          Subclass E27.153 indent level is 5 Linear CCD imager (EPO)
   E27.154          Subclass E27.154 indent level is 5 Area CCD imager (EPO)
   E27.155          Subclass E27.155 indent level is 6 Frame-interline transfer (EPO)
   E27.156          Subclass E27.156 indent level is 6 Interline transfer (EPO)
   E27.157          Subclass E27.157 indent level is 6 Frame transfer (EPO)
   E27.158          Subclass E27.158 indent level is 5 Charge injection device (CID) imager (EPO)
   E27.159          Subclass E27.159 indent level is 5 CCD or CID color imager (EPO)
   E27.16          Subclass E27.16 indent level is 5 Infrared CCD or CID imager (EPO)
   E27.161          Subclass E27.161 indent level is 6 Of the hybrid type (e.g., chip-on-chip, bonded substrates) (EPO)
   E27.162          Subclass E27.162 indent level is 5 Anti-blooming (EPO)
   E27.163          Subclass E27.163 indent level is 5 Including a photoconductive layer deposited on the CCD structure (EPO)
   E29.001          SEMICONDUCTORS DEVICES ADAPTED FOR RECTIFYING, AMPLIFYING, OSCILLATING, OR SWITCHING, CAPACITORS, OR RESISTORS WITH AT LEAST ONE POTENTIAL-JUMP BARRIER OR SURFACE BARRIER (EPO)
   E29.002          Subclass E29.002 indent level is 1 Electrical characteristics due to properties of entire semiconductor body rather than just surface region (EPO)
   E29.003          Subclass E29.003 indent level is 2 Characterized by their crystalline structure (e.g., polycrystalline, cubic) particular orientation of crystalline planes (EPO)
   E29.004          Subclass E29.004 indent level is 3 With specified crystalline planes or axis (EPO)
   E29.005          Subclass E29.005 indent level is 2 Characterized by specified shape or size of PN junction or by specified impurity concentration gradient within the device (EPO)
   E29.006          Subclass E29.006 indent level is 3 Characterized by particular design considerations to control electrical field effect within device (EPO)
   E29.007          Subclass E29.007 indent level is 4 For controlling surface leakage or electric field concentration (EPO)
   E29.008          Subclass E29.008 indent level is 5 For controlling breakdown voltage of reverse biased devices (EPO)
   E29.009          Subclass E29.009 indent level is 6 With field relief electrode (field plate) (EPO)
   E29.01          Subclass E29.01 indent level is 7 With at least two field relief electrodes used in combination and not electrically interconnected (EPO)
   E29.011          Subclass E29.011 indent level is 8 With one or more field relief electrode comprising resistance material (e.g., semi insulating material, lightly doped poly-silicon) (EPO)
   E29.012          Subclass E29.012 indent level is 6 By doping profile or shape or arrangement of the PN junction, or with supplementary regions (e.g., guard ring, LDD, drift region) (EPO)
   E29.013          Subclass E29.013 indent level is 7 With supplementary region doped oppositely to or in rectifying contact with semiconductor containing or contacting region(e.g., guard rings with PN or Schottky junction) (EPO)
   E29.014          Subclass E29.014 indent level is 7 With breakdown supporting region for localizing breakdown or limiting its voltage (EPO)
   E29.015          Subclass E29.015 indent level is 6 With insulating layer characterized by dielectric or electrostatic property (e.g., including fixed charge or semi-insulating surface layer) (EPO)
   E29.016          Subclass E29.016 indent level is 5 For preventing surface leakage due to surface inversion layer (e.g., channel stop) (EPO)
   E29.017          Subclass E29.017 indent level is 6 With field relief electrodes acting on insulator potential or insulator charges (EPO)
   E29.018          Subclass E29.018 indent level is 4 Comprising internal isolation within devices or components (EPO)
   E29.019          Subclass E29.019 indent level is 5 Isolation by PN junctions (EPO)
   E29.02          Subclass E29.02 indent level is 5 Isolation by dielectric regions (EPO)
   E29.021          Subclass E29.021 indent level is 6 For source or drain region of field-effect device (EPO)
   E29.022          Subclass E29.022 indent level is 3 Characterized by shape of semiconductor body (EPO)
   E29.023          Subclass E29.023 indent level is 4 Adapted for altering junction breakdown voltage by shape of semiconductor body (EPO)
   E29.024          Subclass E29.024 indent level is 3 Characterized by shape, relative sizes or dispositions of semiconductor regions or junctions between regions (EPO)
   E29.025          Subclass E29.025 indent level is 4 Characterized by particular shape of junction between semiconductor regions (EPO)
   E29.026          Subclass E29.026 indent level is 4 Surface layout of device (EPO)
   E29.027          Subclass E29.027 indent level is 5 Surface layout of MOS gated device (e.g., DMOSFET or IGBT) (EPO)
   E29.028          Subclass E29.028 indent level is 6 With a nonplanar gate structure (EPO)
   E29.029          Subclass E29.029 indent level is 3 With semiconductor regions connected to electrode carrying current to be rectified, amplified or switched and such electrode being part of semiconductor device which comprises three or more electrodes (EPO)
   E29.03          Subclass E29.03 indent level is 4 Emitter regions of bipolar transistors (EPO)
   E29.031          Subclass E29.031 indent level is 5 Of lateral transistors (EPO)
   E29.032          Subclass E29.032 indent level is 5 Noninterconnected multiemitter structures (EPO)
   E29.033          Subclass E29.033 indent level is 5 Of heterojunction bipolar transistors (EPO)
   E29.034          Subclass E29.034 indent level is 4 Collector regions of bipolar transistors (EPO)
   E29.035          Subclass E29.035 indent level is 5 Pedestal collectors (EPO)
   E29.036          Subclass E29.036 indent level is 4 Anode or cathode regions of thyristors or gated bipolar-mode devices (EPO)
   E29.037          Subclass E29.037 indent level is 5 Anode regions of thyristors or gated bipolar-mode devices (EPO)
   E29.038          Subclass E29.038 indent level is 5 Cathode regions of thyristors (EPO)
   E29.039          Subclass E29.039 indent level is 4 Source or drain regions of field-effect devices (EPO)
   E29.04          Subclass E29.04 indent level is 5 Of field-effect transistors with insulated gate (EPO)
   E29.041          Subclass E29.041 indent level is 5 Of field-effect transistors with Schottky gate (EPO)
   E29.042          Subclass E29.042 indent level is 4 Tunneling barrier (EPO)
   E29.043          Subclass E29.043 indent level is 3 With semiconductor regions connected to electrode not carrying current to be rectified, amplified or switched and such electrode being part of semiconductor device which comprises three or more electrodes (EPO)
   E29.044          Subclass E29.044 indent level is 4 Base region of bipolar transistors (EPO)
   E29.045          Subclass E29.045 indent level is 5 Of lateral transistors (EPO)
   E29.046          Subclass E29.046 indent level is 4 Base regions of thyristors (EPO)
   E29.047          Subclass E29.047 indent level is 5 Anode base regions of thyristors (EPO)
   E29.048          Subclass E29.048 indent level is 5 Cathode base regions of thyristors (EPO)
   E29.049          Subclass E29.049 indent level is 4 Channel region of field-effect devices (EPO)
   E29.05          Subclass E29.05 indent level is 5 Of field-effect transistors (EPO)
   E29.051          Subclass E29.051 indent level is 6 With insulated gate (EPO)
   E29.052          Subclass E29.052 indent level is 7 Nonplanar channel (EPO)
   E29.053          Subclass E29.053 indent level is 7 With nonuniform doping structure in channel region surface (EPO)
   E29.054          Subclass E29.054 indent level is 8 Doping structure being parallel to channel length (EPO)
   E29.055          Subclass E29.055 indent level is 7 With vertical doping variation (EPO)
   E29.056          Subclass E29.056 indent level is 7 With variation of composition of channel (EPO)
   E29.057          Subclass E29.057 indent level is 6 With PN junction gate
   E29.058          Subclass E29.058 indent level is 5 Of charge coupled devices (EPO)
   E29.059          Subclass E29.059 indent level is 4 Gate region of field-effect devices with PN junction gate (EPO)
   E29.06          Subclass E29.06 indent level is 4 Substrate region of field-effect devices (EPO)
   E29.061          Subclass E29.061 indent level is 5 Of field-effect transistors (EPO)
   E29.062          Subclass E29.062 indent level is 6 With insulated gate (EPO)
   E29.063          Subclass E29.063 indent level is 7 With inactive supplementary region (e.g., for preventing punch-through, improving capacity effect or leakage current) (EPO)
   E29.064          Subclass E29.064 indent level is 7 Characterized by contact structure of substrate region (EPO)
   E29.065          Subclass E29.065 indent level is 5 Of charge coupled devices (EPO)
   E29.066          Subclass E29.066 indent level is 4 Body region structure of IGFET's with channel containing layer (DMOSFET or IGBT) (EPO)
   E29.067          Subclass E29.067 indent level is 5 With nonplanar gate structure (EPO)
   E29.068          Subclass E29.068 indent level is 2 Characterized by materials of semiconductor body (EPO)
   E29.069          Subclass E29.069 indent level is 3 Single quantum well structures (EPO)
   E29.07          Subclass E29.07 indent level is 4 Quantum wire structures (EPO)
   E29.071          Subclass E29.071 indent level is 4 Quantum box or quantum dot structures (EPO)
   E29.072          Subclass E29.072 indent level is 3 Structures with periodic or quasi-periodic potential variation, (e.g., multiple quantum wells, superlattices) (EPO)
   E29.073          Subclass E29.073 indent level is 4 Doping structures (e.g., doping superlattices, nipi-superlattices) (EPO)
   E29.074          Subclass E29.074 indent level is 4 Structures without potential periodicity in direction perpendicular to major surface of substrate (e.g., lateral superlattice) (EPO)
   E29.075          Subclass E29.075 indent level is 4 Compositional structures (EPO)
   E29.076          Subclass E29.076 indent level is 5 With layered structures with quantum effects in vertical direction (EPO)
   E29.077          Subclass E29.077 indent level is 6 Comprising at least one long-range structurally disordered material (e.g., one-dimensional vertical amorphous superlattices) (EPO)
   E29.078          Subclass E29.078 indent level is 6 Comprising only semiconductor materials (EPO)
   E29.079          Subclass E29.079 indent level is 3 Two or more elements from two or more groups of Periodic Table of elements (e.g., alloys) (EPO)
   E29.08          Subclass E29.08 indent level is 4 Amorphous materials (EPO)
   E29.081          Subclass E29.081 indent level is 4 In different semiconductor regions (e.g., heterojunctions) (EPO)
   E29.082          Subclass E29.082 indent level is 3 Only element from fourth group of Periodic System in uncombined form (EPO)
   E29.083          Subclass E29.083 indent level is 4 Amorphous materials (EPO)
   E29.084          Subclass E29.084 indent level is 4 Including two or more of elements from fourth group of Periodic System (EPO)
   E29.085          Subclass E29.085 indent level is 5 In different semiconductor regions (e.g., heterojunctions) (EPO)
   E29.086          Subclass E29.086 indent level is 4 Further characterized by doping material (EPO)
   E29.087          Subclass E29.087 indent level is 3 Selenium or tellurium only (EPO)
   E29.088          Subclass E29.088 indent level is 4 Amorphous materials (EPO)
   E29.089          Subclass E29.089 indent level is 3 Only Group III-V compounds (EPO)
   E29.09          Subclass E29.09 indent level is 4 Including two or more compounds (e.g., alloys) (EPO)
   E29.091          Subclass E29.091 indent level is 5 In different semiconductor regions (e.g., heterojunctions) (EPO)
   E29.092          Subclass E29.092 indent level is 4 Amorphous materials (EPO)
   E29.093          Subclass E29.093 indent level is 4 Further characterized by doping material (EPO)
   E29.094          Subclass E29.094 indent level is 3 Only Group II-VI compounds (EPO)
   E29.095          Subclass E29.095 indent level is 4 Amorphous materials (EPO)
   E29.096          Subclass E29.096 indent level is 4 Including two or more compounds (e.g., alloys) (EPO)
   E29.097          Subclass E29.097 indent level is 5 In different semiconductor regions (e.g., heterojunctions) (EPO)
   E29.098          Subclass E29.098 indent level is 4 Further characterized by doping material (EPO)
   E29.099          Subclass E29.099 indent level is 4 CdX compounds being one element of sixth group of Periodic System (EPO)
   E29.1          Subclass E29.1 indent level is 3 Semiconductor materials other than Group IV, selenium, tellurium, or Group III-V compounds (EPO)
   E29.101          Subclass E29.101 indent level is 4 Amorphous materials (EPO)
   E29.102          Subclass E29.102 indent level is 4 Group I-VI or I-VII compounds (e.g., Cu 2 O, CuI) (EPO)
   E29.103          Subclass E29.103 indent level is 4 Pb compounds (e.g., PbO) (EPO)
   E29.104          Subclass E29.104 indent level is 4 Si compounds (e.g., SiC) (EPO)
   E29.105          Subclass E29.105 indent level is 2 Characterized by combinations of two or more features of crystalline structure, shape, materials, physical imperfections, and concentration/distribution of impurities in bulk material (EPO)
   E29.106          Subclass E29.106 indent level is 2 Characterized by physical imperfections; having polished or roughened surface (EPO)
   E29.107          Subclass E29.107 indent level is 3 Imperfections within semiconductor body (EPO)
   E29.108          Subclass E29.108 indent level is 3 Imperfections on surface of semiconductor body (EPO)
   E29.109          Subclass E29.109 indent level is 2 Characterized by concentration or distribution of impurities in bulk material (EPO)
   E29.11          Subclass E29.11 indent level is 3 Planar doping (e.g., atomic-plane doping, delta-doping) (EPO)
   E29.111          Subclass E29.111 indent level is 1 Electrodes (EPO)
   E29.112          Subclass E29.112 indent level is 2 Characterized by their shape, relative sizes or dispositions (EPO)
   E29.113          Subclass E29.113 indent level is 3 Carrying current to be rectified, amplified or switched (EPO)
   E29.114          Subclass E29.114 indent level is 4 Emitter or collector electrodes for bipolar transistors (EPO)
   E29.115          Subclass E29.115 indent level is 4 Cathode or anode electrodes for thyristors (EPO)
   E29.116          Subclass E29.116 indent level is 4 Source or drain electrodes for field-effect devices (EPO)
   E29.117          Subclass E29.117 indent level is 5 For thin film transistors with insulated gate (EPO)
   E29.118          Subclass E29.118 indent level is 5 For vertical current flow (EPO)
   E29.119          Subclass E29.119 indent level is 5 For lateral devices where connection to source or drain region is done through at least one part of semiconductor substrate thickness (e.g., with connecting sink or with via-hole) (EPO)
   E29.12          Subclass E29.12 indent level is 5 Layout configuration for lateral device source or drain region (e.g., cellular, interdigitated or ring structure or being curved or angular) (EPO)
   E29.121          Subclass E29.121 indent level is 5 Source or drain electrode in groove (EPO)
   E29.122          Subclass E29.122 indent level is 5 Characterized by relative position of source or drain electrode and gate electrode (EPO)
   E29.123          Subclass E29.123 indent level is 3 Not carrying current to be rectified, amplified, or switched (EPO)
   E29.124          Subclass E29.124 indent level is 4 Base electrodes for bipolar transistors (EPO)
   E29.125          Subclass E29.125 indent level is 4 Gate electrodes for thyristors (EPO)
   E29.126          Subclass E29.126 indent level is 4 Gate stack for field-effect devices (EPO)
   E29.127          Subclass E29.127 indent level is 5 For field-effect transistors (EPO)
   E29.128          Subclass E29.128 indent level is 6 With insulated gate (EPO)
   E29.129          Subclass E29.129 indent level is 7 Gate electrodes for transistors with floating gate (EPO)
   E29.13          Subclass E29.13 indent level is 7 Gate electrodes for nonplanar MOSFET (EPO)
   E29.131          Subclass E29.131 indent level is 8 Having drain and source regions at different vertical level having channel composed only of vertical sidewall connecting drain and source layers (EPO)
   E29.132          Subclass E29.132 indent level is 7 Characterized by insulating layer (EPO)
   E29.133          Subclass E29.133 indent level is 8 Nonuniform insulating layer thickness (EPO)
   E29.134          Subclass E29.134 indent level is 7 Characterized by configuration of gate electrode layer (EPO)
   E29.135          Subclass E29.135 indent level is 8 Characterized by length or sectional shape (EPO)
   E29.136          Subclass E29.136 indent level is 8 Characterized by surface lay-out (EPO)
   E29.137          Subclass E29.137 indent level is 7 Characterized by configuration of gate stack of thin film FETs (EPO)
   E29.138          Subclass E29.138 indent level is 5 For charge coupled devices (EPO)
   E29.139          Subclass E29.139 indent level is 2 Of specified material (EPO)
   E29.14          Subclass E29.14 indent level is 3 For gate of heterojunction field-effect devices (EPO)
   E29.141          Subclass E29.141 indent level is 3 Resistive materials for field-effect devices (EPO)
   E29.142          Subclass E29.142 indent level is 3 Superconductor materials (EPO)
   E29.143          Subclass E29.143 indent level is 3 Ohmic electrodes (EPO)
   E29.144          Subclass E29.144 indent level is 4 On Group III-V material (EPO)
   E29.145          Subclass E29.145 indent level is 5 On thin-film Group III-V material (EPO)
   E29.146          Subclass E29.146 indent level is 4 On silicon (EPO)
   E29.147          Subclass E29.147 indent level is 5 For thin-film silicon (EPO)
   E29.148          Subclass E29.148 indent level is 3 Schottky barrier electrodes (EPO)
   E29.149          Subclass E29.149 indent level is 4 On Group III-V material (EPO)
   E29.15          Subclass E29.15 indent level is 3 Electrodes for IGFET (EPO)
   E29.151          Subclass E29.151 indent level is 4 For TFT (EPO)
   E29.152          Subclass E29.152 indent level is 4 With lateral structure (e.g., poly-silicon gate with lateral doping variation or with lateral composition variation or characterized by sidewalls being composed of conductive, resistivity) (EPO)
   E29.154          Subclass E29.154 indent level is 4 Silicon gate conductor material (EPO)
   E29.155          Subclass E29.155 indent level is 5 Multiple silicon layers
   E29.156          Subclass E29.156 indent level is 6 Including silicide layer contacting silicon layer (EPO)
   E29.157          Subclass E29.157 indent level is 6 Including barrier layer between silicon and non-Si electrode
   E29.158          Subclass E29.158 indent level is 4 Elemental metal gate conductor material (e.g., W, Mo) (EPO)
   E29.159          Subclass E29.159 indent level is 5 Diverse conductors (EPO)
   E29.16          Subclass E29.16 indent level is 4 Gate conductor material being compound or alloy material (e.g., organic material, TiN, MoSi 2 ) (EPO)
   E29.161          Subclass E29.161 indent level is 5 Silicide (EPO)
   E29.162          Subclass E29.162 indent level is 4 Insulating materials for IGFET (EPO)
   E29.164          Subclass E29.164 indent level is 5 With at least one ferroelectric layer (EPO)
   E29.165          Subclass E29.165 indent level is 5 Multiple layers (EPO)
   E29.166          Subclass E29.166 indent level is 1 Types of semiconductor device (EPO)
   E29.167          Subclass E29.167 indent level is 2 Controllable by plural effects that include variations in magnetic field, mechanical force, or electric current/potential applied to device or one or more electrodes of device (EPO)
   E29.168          Subclass E29.168 indent level is 2 Quantum effect device (EPO)
   E29.169          Subclass E29.169 indent level is 2 Controllable by only signal applied to control electrode (e.g., base of bipolar transistor, gate of field-effect transistor) (EPO)
   E29.17          Subclass E29.17 indent level is 3 Memory effect devices (EPO)
   E29.171          Subclass E29.171 indent level is 3 Bipolar device (EPO)
   E29.172          Subclass E29.172 indent level is 4 Double-base diode (EPO)
   E29.173          Subclass E29.173 indent level is 4 Transistor-type device (i.e., able to continuously respond to applied control signal)
   E29.174          Subclass E29.174 indent level is 5 Bipolar junction transistor
   E29.175          Subclass E29.175 indent level is 6 Structurally associated with other devices (EPO)
   E29.176          Subclass E29.176 indent level is 6 Device being resistive element (e.g., ballasting resistor) (EPO)
   E29.177          Subclass E29.177 indent level is 6 Point contact transistors (EPO)
   E29.178          Subclass E29.178 indent level is 6 Schottky transistors (EPO)
   E29.179          Subclass E29.179 indent level is 6 Tunnel transistors (EPO)
   E29.18          Subclass E29.18 indent level is 6 Avalanche transistors (EPO)
   E29.181          Subclass E29.181 indent level is 6 Transistors with hook collector (i.e., collector having two layers of opposite conductivity type (e.g., SCR)) (EPO)
   E29.182          Subclass E29.182 indent level is 6 Bipolar thin-film transistors (EPO)
   E29.183          Subclass E29.183 indent level is 6 Vertical transistor (EPO)
   E29.184          Subclass E29.184 indent level is 7 Having emitter-base and base-collector junctions in same plane (EPO)
   E29.185          Subclass E29.185 indent level is 7 Having emitter-base junction and base-collector junction on different surfaces (e.g., mesa planar transistor) (EPO)
   E29.186          Subclass E29.186 indent level is 7 Inverse vertical transistor (EPO)
   E29.187          Subclass E29.187 indent level is 6 Lateral transistor (EPO)
   E29.188          Subclass E29.188 indent level is 6 Hetero-junction transistor (EPO)
   E29.189          Subclass E29.189 indent level is 7 Vertical transistors (EPO)
   E29.19          Subclass E29.19 indent level is 8 Having two-dimensional base (e.g., modulation-doped base, inversion layer base, delta-doped base) (EPO)
   E29.191          Subclass E29.191 indent level is 8 Having emitter comprising one or more nonmonocrystalline elements of Group IV (e.g., amorphous silicon) alloys comprising Group IV elements (EPO)
   E29.192          Subclass E29.192 indent level is 8 Resonant tunneling transistors (EPO)
   E29.193          Subclass E29.193 indent level is 8 Comprising lattice mismatched active layers (e.g., SiGe strained layer transistors) (EPO)
   E29.194          Subclass E29.194 indent level is 5 Controlled by field effect (e.g., bipolar static induction transistor (BSIT)) (EPO)
   E29.195          Subclass E29.195 indent level is 6 Gated diode structure (EPO)
   E29.196          Subclass E29.196 indent level is 7 With PN junction gate (e.g., field-controlled thyristor (FCTh), static induction thyristor (SITh)) (EPO)
   E29.197          Subclass E29.197 indent level is 6 Insulated gate bipolar mode transistor (e.g., IGBT; IGT; COMFET) (EPO)
   E29.198          Subclass E29.198 indent level is 7 Transistor with vertical current flow (EPO)
   E29.199          Subclass E29.199 indent level is 8 With both emitter and collector contacts in same substrate side (EPO)
   E29.2          Subclass E29.2 indent level is 8 With nonplanar surface (e.g., with nonplanar gate or with trench or recess or pillar in surface of emitter, base, or collector region for improving current density or short-circuiting emitter and base regions) (EPO)
   E29.201          Subclass E29.201 indent level is 9 And gate structure lying on slanted or vertical surface or formed in groove (e.g., trench gate IGBT) (EPO)
   E29.202          Subclass E29.202 indent level is 7 Thin-film device (EPO)
   E29.211          Subclass E29.211 indent level is 4 Thyristor-type device (e.g., having four-zone regenerative action) (EPO)
   E29.212          Subclass E29.212 indent level is 5 Gate-turn-off device (EPO)
   E29.213          Subclass E29.213 indent level is 6 With turn off by field effect (EPO)
   E29.214          Subclass E29.214 indent level is 7 Produced by insulated gate structure (EPO)
   E29.215          Subclass E29.215 indent level is 5 Bidirectional device (e.g., triac) (EPO)
   E29.216          Subclass E29.216 indent level is 5 With turn on by field effect (EPO)
   E29.217          Subclass E29.217 indent level is 5 Combined structurally with at least one other device (EPO)
   E29.218          Subclass E29.218 indent level is 6 Combined with capacitor or resistor (EPO)
   E29.219          Subclass E29.219 indent level is 6 Combined with diode (EPO)
   E29.22          Subclass E29.22 indent level is 7 Antiparallel diode (EPO)
   E29.221          Subclass E29.221 indent level is 6 Combined with field-effect transistor (EPO)
   E29.222          Subclass E29.222 indent level is 5 Having built-in localized breakdown/breakover region (EPO)
   E29.223          Subclass E29.223 indent level is 5 Having amplifying gate structure (e.g., Darlington configuration) (EPO)
   E29.224          Subclass E29.224 indent level is 5 Asymmetrical thyristor (EPO)
   E29.225          Subclass E29.225 indent level is 5 Lateral thyristor (EPO)
   E29.226          Subclass E29.226 indent level is 3 Unipolar device (EPO)
   E29.227          Subclass E29.227 indent level is 4 Charge transfer device (EPO)
   E29.228          Subclass E29.228 indent level is 5 Charge-coupled device (EPO)
   E29.229          Subclass E29.229 indent level is 6 With field effect produced by insulated gate (EPO)
   E29.23          Subclass E29.23 indent level is 7 Input structure (EPO)
   E29.231          Subclass E29.231 indent level is 7 Output structure (EPO)
   E29.232          Subclass E29.232 indent level is 7 Structure for improving output signal (EPO)
   E29.233          Subclass E29.233 indent level is 7 Buried channel CCD (EPO)
   E29.234          Subclass E29.234 indent level is 8 Two-phase CCD (EPO)
   E29.235          Subclass E29.235 indent level is 8 Three-phase CCD (EPO)
   E29.236          Subclass E29.236 indent level is 8 Four-phase CCD (EPO)
   E29.237          Subclass E29.237 indent level is 7 Surface channel CCD (EPO)
   E29.238          Subclass E29.238 indent level is 8 Two-phase CCD (EPO)
   E29.239          Subclass E29.239 indent level is 8 Three-phase CCD (EPO)
   E29.24          Subclass E29.24 indent level is 8 Four-phase CCD (EPO)
   E29.241          Subclass E29.241 indent level is 4 Hot electron transistor (HET) or metal base transistor (MBT) (EPO)
   E29.242          Subclass E29.242 indent level is 4 Field-effect transistor (EPO)
   E29.243          Subclass E29.243 indent level is 5 Using static field induced region (e.g., SIT, PBT) (EPO)
   E29.244          Subclass E29.244 indent level is 5 Velocity modulations transistor (i.e., VMT) (EPO)
   E29.245          Subclass E29.245 indent level is 5 With one-dimensional charge carrier gas channel (e.g., quantum wire FET) (EPO)
   E29.246          Subclass E29.246 indent level is 5 With two-dimensional charge carrier gas channel (e.g., HEMT; with two-dimensional charge-carrier layer formed at heterojunction interface) (EPO)
   E29.247          Subclass E29.247 indent level is 6 With inverted single heterostructure (i.e., with active layer formed on top of wide bandgap layer (e.g., IHEMT)) (EPO)
   E29.248          Subclass E29.248 indent level is 6 With confinement of carriers by at least two heterojunctions (e.g., DHHEMT, quantum well HEMT, DHMODFET) (EPO)
   E29.249          Subclass E29.249 indent level is 7 Using Group III-V semiconductor material (EPO)
   E29.25          Subclass E29.25 indent level is 8 With more than one donor layer (EPO)
   E29.251          Subclass E29.251 indent level is 8 With delta or planar doped donor layer (EPO)
   E29.252          Subclass E29.252 indent level is 6 With direct single heterostructure (i.e., with wide bandgap layer formed on top of active layer (e.g., direct single heterostructure MIS-like HEMT)) (EPO)
   E29.253          Subclass E29.253 indent level is 7 With wide bandgap charge-carrier supplying layer (e.g., direct single heterostructure MODFET) (EPO)
   E29.254          Subclass E29.254 indent level is 5 With delta-doped channel (EPO)
   E29.255          Subclass E29.255 indent level is 5 With field effect produced by insulated gate (EPO)
   E29.256          Subclass E29.256 indent level is 6 With channel containing layer contacting drain drift region (e.g., DMOS transistor) (EPO)
   E29.257          Subclass E29.257 indent level is 7 Having vertical bulk current component or current vertically following trench gate (e.g., vertical power DMOS transistor) (EPO)
   E29.258          Subclass E29.258 indent level is 8 With both source and drain contacts in same substrate side (EPO)
   E29.259          Subclass E29.259 indent level is 8 With nonplanar surface (EPO)
   E29.26          Subclass E29.26 indent level is 9 Channel structure lying under slanted or vertical surface or being formed along surface of groove (e.g., trench gate DMOSFET) (EPO)
   E29.261          Subclass E29.261 indent level is 7 With at least part of active region on insulating substrate (e.g., lateral DMOS in oxide isolated well) (EPO)
   E29.262          Subclass E29.262 indent level is 6 Vertical transistor (EPO)
   E29.263          Subclass E29.263 indent level is 6 Comprising gate-to-body connection (i.e., bulk dynamic threshold voltage MOSFET) (EPO)
   E29.264          Subclass E29.264 indent level is 6 With multiple gate structure (EPO)
   E29.265          Subclass E29.265 indent level is 7 Structure comprising MOS gate and at least one non-MOS gate (e.g., JFET or MESFET gate) (EPO)
   E29.266          Subclass E29.266 indent level is 6 With lightly doped drain or source extension (EPO)
   E29.267          Subclass E29.267 indent level is 7 With nonplanar structure (e.g., gate or source or drain being nonplanar) (EPO)
   E29.268          Subclass E29.268 indent level is 7 Source region and drain region having nonsymmetrical structure about gate electrode (EPO)
   E29.269          Subclass E29.269 indent level is 7 With overlap between lightly doped extension and gate electrode (EPO)
   E29.27          Subclass E29.27 indent level is 6 With buried channel (EPO)
   E29.271          Subclass E29.271 indent level is 6 With Schottky drain or source contact (EPO)
   E29.272          Subclass E29.272 indent level is 6 Gate comprising ferroelectric layer (EPO)
   E29.273          Subclass E29.273 indent level is 6 Thin-film transistor (EPO)
   E29.274          Subclass E29.274 indent level is 7 Vertical transistor (EPO)
   E29.275          Subclass E29.275 indent level is 7 With multiple gates (EPO)
   E29.276          Subclass E29.276 indent level is 7 With supplementary region or layer in thin film or in insulated bulk substrate supporting it for controlling or increasing voltage resistance of device (EPO)
   E29.277          Subclass E29.277 indent level is 8 Characterized by drain or source properties (EPO)
   E29.278          Subclass E29.278 indent level is 9 With LDD structure or extension or offset region or characterized by doping profile (EPO)
   E29.279          Subclass E29.279 indent level is 10 Asymmetrical source and drain regions (EPO)
   E29.28          Subclass E29.28 indent level is 8 For preventing leakage current (EPO)
   E29.281          Subclass E29.281 indent level is 8 For preventing kink or snapback effect (e.g., discharging minority carriers of channel region for preventing bipolar effect) (EPO)
   E29.282          Subclass E29.282 indent level is 8 With light shield (EPO)
   E29.283          Subclass E29.283 indent level is 8 With supplementary region or layer for improving flatness of device (EPO)
   E29.284          Subclass E29.284 indent level is 8 With drain or source connected to bulk conducting substrate (EPO)
   E29.285          Subclass E29.285 indent level is 7 Silicon transistor (EPO)
   E29.286          Subclass E29.286 indent level is 8 Monocrystalline only (EPO)
   E29.287          Subclass E29.287 indent level is 9 SOS transistor (EPO)
   E29.288          Subclass E29.288 indent level is 8 Nonmonocrystalline (EPO)
   E29.289          Subclass E29.289 indent level is 9 Amorphous silicon transistor (EPO)
   E29.29          Subclass E29.29 indent level is 10 With top gate (EPO)
   E29.291          Subclass E29.291 indent level is 10 With inverted transistor structure (EPO)
   E29.292          Subclass E29.292 indent level is 9 Polycrystalline or microcrystalline silicon transistor (EPO)
   E29.293          Subclass E29.293 indent level is 10 With top gate (EPO)
   E29.294          Subclass E29.294 indent level is 10 With inverted transistor structure (EPO)
   E29.295          Subclass E29.295 indent level is 7 Characterized by insulating substrate or support (EPO)
   E29.296          Subclass E29.296 indent level is 7 Comprising Group III-V or II-VI compound, or of Se, Te, or oxide semiconductor (EPO)
   E29.297          Subclass E29.297 indent level is 7 Comprising Group IV non-Si semiconductor materials or alloys (e.g., Ge, SiN alloy, SiC alloy) (EPO)
   E29.298          Subclass E29.298 indent level is 8 With multilayer structure or superlattice structure (EPO)
   E29.299          Subclass E29.299 indent level is 7 Characterized by property or structure of channel or contact thereto (EPO)
   E29.3          Subclass E29.3 indent level is 6 With floating gate (EPO)
   E29.301          Subclass E29.301 indent level is 7 Programmable by two single electrons (EPO)
   E29.302          Subclass E29.302 indent level is 7 Hi-lo programming levels only (EPO)
   E29.303          Subclass E29.303 indent level is 8 Charging by injection of carriers through conductive insulator (e.g., Poole-Frankel conduction) (EPO)
   E29.304          Subclass E29.304 indent level is 8 Charging by tunneling of carriers (e.g., Fowler-Nordheim tunneling) (EPO)
   E29.305          Subclass E29.305 indent level is 8 Charging by hot carrier injection (EPO)
   E29.306          Subclass E29.306 indent level is 9 Hot carrier injection from channel (EPO)
   E29.307          Subclass E29.307 indent level is 9 Hot carrier produced by avalanche breakdown of PN junction (e.g., FAMOS) (EPO)
   E29.308          Subclass E29.308 indent level is 7 Programmable with more than two possible different levels (EPO)
   E29.309          Subclass E29.309 indent level is 6 With charge trapping gate insulator (e.g., MNOS-memory transistors) (EPO)
   E29.31          Subclass E29.31 indent level is 5 With field effect produced by PN or other rectifying junction gate (i.e., potential barrier) (EPO)
   E29.311          Subclass E29.311 indent level is 6 With Schottky drain or source contact (EPO)
   E29.312          Subclass E29.312 indent level is 6 With PN junction gate (e.g., PN homojunction gate) (EPO)
   E29.313          Subclass E29.313 indent level is 7 Vertical transistors (EPO)
   E29.314          Subclass E29.314 indent level is 7 Thin-film JFET (EPO)
   E29.315          Subclass E29.315 indent level is 6 With heterojunction gate (e.g., transistors with semiconductor layer acting as gate insulating layer) (EPO)
   E29.316          Subclass E29.316 indent level is 7 Programmable transistor (e.g., with charge-trapping quantum well) (EPO)
   E29.317          Subclass E29.317 indent level is 6 With Schottky gate (EPO)
   E29.318          Subclass E29.318 indent level is 7 Vertical transistors (EPO)
   E29.319          Subclass E29.319 indent level is 7 With multiple gate (EPO)
   E29.32          Subclass E29.32 indent level is 7 Thin-film MESFET (EPO)
   E29.321          Subclass E29.321 indent level is 7 With recessed gate (EPO)
   E29.322          Subclass E29.322 indent level is 4 Single electron transistors: Coulomb blockade device (EPO)
   E29.323          Subclass E29.323 indent level is 2 Controllable by variation of magnetic field applied to device (EPO)
   E29.324          Subclass E29.324 indent level is 2 Controllable by variation of applied mechanical force (e.g., of pressure) (EPO)
   E29.325          Subclass E29.325 indent level is 2 Controllable only by variation of electric current supplied or only electric potential applied to electrode carrying current to be rectified, amplified, oscillated, or switched (EPO)
   E29.326          Subclass E29.326 indent level is 3 Resistor with PN junction (EPO)
   E29.327          Subclass E29.327 indent level is 3 Diode (EPO)
   E29.328          Subclass E29.328 indent level is 4 Planar PN junction diode (EPO)
   E29.329          Subclass E29.329 indent level is 4 Mesa PN junction diode (EPO)
   E29.33          Subclass E29.33 indent level is 4 Hi-lo semiconductor device (e.g., memory device) (EPO)
   E29.331          Subclass E29.331 indent level is 4 Charge trapping diode (EPO)
   E29.332          Subclass E29.332 indent level is 4 Punchthrough diode (i.e., with bulk potential barrier (e.g., camel diode, planar doped barrier diode, graded bandgap diode)) (EPO)
   E29.333          Subclass E29.333 indent level is 4 Point contact diode (EPO)
   E29.334          Subclass E29.334 indent level is 4 Transit-time diode (e.g., IMPATT, TRAPATT diode) (EPO)
   E29.335          Subclass E29.335 indent level is 4 Avalanche diode (e.g., Zener diode) (EPO)
   E29.336          Subclass E29.336 indent level is 4 PIN diode (EPO)
   E29.337          Subclass E29.337 indent level is 4 Thyristor diode (i.e., having only two terminals and no control electrode (e.g., Shockley diode, break-over diode)) (EPO)
   E29.338          Subclass E29.338 indent level is 4 Schottky diode (EPO)
   E29.339          Subclass E29.339 indent level is 4 Tunneling diode (EPO)
   E29.34          Subclass E29.34 indent level is 5 Resonant tunneling diode (i.e., RTD, RTBD) (EPO)
   E29.341          Subclass E29.341 indent level is 5 Esaki diode (EPO)
   E29.342          Subclass E29.342 indent level is 3 Capacitor with potential barrier or surface barrier (EPO)
   E29.343          Subclass E29.343 indent level is 4 Conductor-insulator-conductor capacitor on semiconductor substrate (EPO)
   E29.344          Subclass E29.344 indent level is 4 Variable capacitance diode (e.g., varactors) (EPO)
   E29.345          Subclass E29.345 indent level is 4 Metal-insulator-semiconductor (e.g., MOS capacitor) (EPO)
   E29.346          Subclass E29.346 indent level is 5 Trench capacitor (EPO)
   E29.347          Subclass E29.347 indent level is 2 Controllable by thermal signal (e.g., IR) (EPO)
   E45.001          SOLID-STATE DEVICES ADAPTED FOR RECTIFYING, AMPLIFYING, OSCILLATING, OR SWITCHING WITHOUT POTENTIAL-JUMP BARRIER OR SURFACE BARRIER, E.G., DIELECTRIC TRIODES; OVSHINSKY-EFFECT DEVICES, PROCESSES, OR APPARATUS PECULIAR TO MANUFACTURE OR TREATMENT THEREOF, OR OF PARTS THEREOF (EPO)
   E45.002          Subclass E45.002 indent level is 1 Bistable switching devices, e.g., Ovshinsky-effect devices (EPO)
   E45.003          Subclass E45.003 indent level is 2 Switching materials being oxides or nitrides (EPO)
   E45.004          Subclass E45.004 indent level is 2 N: Light-controlled Ovshinsky devices (EPO)
   E45.005          Subclass E45.005 indent level is 1 Charge density wave transport devices (EPO)
   E45.006          Subclass E45.006 indent level is 1 Solid-state travelling-wave devices (EPO)
   E25.001          ASSEMBLIES CONSISTING OF PLURALITY OF INDIVIDUAL SEMICONDUCTOR OR OTHER SOLID-STATE DEVICES (EPO)
   E25.002          Subclass E25.002 indent level is 1 All devices being of same type, e.g., assemblies of rectifier diodes (EPO)
   E25.003          Subclass E25.003 indent level is 2 Devices not having separate containers (EPO)
   E25.004          Subclass E25.004 indent level is 3 Devices responsive or sensitive to electromagnetic radiation, e.g., infrared radiation, adapted for conversion of radiation into electrical energy or for control of electrical energy by such radiation (EPO)
   E25.005          Subclass E25.005 indent level is 4 Devices being arranged next to each other (EPO)
   E25.006          Subclass E25.006 indent level is 4 Stacked arrangements of devices (EPO)
   E25.007          Subclass E25.007 indent level is 5 Devices being solar cells (EPO)
   E25.008          Subclass E25.008 indent level is 3 Organic solid-state devices (EPO)
   E25.009          Subclass E25.009 indent level is 4 Devices responsive or sensitive to electromagnetic radiation, e.g., infrared radiation, adapted for conversion of radiation into electrical energy or for control of electrical energy by such radiation, e.g., photovoltaic modules based on organic solar cells (EPO)
   E25.01          Subclass E25.01 indent level is 3 Device consisting of plurality of semiconductor or other solid state devices or components formed in or on common substrate, e.g., integrated circuit device (EPO)
   E25.011          Subclass E25.011 indent level is 4 Devices being arranged next and on each other, i.e., mixed assemblies (EPO)
   E25.012          Subclass E25.012 indent level is 4 Devices being arranged next to each other (EPO)
   E25.013          Subclass E25.013 indent level is 4 Stacked arrangements of devices (EPO)
   E25.014          Subclass E25.014 indent level is 3 Semiconductor devices adapted for rectifying, amplifying, oscillating, or switching, capacitors, or resistors with at least one potential-jump barrier or surface barrier (EPO)
   E25.015          Subclass E25.015 indent level is 4 Devices being arranged next and on each other, i.e., mixed assemblies (EPO)
   E25.016          Subclass E25.016 indent level is 4 Devices being arranged next to each other (EPO)
   E25.017          Subclass E25.017 indent level is 4 Apertured devices mounted on one or more rods passed through apertures (EPO)
   E25.018          Subclass E25.018 indent level is 4 Stacked arrangements of nonapertured devices (EPO)
   E25.019          Subclass E25.019 indent level is 3 Incoherent light-emitting semiconductor devices having potential or surface barrier (EPO)
   E25.02          Subclass E25.02 indent level is 4 Devices being arranged next to each other (EPO)
   E25.021          Subclass E25.021 indent level is 4 Stacked arrangements of devices (EPO)
   E25.022          Subclass E25.022 indent level is 2 Devices having separate containers (EPO)
   E25.023          Subclass E25.023 indent level is 3 Device consisting of plurality of semiconductor or other solid-state devices or components formed in or on common substrate, e.g., integrated circuit device (EPO)
   E25.024          Subclass E25.024 indent level is 3 Semiconductors devices adapted for rectifying, amplifying, oscillating, or switching, capacitors, or resistors with at least one potential-jump barrier or surface barrier (EPO)
   E25.025          Subclass E25.025 indent level is 4 Mixed assemblies (EPO)
   E25.026          Subclass E25.026 indent level is 4 Devices being arranged next to each other (EPO)
   E25.027          Subclass E25.027 indent level is 4 Stacked arrangements of devices (EPO)
   E25.028          Subclass E25.028 indent level is 3 Incoherent light-emitting semiconductor devices having potential or surface barrier (EPO)
   E25.029          Subclass E25.029 indent level is 1 Devices being of two or more types, e.g., forming hybrid circuits (EPO)
   E25.03          Subclass E25.03 indent level is 2 Devices being mounted on two or more different substrates (EPO)
   E25.031          Subclass E25.031 indent level is 2 Containers (EPO)
   E25.032          Subclass E25.032 indent level is 2 Comprising optoelectronic devices, e.g., LED, photodiodes (EPO)
   E23.001          PACKAGING, INTERCONNECTS, AND MARKINGS FOR SEMICONDUCTOR OR OTHER SOLID-STATE DEVICES (EPO)
   E23.002          Subclass E23.002 indent level is 1 Details not otherwise provided for, e.g., protection against moisture (EPO)
   E23.003          Subclass E23.003 indent level is 1 Mountings, e.g., nondetachable insulating substrates (EPO)
   E23.004          Subclass E23.004 indent level is 2 Characterized by shape (EPO)
   E23.005          Subclass E23.005 indent level is 2 Characterized by material or its electrical properties (EPO)
   E23.006          Subclass E23.006 indent level is 3 Metallic substrates having insulating layers (EPO)
   E23.007          Subclass E23.007 indent level is 3 Organic substrates, e.g., plastic (EPO)
   E23.008          Subclass E23.008 indent level is 3 Semiconductor insulating substrates (EPO)
   E23.009          Subclass E23.009 indent level is 3 Ceramic or glass substrates (EPO)
   E23.01          Subclass E23.01 indent level is 1 Arrangements for conducting electric current to or from solid-state body in operation, e.g., leads, terminal arrangements (EPO)
   E23.011          Subclass E23.011 indent level is 2 Internal lead connections, e.g., via connections, feedthrough structures (EPO)
   E23.012          Subclass E23.012 indent level is 2 Consisting of lead-in layers inseparably applied to semiconductor body (EPO)
   E23.013          Subclass E23.013 indent level is 3 Bridge structure with air gap (EPO)
   E23.014          Subclass E23.014 indent level is 3 Beam leads (EPO)
   E23.015          Subclass E23.015 indent level is 3 Pads with extended contours, e.g., grid structure, branch structure, finger structure (EPO)
   E23.016          Subclass E23.016 indent level is 3 For devices consisting of semiconductor layers on insulating or semi-insulating substrates, e.g., silicon on sapphire devices, i.e., SOS (EPO)
   E23.017          Subclass E23.017 indent level is 3 Materials (EPO)
   E23.018          Subclass E23.018 indent level is 4 Conductive organic material or pastes, e.g., conductive adhesives, inks (EPO)
   E23.019          Subclass E23.019 indent level is 3 Consisting of layered constructions comprising conductive layers and insulating layers, e.g., planar contacts (EPO)
   E23.02          Subclass E23.02 indent level is 4 Bonding areas, e.g., pads (EPO)
   E23.021          Subclass E23.021 indent level is 4 Bump or ball contacts (EPO)
   E23.022          Subclass E23.022 indent level is 4 Overhang structure (EPO)
   E23.023          Subclass E23.023 indent level is 2 Consisting of soldered or bonded constructions (EPO)
   E23.024          Subclass E23.024 indent level is 3 Wire-like arrangements or pins or rods (EPO)
   E23.025          Subclass E23.025 indent level is 4 Characterized by materials of wires or their coatings (EPO)
   E23.026          Subclass E23.026 indent level is 3 Bases or plates or solder therefor (EPO)
   E23.027          Subclass E23.027 indent level is 4 Having heterogeneous or anisotropic structure (EPO)
   E23.028          Subclass E23.028 indent level is 4 Characterized by material (EPO)
   E23.029          Subclass E23.029 indent level is 5 Semiconductor (EPO)
   E23.03          Subclass E23.03 indent level is 5 Carbon (EPO)
   E23.031          Subclass E23.031 indent level is 3 Lead frames or other flat leads (EPO)
   E23.032          Subclass E23.032 indent level is 4 Additional leads (EPO)
   E23.033          Subclass E23.033 indent level is 5 Additional leads being bump or wire (EPO)
   E23.034          Subclass E23.034 indent level is 5 Additional leads being tape carrier or flat leads (EPO)
   E23.035          Subclass E23.035 indent level is 5 Additional leads being multilayer (EPO)
   E23.036          Subclass E23.036 indent level is 5 Additional leads being wiring board (EPO)
   E23.037          Subclass E23.037 indent level is 4 Characterized by die pad (EPO)
   E23.038          Subclass E23.038 indent level is 5 Insulative substrate being used as die pad, e.g., ceramic, plastic (EPO)
   E23.039          Subclass E23.039 indent level is 5 Chip-on-leads or leads-on-chip techniques, i.e., inner lead fingers being used as die pad (EPO)
   E23.04          Subclass E23.04 indent level is 5 Having bonding material between chip and die pad (EPO)
   E23.041          Subclass E23.041 indent level is 4 Multilayer (EPO)
   E23.042          Subclass E23.042 indent level is 4 Plurality of lead frames mounted in one device (EPO)
   E23.043          Subclass E23.043 indent level is 4 Geometry of lead frame (EPO)
   E23.044          Subclass E23.044 indent level is 5 For devices adapted for rectifying, amplifying, oscillating, or switching, capacitors, or resistors with at least one potential-jump barrier or surface barrier (EPO)
   E23.045          Subclass E23.045 indent level is 5 Deformation absorbing parts in lead frame plane, e.g., meanderline shape (EPO)
   E23.046          Subclass E23.046 indent level is 5 Cross-section geometry (EPO)
   E23.047          Subclass E23.047 indent level is 6 Characterized by bent parts (EPO)
   E23.048          Subclass E23.048 indent level is 7 Bent parts being outer leads (EPO)
   E23.049          Subclass E23.049 indent level is 5 Insulating layers on lead frame, e.g., bridging members (EPO)
   E23.05          Subclass E23.05 indent level is 6 Side rails of lead frame, e.g., with perforations, sprocket holes (EPO)
   E23.051          Subclass E23.051 indent level is 4 Specifically adapted to facilitate heat dissipation (EPO)
   E23.052          Subclass E23.052 indent level is 4 Assembly of semiconductor devices on lead frame (EPO)
   E23.053          Subclass E23.053 indent level is 4 Characterized by materials of lead frames or layers thereon (EPO)
   E23.054          Subclass E23.054 indent level is 5 Metallic layers on lead frames (EPO)
   E23.055          Subclass E23.055 indent level is 4 Consisting of thin flexible metallic tape with or without film carrier (EPO)
   E23.056          Subclass E23.056 indent level is 4 Insulating layers on lead frames (EPO)
   E23.057          Subclass E23.057 indent level is 4 Capacitor integral with or on lead frame (EPO)
   E23.058          Subclass E23.058 indent level is 4 Battery in combination with lead frame (EPO)
   E23.059          Subclass E23.059 indent level is 4 Oscillators in combination with lead frame (EPO)
   E23.06          Subclass E23.06 indent level is 3 Leads, i.e., metallizations or lead frames on insulating substrates, e.g., chip carriers (EPO)
   E23.061          Subclass E23.061 indent level is 4 Leads being also applied on sidewalls or bottom of substrate, e.g., leadless packages for surface mounting (EPO)
   E23.062          Subclass E23.062 indent level is 4 Multilayer substrates (EPO)
   E23.063          Subclass E23.063 indent level is 4 Chip support structure consisting of plurality of insulating substrates (EPO)
   E23.064          Subclass E23.064 indent level is 4 For flat cards, e.g., credit cards (EPO)
   E23.065          Subclass E23.065 indent level is 4 Flexible insulating substrates (EPO)
   E23.066          Subclass E23.066 indent level is 4 Lead frames fixed on or encapsulated in insulating substrates (EPO)
   E23.067          Subclass E23.067 indent level is 4 Via connections through substrates, e.g., pins going through substrate, coaxial cables (EPO)
   E23.068          Subclass E23.068 indent level is 4 Additional leads joined to metallizations on insulating substrate, e.g., pins, bumps, wires, flat leads (EPO)
   E23.069          Subclass E23.069 indent level is 5 Spherical bumps on substrate for external connection, e.g., ball grid arrays (BGA) (EPO)
   E23.07          Subclass E23.07 indent level is 4 Geometry or layout (EPO)
   E23.071          Subclass E23.071 indent level is 5 For devices adapted for rectifying, amplifying, oscillating, or switching, capacitors, or resistors with at least one potential-jump barrier or surface barrier (EPO)
   E23.072          Subclass E23.072 indent level is 4 Characterized by materials (EPO)
   E23.073          Subclass E23.073 indent level is 5 Conductive materials containing semiconductor material (EPO)
   E23.074          Subclass E23.074 indent level is 5 Carbon, e.g., fullerenes (EPO)
   E23.075          Subclass E23.075 indent level is 5 Conductive materials containing organic materials or pastes, e.g., for thick films (EPO)
   E23.076          Subclass E23.076 indent level is 5 Conductive materials containing superconducting material (EPO)
   E23.077          Subclass E23.077 indent level is 5 Materials of insulating layers or coatings (EPO)
   E23.078          Subclass E23.078 indent level is 2 Flexible arrangements, e.g., pressure contacts without soldering (EPO)
   E23.079          Subclass E23.079 indent level is 2 For integrated circuit devices, e.g., power bus, number of leads (EPO)
   E23.08          Subclass E23.08 indent level is 1 Arrangements for cooling, heating, ventilating or temperature compensation; temperature-sensing arrangements (EPO)
   E23.081          Subclass E23.081 indent level is 2 Arrangements for heating (EPO)
   E23.082          Subclass E23.082 indent level is 2 Cooling arrangements using Peltier effect (EPO)
   E23.083          Subclass E23.083 indent level is 2 Mountings or securing means for detachable cooling or heating arrangements; fixed by friction, plugs or springs (EPO)
   E23.084          Subclass E23.084 indent level is 3 With bolts or screws (EPO)
   E23.085          Subclass E23.085 indent level is 4 For stacked arrangements of plurality of semiconductor devices (EPO)
   E23.086          Subclass E23.086 indent level is 3 Snap-on arrangements, e.g., clips (EPO)
   E23.087          Subclass E23.087 indent level is 2 Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling (EPO)
   E23.088          Subclass E23.088 indent level is 3 Cooling by change of state, e.g., use of heat pipes (EPO)
   E23.089          Subclass E23.089 indent level is 4 By melting or evaporation of solids (EPO)
   E23.09          Subclass E23.09 indent level is 3 Auxiliary members in containers characterized by their shape, e.g., pistons (EPO)
   E23.091          Subclass E23.091 indent level is 4 Bellows (EPO)
   E23.092          Subclass E23.092 indent level is 4 Auxiliary members in encapsulations (EPO)
   E23.093          Subclass E23.093 indent level is 4 In combination with jet impingement (EPO)
   E23.094          Subclass E23.094 indent level is 4 Pistons, e.g., spring-loaded members (EPO)
   E23.095          Subclass E23.095 indent level is 2 Complete device being wholly immersed in fluid other than air (EPO)
   E23.096          Subclass E23.096 indent level is 3 Fluid being liquefied gas, e.g., in cryogenic vessel (EPO)
   E23.097          Subclass E23.097 indent level is 2 Involving transfer of heat by flowing fluids (EPO)
   E23.098          Subclass E23.098 indent level is 3 By flowing liquids (EPO)
   E23.099          Subclass E23.099 indent level is 3 By flowing gases, e.g., air (EPO)
   E23.1          Subclass E23.1 indent level is 4 Jet impingement (EPO)
   E23.101          Subclass E23.101 indent level is 2 Selection of materials, or shaping, to facilitate cooling or heating, e.g., heat sinks (EPO)
   E23.102          Subclass E23.102 indent level is 3 Cooling facilitated by shape of device (EPO)
   E23.103          Subclass E23.103 indent level is 4 Foil-like cooling fins or heat sinks (EPO)
   E23.104          Subclass E23.104 indent level is 4 Characterized by shape of housing (EPO)
   E23.105          Subclass E23.105 indent level is 4 Wire-like or pin-like cooling fins or heat sinks (EPO)
   E23.106          Subclass E23.106 indent level is 3 Laminates or multilayers, e.g., direct bond copper ceramic substrates (EPO)
   E23.107          Subclass E23.107 indent level is 4 Organic materials with or without thermo-conductive filler (EPO)
   E23.108          Subclass E23.108 indent level is 4 Semiconductor materials (EPO)
   E23.109          Subclass E23.109 indent level is 4 Metallic materials (EPO)
   E23.11          Subclass E23.11 indent level is 3 Cooling facilitated by selection of materials for device (or materials for thermal expansion adaptation, e.g., carbon) (EPO)
   E23.111          Subclass E23.111 indent level is 4 Diamond (EPO)
   E23.112          Subclass E23.112 indent level is 4 Having heterogeneous or anisotropic structure, e.g., powder or fibers in matrix, wire mesh, porous structures (EPO)
   E23.113          Subclass E23.113 indent level is 4 Ceramic materials or glass (EPO)
   E23.114          Subclass E23.114 indent level is 1 Protection against radiation, e.g., light, electromagnetic waves (EPO)
   E23.115          Subclass E23.115 indent level is 2 Against alpha rays (EPO)
   E23.116          Subclass E23.116 indent level is 1 Encapsulations, e.g., encapsulating layers, coatings, e.g., for protection (EPO)
   E23.117          Subclass E23.117 indent level is 2 Characterized by material, e.g., carbon (EPO)
   E23.118          Subclass E23.118 indent level is 3 Oxides or nitrides or carbides, e.g., ceramics, glass (EPO)
   E23.119          Subclass E23.119 indent level is 3 Organic, e.g., plastic, epoxy (EPO)
   E23.12          Subclass E23.12 indent level is 4 Organo-silicon compounds, e.g., silicone (EPO)
   E23.121          Subclass E23.121 indent level is 4 Containing filler (EPO)
   E23.122          Subclass E23.122 indent level is 3 Semiconductor material, e.g., amorphous silicon (EPO)
   E23.123          Subclass E23.123 indent level is 2 Characterized by arrangement or shape (EPO)
   E23.124          Subclass E23.124 indent level is 3 Device being completely enclosed (EPO)
   E23.125          Subclass E23.125 indent level is 4 Substrate forming part of encapsulation (EPO)
   E23.126          Subclass E23.126 indent level is 4 Double encapsulation or coating and encapsulation (EPO)
   E23.127          Subclass E23.127 indent level is 4 Sealing arrangements between parts, e.g., adhesion promoters (EPO)
   E23.128          Subclass E23.128 indent level is 4 Encapsulation having cavity (EPO)
   E23.129          Subclass E23.129 indent level is 3 Partial encapsulation or coating (EPO)
   E23.13          Subclass E23.13 indent level is 4 Coating being foil (EPO)
   E23.131          Subclass E23.131 indent level is 4 Coating or filling in grooves made in semiconductor body (EPO)
   E23.132          Subclass E23.132 indent level is 4 Coating being directly applied to semiconductor body, e.g., passivation layer (EPO)
   E23.133          Subclass E23.133 indent level is 4 Coating also covering sidewalls of semiconductor body (EPO)
   E23.134          Subclass E23.134 indent level is 4 Multilayer coating (EPO)
   E23.135          Subclass E23.135 indent level is 1 Fillings or auxiliary members in containers or encapsulations, e.g., centering rings (EPO)
   E23.136          Subclass E23.136 indent level is 2 Fillings characterized by material, its physical or chemical properties, or its arrangement within complete device (EPO)
   E23.137          Subclass E23.137 indent level is 3 Including materials for absorbing or reacting with moisture or other undesired substances, e.g., getters (EPO)
   E23.138          Subclass E23.138 indent level is 3 Gaseous at normal operating temperature of device (EPO)
   E23.139          Subclass E23.139 indent level is 3 Liquid at normal operating temperature of device (EPO)
   E23.14          Subclass E23.14 indent level is 3 Solid or gel at normal operating temperature of device (EPO)
   E23.141          Subclass E23.141 indent level is 1 Arrangements for conducting electric current within device in operation from one component to another, interconnections, e.g., wires, lead frames (EPO)
   E23.142          Subclass E23.142 indent level is 2 Including external interconnections consisting of multilayer structure of conductive and insulating layers inseparably formed on semiconductor body (EPO)
   E23.143          Subclass E23.143 indent level is 3 Crossover interconnections (EPO)
   E23.144          Subclass E23.144 indent level is 3 Capacitive arrangements or effects of, or between wiring layers (EPO)
   E23.145          Subclass E23.145 indent level is 3 Via connections in multilevel interconnection structure (EPO)
   E23.146          Subclass E23.146 indent level is 3 With adaptable interconnections (EPO)
   E23.147          Subclass E23.147 indent level is 4 Comprising antifuses, i.e., connections having their state changed from nonconductive to conductive (EPO)
   E23.148          Subclass E23.148 indent level is 5 Change of state resulting from use of external beam, e.g., laser beam or ion beam (EPO)
   E23.149          Subclass E23.149 indent level is 4 Comprising fuses, i.e., connections having their state changed from conductive to nonconductive (EPO)
   E23.15          Subclass E23.15 indent level is 5 Change of state resulting from use of external beam, e.g., laser beam or ion beam (EPO)
   E23.151          Subclass E23.151 indent level is 3 Geometry or layout of interconnection structure (EPO)
   E23.152          Subclass E23.152 indent level is 4 Cross-sectional geometry (EPO)
   E23.153          Subclass E23.153 indent level is 4 Arrangements of power or ground buses (EPO)
   E23.154          Subclass E23.154 indent level is 3 Characterized by materials (EPO)
   E23.155          Subclass E23.155 indent level is 4 Conductive materials (EPO)
   E23.156          Subclass E23.156 indent level is 5 Containing superconducting materials (EPO)
   E23.157          Subclass E23.157 indent level is 5 Based on metals, e.g., alloys, metal silicides (EPO)
   E23.158          Subclass E23.158 indent level is 6 Principal metal being aluminum (EPO)
   E23.159          Subclass E23.159 indent level is 7 Aluminum alloys (EPO)
   E23.16          Subclass E23.16 indent level is 7 Additional layers associated with aluminum layers, e.g., adhesion, barrier, cladding layers (EPO)
   E23.161          Subclass E23.161 indent level is 6 Principal metal being copper (EPO)
   E23.162          Subclass E23.162 indent level is 6 Principal metal being noble metal, e.g., gold (EPO)
   E23.163          Subclass E23.163 indent level is 6 Principal metal being refractory metal (EPO)
   E23.164          Subclass E23.164 indent level is 5 Containing semiconductor material, e.g., polysilicon (EPO)
   E23.165          Subclass E23.165 indent level is 5 Containing carbon, e.g., fullerenes (EPO)
   E23.166          Subclass E23.166 indent level is 5 Containing conductive organic materials or pastes, e.g., conductive adhesives, inks (EPO)
   E23.167          Subclass E23.167 indent level is 4 Insulating materials (EPO)
   E23.168          Subclass E23.168 indent level is 2 Including internal interconnections, e.g., cross-under constructions (EPO)
   E23.169          Subclass E23.169 indent level is 2 Interconnection structure between plurality of semiconductor chips being formed on or in insulating substrates (EPO)
   E23.17          Subclass E23.17 indent level is 3 Crossover interconnections, e.g., bridge stepovers (EPO)
   E23.171          Subclass E23.171 indent level is 3 Adaptable interconnections, e.g., for engineering changes (EPO)
   E23.172          Subclass E23.172 indent level is 3 Assembly of plurality of insulating substrates (EPO)
   E23.173          Subclass E23.173 indent level is 3 Multilayer substrates (EPO)
   E23.174          Subclass E23.174 indent level is 3 Conductive vias through substrate with or without pins, e.g., buried coaxial conductors (EPO)
   E23.175          Subclass E23.175 indent level is 3 Geometry or layout of interconnection structure (EPO)
   E23.176          Subclass E23.176 indent level is 3 For flat cards, e.g., credit cards (EPO)
   E23.177          Subclass E23.177 indent level is 3 Flexible insulating substrates (EPO)
   E23.178          Subclass E23.178 indent level is 3 Chips being integrally enclosed by interconnect and support structures (EPO)
   E23.179          Subclass E23.179 indent level is 1 Marks applied to semiconductor devices or parts, e.g., registration marks, test patterns, alignment structures, wafer maps (EPO)
   E23.18          Subclass E23.18 indent level is 1 Containers; seals (EPO)
   E23.181          Subclass E23.181 indent level is 2 Characterized by shape of container or parts, e.g., caps, walls (EPO)
   E23.182          Subclass E23.182 indent level is 3 Container being hollow construction having no base used as mounting for semiconductor body (EPO)
   E23.183          Subclass E23.183 indent level is 3 Container being hollow construction and having conductive base as mounting as well as lead for the semiconductor body (EPO)
   E23.184          Subclass E23.184 indent level is 4 Other leads having insulating passage through base (EPO)
   E23.185          Subclass E23.185 indent level is 4 Other leads being parallel to base (EPO)
   E23.186          Subclass E23.186 indent level is 4 Other leads being perpendicular to base (EPO)
   E23.187          Subclass E23.187 indent level is 4 Another lead being formed by cover plate parallel to base plate, e.g., sandwich type (EPO)
   E23.188          Subclass E23.188 indent level is 3 Container being hollow construction and having insulating or insulated base as mounting for semiconductor body (EPO)
   E23.189          Subclass E23.189 indent level is 4 Leads being parallel to base (EPO)
   E23.19          Subclass E23.19 indent level is 4 Leads having passage through base (EPO)
   E23.191          Subclass E23.191 indent level is 2 Characterized by material of container or its electrical properties (EPO)
   E23.192          Subclass E23.192 indent level is 3 Material being electrical insulator, e.g., glass (EPO)
   E23.193          Subclass E23.193 indent level is 2 Characterized by material or arrangement of seals between parts, e.g., between cap and base of container or between leads and walls of container (EPO)
   E23.194          Subclass E23.194 indent level is 1 Protection against mechanical damage (EPO)
   E49.001          SOLID-STATE DEVICES WITH AT LEAST ONE POTENTIAL-JUMP BARRIER OR SURFACE BARRIER USING ACTIVE LAYER OF LOWER ELECTRICAL CONDUCTIVITY THAN MATERIAL ADJACENT THERETO AND THROUGH WHICH CARRIER TUNNELING OCCURS, PROCESSES OR APPARATUS PECULIAR TO MANUFACTURE OR TREATMENT OF SUCH DEVICES, OR OF PARTS THEREOF (EPO)
   E49.002          Subclass E49.002 indent level is 1 Devices using Mott metal-insulator transition, e.g., field-effect transistors (EPO)
   E49.003          Subclass E49.003 indent level is 1 Quantum devices, e.g., quantum interference devices, metal single electron transistor (EPO)
   E49.004          Subclass E49.004 indent level is 1 Thin-film or thick-film devices (EPO)
   E21.001          PROCESSES OR APPARATUS ADAPTED FOR MANUFACTURE OR TREATMENT OF SEMICONDUCTOR OR SOLID-STATE DEVICES OR OF PARTS THEREOF (EPO)
   E21.002          Subclass E21.002 indent level is 1 Manufacture or treatment of semiconductor device (EPO)
   E21.003          Subclass E21.003 indent level is 2 Manufacture of two-terminal component for integrated circuit (EPO)
   E21.004          Subclass E21.004 indent level is 3 Of resistor (EPO)
   E21.005          Subclass E21.005 indent level is 4 Active material comprising carbon, e.g., diamond or diamond-like carbon (EPO)
   E21.006          Subclass E21.006 indent level is 4 Active material comprising refractory, transition, or noble metal or metal compound, e.g., alloy, silicide, oxide, nitride (EPO)
   E21.007          Subclass E21.007 indent level is 4 Active material comprising organic conducting material, e.g., conducting polymer (EPO)
   E21.008          Subclass E21.008 indent level is 3 Of capacitor (EPO)
   E21.009          Subclass E21.009 indent level is 4 Dielectric having perovskite structure (EPO)
   E21.01          Subclass E21.01 indent level is 5 Dielectric comprising two or more layers, e.g., buffer layers, seed layers, gradient layers (EPO)
   E21.011          Subclass E21.011 indent level is 4 Formation of electrode (EPO)
   E21.012          Subclass E21.012 indent level is 5 With increased surface area, e.g., by roughening, texturing (EPO)
   E21.013          Subclass E21.013 indent level is 6 With rough surface, e.g., using hemispherical grains (EPO)
   E21.014          Subclass E21.014 indent level is 6 Having cylindrical, crown, or fin-type shape (EPO)
   E21.015          Subclass E21.015 indent level is 6 Having horizontal extensions (EPO)
   E21.016          Subclass E21.016 indent level is 7 Made by depositing layers, e.g., alternatingly conductive and insulating layers (EPO)
   E21.017          Subclass E21.017 indent level is 7 Made by patterning layers, e.g., etching conductive layers (EPO)
   E21.018          Subclass E21.018 indent level is 6 Having vertical extensions (EPO)
   E21.019          Subclass E21.019 indent level is 7 Made by depositing layers, e.g., alternatingly conductive and insulating layers (EPO)
   E21.02          Subclass E21.02 indent level is 7 Made by patterning layers, e.g., etching conductive layers (EPO)
   E21.021          Subclass E21.021 indent level is 6 Having multilayers, e.g., comprising barrier layer and metal layer (EPO)
   E21.022          Subclass E21.022 indent level is 3 Of inductor (EPO)
   E21.023          Subclass E21.023 indent level is 2 Making mask on semicond uctor body for further photolithographic processing (EPO)
   E21.024          Subclass E21.024 indent level is 3 Comprising organic layer (EPO)
   E21.025          Subclass E21.025 indent level is 4 For lift-off process (EPO)
   E21.026          Subclass E21.026 indent level is 4 Characterized by treatment of photoresist layer (EPO)
   E21.027          Subclass E21.027 indent level is 5 Photolith ographic process (EPO)
   E21.028          Subclass E21.028 indent level is 6 Using laser (EPO)
   E21.029          Subclass E21.029 indent level is 6 Using anti-reflective coating (EPO)
   E21.03          Subclass E21.03 indent level is 5 Electro-lithographic process (EPO)
   E21.031          Subclass E21.031 indent level is 5 X-ray lithographic process (EPO)
   E21.032          Subclass E21.032 indent level is 5 Ion lithographic process (EPO)
   E21.033          Subclass E21.033 indent level is 3 Comprising inorganic layer (EPO)
   E21.034          Subclass E21.034 indent level is 4 For lift-off process (EPO)
   E21.035          Subclass E21.035 indent level is 4 Characterized by their composition, e.g., multilayer masks, materials (EPO)
   E21.036          Subclass E21.036 indent level is 4 Characterized by their size, orientation, disposition, behavior, shape, in horizontal or vertical plane (EPO)
   E21.037          Subclass E21.037 indent level is 5 Characterized by their behavior during process, e.g., soluble mask, re-deposited mask (EPO)
   E21.038          Subclass E21.038 indent level is 5 Characterized by process involved to create mask, e.g., lift-off mask, sidewalls, or to modify mask, such as pre-treatment, post-treatment (EPO)
   E21.039          Subclass E21.039 indent level is 5 Process specially adapted to improve the resolution of the mask (EPO)
   E21.04          Subclass E21.04 indent level is 2 Device having at least one potential-jump barrier or surface barrier, e.g., PN junction, depletion layer, carrier concentration layer (EPO)
   E21.041          Subclass E21.041 indent level is 3 Device having semiconductor body comprising carbon, e.g., diamond, diamond-like carbon (EPO)
   E21.042          Subclass E21.042 indent level is 4 Making n- or p-doped regions (EPO)
   E21.043          Subclass E21.043 indent level is 5 Using ion im plantation (EPO)
   E21.044          Subclass E21.044 indent level is 4 Changing their shape, e.g., forming recess (EPO)
   E21.045          Subclass E21.045 indent level is 4 Making electrode (EPO)
   E21.046          Subclass E21.046 indent level is 5 Ohmic electrode (EPO)
   E21.047          Subclass E21.047 indent level is 5 Schottky electrode (EPO)
   E21.048          Subclass E21.048 indent level is 5 Conductor-insulator-semiconductor electrode, e.g., MIS contacts (EPO)
   E21.049          Subclass E21.049 indent level is 4 Multistep processes for manufacture of device whose active layer, e.g., base, channel, comprises semiconducting carbon, e.g., diamond, diamond-like carbon (EPO)
   E21.05          Subclass E21.05 indent level is 5 Device controllable only by electric current supplied or the electric potential applied to electrode which does not carry current to be rectified, amplified, or switched, e.g., three-terminal devices such as source, drain, and gate terminals; emitter, base, collector terminals (EPO)
   E21.051          Subclass E21.051 indent level is 6 Field-effect transistor (EPO)
   E21.052          Subclass E21.052 indent level is 5 Device controllable only by variation of electric current supplied or the electric potential applied to electrodes carrying current to be rectified, amplified, oscillated, or switched, e.g., two-terminal device (EPO)
   E21.053          Subclass E21.053 indent level is 6 Diode (EPO)
   E21.054          Subclass E21.054 indent level is 3 Device having semiconductor body comprising silicon carbide (SiC) (EPO)
   E21.055          Subclass E21.055 indent level is 4 Passivating silicon carbide surface (EPO)
   E21.056          Subclass E21.056 indent level is 4 Making n- or p- doped regions or layers, e.g., using diffusion (EPO)
   E21.057          Subclass E21.057 indent level is 5 Using ion implantation (EPO)
   E21.058          Subclass E21.058 indent level is 6 Using masks (EPO)
   E21.059          Subclass E21.059 indent level is 6 Angled implantation (EPO)
   E21.06          Subclass E21.06 indent level is 4 Changing shape of semiconductor body, e.g., forming recesses (EPO)
   E21.061          Subclass E21.061 indent level is 4 Making electrode (EPO)
   E21.062          Subclass E21.062 indent level is 5 Ohmic electrode (EPO)
   E21.063          Subclass E21.063 indent level is 5 Conductor-insulator-semiconductor electrode, e.g., MIS contact (EPO)
   E21.064          Subclass E21.064 indent level is 5 Schottky electrode (EPO)
   E21.065          Subclass E21.065 indent level is 4 Multistep processes for manufacture of device whose active layer, e.g., base, channel, comprises silicon carbide (EPO)
   E21.066          Subclass E21.066 indent level is 5 Device controllable only by electric current supplied or the electric potential applied to electrode which does not carry current to be rectified, amplified, or switched, e.g., three-terminal device (EPO)
   E21.067          Subclass E21.067 indent level is 5 Device controllable only by variation of electric current supplied or electric potential applied to one or more of the electrodes carrying current to be rectified, amplified, oscillated, or switched, e.g., two-terminal device (EPO)
   E21.068          Subclass E21.068 indent level is 3 Device having semiconductor body comprising selenium (Se) or tellurium (Te) (EPO)
   E21.069          Subclass E21.069 indent level is 4 Preparation of substrate or foundation plate for Se or Te semiconductor (EPO)
   E21.07          Subclass E21.07 indent level is 4 Preliminary treatment of Se or Te, its application to substrate, or the subsequent treatment of combination (EPO)
   E21.071          Subclass E21.071 indent level is 5 Application of Se or Te to substrate or foundation plate (EPO)
   E21.072          Subclass E21.072 indent level is 5 Conversion of Se or Te to conductive state (EPO)
   E21.073          Subclass E21.073 indent level is 5 Treatment of surface of Se or Te layer after having been made conductive (EPO)
   E21.074          Subclass E21.074 indent level is 5 Provision of discrete insulating layer, i.e., specified barrier layer material (EPO)
   E21.075          Subclass E21.075 indent level is 4 Application of electrode to exposed surface of Se or Te after Se or Te has been applied to foundation plate (EPO)
   E21.076          Subclass E21.076 indent level is 4 Treatment of complete device, e.g., by electroforming to form barrier (EPO)
   E21.077          Subclass E21.077 indent level is 5 Heat treating (EPO)
   E21.078          Subclass E21.078 indent level is 3 Device having semiconductor body comprising cuprous oxide (Cu 2 O) or cuprous iodide (CuI) (EPO)
   E21.079          Subclass E21.079 indent level is 4 Preparation of substrate, preliminary treatment oxidation of substrate, reduction treatment (EPO)
   E21.08          Subclass E21.08 indent level is 5 Preliminary treatment of foundation plate (EPO)
   E21.081          Subclass E21.081 indent level is 5 Reduction of copper oxide, treatment of oxide layer (EPO)
   E21.082          Subclass E21.082 indent level is 5 Oxidation and subsequent heat treatment of substrate (EPO)
   E21.083          Subclass E21.083 indent level is 5 Application of specified conductive layer (EPO)
   E21.084          Subclass E21.084 indent level is 4 Treatment of complete device, e.g., electroforming, heat treating (EPO)
   E21.085          Subclass E21.085 indent level is 3 Device having semiconductor body comprising Group IV elements or Group III-V compounds with or without impurities, e.g., doping materials (EPO)
   E21.086          Subclass E21.086 indent level is 4 Intermixing or interdiffusion or disordering of Group III-V heterostructures, e.g., IILD (EPO)
   E21.087          Subclass E21.087 indent level is 4 Joining of semiconductor body for junction formation (EPO)
   E21.088          Subclass E21.088 indent level is 5 By direct bonding (EPO)
   E21.089          Subclass E21.089 indent level is 4 Multistep processes for manufacture of device using quantum interference effect, e.g., electrostatic Aharonov-Bohm effect (EPO)
   E21.09          Subclass E21.09 indent level is 4 Deposition of semiconductor material on substrate, e.g., epitaxial growth, solid phase epitaxy (EPO)
   E21.091          Subclass E21.091 indent level is 5 Using physical deposition, e.g., vacuum deposition, sputtering (EPO)
   E21.092          Subclass E21.092 indent level is 6 Epitaxial deposition of Group IV element, e.g., Si, Ge (EPO)
   E21.093          Subclass E21.093 indent level is 7 Deposition on semiconductor substrate being different from deposited semiconductor material; i.e., formation of heterojunctions (EPO)
   E21.094          Subclass E21.094 indent level is 7 Deposition on insulating or meta llic substrate (EPO)
   E21.095          Subclass E21.095 indent level is 7 Epitaxial deposition of diamond (EPO)
   E21.096          Subclass E21.096 indent level is 6 Deposition of diamond (EPO)
   E21.097          Subclass E21.097 indent level is 6 Epitaxial deposition of Group III-V compound (EPO)
   E21.098          Subclass E21.098 indent level is 7 Deposition on semiconductor substrate not being an Group III-V compound (EPO)
   E21.099          Subclass E21.099 indent level is 7 Deposition on insulating or metallic substrate (EPO)
   E21.1          Subclass E21.1 indent level is 7 Doping during epitaxial deposition (EPO)
   E21.101          Subclass E21.101 indent level is 5 Using reduction or decomposition of gaseous compound yielding solid condensate, i.e., chemical deposition (EPO)
   E21.102          Subclass E21.102 indent level is 6 Epitaxial deposition of Group IV elements, e.g., Si, Ge, C (EPO)
   E21.103          Subclass E21.103 indent level is 7 Deposition on a semiconductor substrate which is different from the semiconductor material being deposited, i.e., formation of heterojunctions (EPO)
   E21.104          Subclass E21.104 indent level is 7 Deposition on an insulating or a metallic substrate (EPO)
   E21.105          Subclass E21.105 indent level is 7 Epitaxial deposition of diamond (EPO)
   E21.106          Subclass E21.106 indent level is 7 Doping during the epitaxial deposition (EPO)
   E21.107          Subclass E21.107 indent level is 6 Deposition of diamond (EPO)
   E21.108          Subclass E21.108 indent level is 6 Epitaxial deposition of Group III-V compound (EPO)
   E21.109          Subclass E21.109 indent level is 7 Using molecular beam technique (EPO)
   E21.11          Subclass E21.11 indent level is 7 Doping the epitaxial deposit (EPO)
   E21.111          Subclass E21.111 indent level is 8 Doping with transition metals to form semi-insulating layers (EPO)
   E21.112          Subclass E21.112 indent level is 7 Deposition on a semiconductor substrate not being Group III-V compound (EPO)
   E21.113          Subclass E21.113 indent level is 7 Deposition on an insulating or a metallic substrate (EPO)
   E21.114          Subclass E21.114 indent level is 5 Using liquid deposition (EPO)
   E21.115          Subclass E21.115 indent level is 6 Epitaxial deposition of Group IV elements, e.g., Si, Ge, C (EPO)
   E21.116          Subclass E21.116 indent level is 7 Deposition on a semiconductor substrate which is different from the semiconductor material being deposited, i.e., formation of heterojunction (EPO)
   E21.117          Subclass E21.117 indent level is 6 Epitaxial deposition of Group III-V compound (EPO)
   E21.118          Subclass E21.118 indent level is 7 Deposition on a semiconductor substrate not being an Group III-V compound (EPO)
   E21.119          Subclass E21.119 indent level is 5 Characterized by the substrate (EPO)
   E21.12          Subclass E21.12 indent level is 6 Characterized by the post-treatment used to control the interface betw een substrate and epitaxial layer, e.g., ion implantation followed by annealing (EPO)
   E21.121          Subclass E21.121 indent level is 6 Substrate is crystalline insulating material, e.g., sapphire (EPO)
   E21.122          Subclass E21.122 indent level is 6 Bonding of semiconductor wafer to insulating substrate or to semic onducting substrate using an intermediate insulating layer (EPO)
   E21.123          Subclass E21.123 indent level is 7 Substrate is crystalline semiconductor material, e.g., lattice adaptation, heteroepitaxy (EPO)
   E21.124          Subclass E21.124 indent level is 8 Heteroepitaxy (EPO)
   E21.125          Subclass E21.125 indent level is 8 Defect and dislocati on suppression due to lattice mismatch, e.g., lattice adaptation (EPO)
   E21.126          Subclass E21.126 indent level is 8 Group III-V compound on dissimilar Group III-V compound (EPO)
   E21.127          Subclass E21.127 indent level is 8 Group III-V compound on Si or Ge (EPO)
   E21.128          Subclass E21.128 indent level is 8 Carbon on a noncarbon semiconductor substrate (EPO)
   E21.129          Subclass E21.129 indent level is 6 Group IVA, e.g., Si, C, Ge on Group IVB, e.g., Ti, Zr (EPO)
   E21.13          Subclass E21.13 indent level is 6 The substrate is crystalline conducting material, e.g., metallic silicide (EPO)
   E21.131          Subclass E21.131 indent level is 5 Selective epilaxial growth, e.g., simultaneous deposition of mono- and non-mono semiconductor material (EPO)
   E21.132          Subclass E21.132 indent level is 6 Preparation of substrate for selective epitaxy (EPO)
   E21.133          Subclass E21.133 indent level is 5 Epitaxial re-growth of non-monocrystalline semiconductor material, e.g., lateral epitaxy by seeded solidific ation, solid-state crystallization, solid-state graphoepitaxy, explosive crystallization, grain growth in polycrystalline material (EPO)
   E21.134          Subclass E21.134 indent level is 6 Using a coherent energy beam, e.g., laser or electron beam (EPO)
   E21.135          Subclass E21.135 indent level is 4 Diffusion of impurity material, e.g., doping material, electrode material, into or out of a semiconductor body, or between semiconductor regions; interactions between two or more impurities; redistribution of impurities (EPO)
   E21.136          Subclass E21.136 indent level is 5 From the substrate during epitaxy, e.g., autodoping; preventing or using autodoping (EPO)
   E21.137          Subclass E21.137 indent level is 5 To control carrier lifetime, i.e., deep level dopant (EPO)
   E21.138          Subclass E21.138 indent level is 6 In Group III-V compound (EPO)
   E21.139          Subclass E21.139 indent level is 5 Lithium-drift (EPO)
   E21.14          Subclass E21.14 indent level is 5 Diffusion source (EPO)
   E21.141          Subclass E21.141 indent level is 5 Using diffusion into or out of a solid from or into a gaseous phase (EPO)
   E21.142          Subclass E21.142 indent level is 6 Diffusion into or out of Group III-V compound (EPO)
   E21.143          Subclass E21.143 indent level is 6 From or into plasma phase (EPO)
   E21.144          Subclass E21.144 indent level is 5 Using diffusion into or out of a s olid from or into a solid phase, e.g., a doped oxide layer (EPO)
   E21.145          Subclass E21.145 indent level is 6 Diffusion into or out of Group IV semiconductor (EPO)
   E21.146          Subclass E21.146 indent level is 7 Using predeposition of impurities into the semiconductor surface, e.g., from gaseous phase (EPO)
   E21.147          Subclass E21.147 indent level is 8 By ion implantation (EPO)
   E21.148          Subclass E21.148 indent level is 7 From or through or into an applied layer, e.g., photoresist, nitride (EPO)
   E21.149          Subclass E21.149 indent level is 8 Applied layer is oxide, e.g., P 2 O 5 , PSG, H 3 BO 3 , doped oxide (EPO)
   E21.15          Subclass E21.15 indent level is 9 Through the applied layer (EPO)
   E21.151          Subclass E21.151 indent level is 8 Applied layer being silicon or silicide or SIPOS, e.g., polysilicon, porous silicon (EPO)
   E21.152          Subclass E21.152 indent level is 6 Diffusion into or out of Group III-V compound (EPO)
   E21.153          Subclass E21.153 indent level is 5 Using diffusion into or out of a solid from or into a liquid phase, e.g., alloy diffusion process (EPO)
   E21.154          Subclass E21.154 indent level is 4 Alloying of impurity material, e.g., doping material, electrode material, with a semiconductor body (EPO)
   E21.155          Subclass E21.155 indent level is 5 Alloying of doping material with Group III-V compound (EPO)
   E21.156          Subclass E21.156 indent level is 5 Alloying of electrode material (EPO)
   E21.157          Subclass E21.157 indent level is 6 With Group III-V compound (EPO)
   E21.158          Subclass E21.158 indent level is 4 Manufacture of electrode on semiconductor body using process other than by epitaxial growth, diffusion of impurities, alloying of impurity materials, or radiation bombardment (EPO)
   E21.159          Subclass E21.159 indent level is 5 Deposition of conductive or insulating material for electrode conducting electric current (EPO)
   E21.16          Subclass E21.16 indent level is 6 From a gas or vapor, e.g., condensation (EPO)
   E21.161          Subclass E21.161 indent level is 7 Of conductive layer (EPO)
   E21.162          Subclass E21.162 indent level is 8 On semiconductor body comprising Group IV element (EPO)
   E21.163          Subclass E21.163 indent level is 9 Deposition of Schottky electrode (EPO)
   E21.164          Subclass E21.164 indent level is 9 O layer comprising silicide (EPO)
   E21.165          Subclass E21.165 indent level is 9 Conductive layer comprising silicide (EPO)
   E21.166          Subclass E21.166 indent level is 9 Conductive layer comprising semiconducting material (EPO)
   E21.167          Subclass E21.167 indent level is 10 Making of side-wall contact (EPO)
   E21.168          Subclass E21.168 indent level is 9 Conductive layer comprising transition metal, e.g., Ti, W, Mo (EPO)
   E21.169          Subclass E21.169 indent level is 9 By physical means, e.g., sputtering, evaporation (EPO)
   E21.17          Subclass E21.17 indent level is 9 By chemical means, e.g., CVD, LPCVD, PECVD, laser CVD (EPO)
   E21.171          Subclass E21.171 indent level is 10 Selective deposition (EPO)
   E21.172          Subclass E21.172 indent level is 8 On semiconductor body comprising Group III-V compound (EPO)
   E21.173          Subclass E21.173 indent level is 9 Deposition of Schottky electrode (EPO)
   E21.174          Subclass E21.174 indent level is 6 From a liquid, e.g., electrolytic deposition (EPO)
   E21.175          Subclass E21.175 indent level is 7 Using an external electrical current, i.e., electro-deposition (EPO)
   E21.176          Subclass E21.176 indent level is 5 Manufacture or post-treatment of electrode having a capacitive structure, i.e., gate structure for field-effect device (EPO)
   E21.177          Subclass E21.177 indent level is 6 MOS-gate structure (EPO)
   E21.178          Subclass E21.178 indent level is 7 Joint-gate structure (EPO)
   E21.179          Subclass E21.179 indent level is 7 Floating or plural gate structure (EPO)
   E21.18          Subclass E21.18 indent level is 7 Gate structure with charge-trapping insulator (EPO)
   E21.181          Subclass E21.181 indent level is 7 On semiconductor body not comprising Group IV element, e.g., Group III-V compound (EPO)
   E21.182          Subclass E21.182 indent level is 7 On semiconductor body comprising Group IV element excluding non-elemental Si, e.g., Ge, C, diamond, silicon compound or compound, such as SiC or SiGe (EPO)
   E21.183          Subclass E21.183 indent level is 7 For charge-coupled device (EPO)
   E21.184          Subclass E21.184 indent level is 6 PN-homojunction gate structure (EPO)
   E21.185          Subclass E21.185 indent level is 7 For charge-coupled device (EPO)
   E21.186          Subclass E21.186 indent level is 6 Schottky gate structure (EPO)
   E21.187          Subclass E21.187 indent level is 7 For charge-coupled device (EPO)
   E21.188          Subclass E21.188 indent level is 6 Heterojunction gate structure (EPO)
   E21.189          Subclass E21.189 indent level is 7 For charge-coupled device (EPO)
   E21.19          Subclass E21.19 indent level is 5 Making electrode structure comprising conductor-insulator-semiconductor, e.g., MIS gate (EPO)
   E21.191          Subclass E21.191 indent level is 6 Insulator formed on silicon semiconductor body (EPO)
   E21.192          Subclass E21.192 indent level is 7 Characterized by insulator (EPO)
   E21.193          Subclass E21.193 indent level is 8 On single crystalline silicon (EPO)
   E21.194          Subclass E21.194 indent level is 9 Characterized by treatment after formation of definitive gate conductor (EPO)
   E21.195          Subclass E21.195 indent level is 7 Characterized by conductor (EPO)
   E21.196          Subclass E21.196 indent level is 8 Final conductor next to insulator having lateral composition or doping variation, or being formed laterally by more than one deposition step (EPO)
   E21.197          Subclass E21.197 indent level is 8 Final conductor layer next to insulator being silicon e.g., polysilicon, with or without impurities (EPO)
   E21.198          Subclass E21.198 indent level is 9 Conductor comprising at least another nonsilicon conductive layer (EPO)
   E21.199          Subclass E21.199 indent level is 10 Conductor comprising silicide layer formed by silicidation reaction of silicon with metal layer (EPO)
   E21.2          Subclass E21.2 indent level is 10 Conductor comprising metal or metallic silicide formed by deposition e.g., sputter deposition, i.e., without silicidation reaction (EPO)
   E21.201          Subclass E21.201 indent level is 8 Conductor layer next to insulator is Si or Ge or C and their non-Si alloys (EPO)
   E21.202          Subclass E21.202 indent level is 8 Conductor layer next to the insulator is single metal, e.g., Ta, W, Mo, Al (EPO)
   E21.203          Subclass E21.203 indent level is 8 Conductor layer next to insulator is metallic silicide (Me Si) (EPO)
   E21.204          Subclass E21.204 indent level is 8 Conductor layer next to insulator is non-MeSi composite or compound, e.g., TiN (EPO)
   E21.205          Subclass E21.205 indent level is 8 Characterized by sectional shape, e.g., T-shape, inverted T, spacer (EPO)
   E21.206          Subclass E21.206 indent level is 8 Lithography, isolation, or planarization-related aspects of making conductor-insulator-semiconductor structure, e.g., sub-lithography lengths; to solve problems arising at crossing with side of device isolation (EPO)
   E21.207          Subclass E21.207 indent level is 6 Insulator formed on nonelemental silicon semiconductor body, e.g., Ge, SiGe, SiGeC (EPO)
   E21.208          Subclass E21.208 indent level is 5 Comprising layer having ferroelectric properties (EPO)
   E21.209          Subclass E21.209 indent level is 5 Making electrode structure comprising conductor-insulator-conuctor-insulator-semiconductor, e.g., gate stack for non-volatile memory (EPO)
   E21.21          Subclass E21.21 indent level is 5 Comprising charge trapping insulator (EPO)
   E21.211          Subclass E21.211 indent level is 4 Treatment of semiconductor body using process other than deposition of semiconductor material on a substrate, diffusion or alloying of impurity material, or radiation treatment (EPO)
   E21.212          Subclass E21.212 indent level is 5 Hydrogenation or deuterization, e.g., using atomic hydrogen or deuterium from a plasma (EPO)
   E21.213          Subclass E21.213 indent level is 6 Of Group III-V compound (EPO)
   E21.214          Subclass E21.214 indent level is 5 To change their surface-physical characteristics or shape, e.g., etching, polishing, cutting (EPO)
   E21.215          Subclass E21.215 indent level is 6 Chemical or electrical treatment, e.g., electrolytic etching (EPO)
   E21.216          Subclass E21.216 indent level is 7 Electrolytic etching (EPO)
   E21.217          Subclass E21.217 indent level is 8 Of Group III-V compound (EPO)
   E21.218          Subclass E21.218 indent level is 7 Plasma etching; reactive-ion etching (EPO)
   E21.219          Subclass E21.219 indent level is 7 Chemical etching (EPO)
   E21.22          Subclass E21.22 indent level is 8 Etching of Group III-V compound (EPO)
   E21.221          Subclass E21.221 indent level is 9 Anisotropic liquid etching (EPO)
   E21.222          Subclass E21.222 indent level is 9 Vapor phase etching (EPO)
   E21.223          Subclass E21.223 indent level is 8 Anisotropic liquid etching (EPO)
   E21.224          Subclass E21.224 indent level is 7 Chemical cleaning (EPO)
   E21.225          Subclass E21.225 indent level is 8 Cleaning diamond or graphite (EPO)
   E21.226          Subclass E21.226 indent level is 8 Dry cleaning (EPO)
   E21.227          Subclass E21.227 indent level is 9 With gaseous hydrogen fluoride (HF) (EPO)
   E21.228          Subclass E21.228 indent level is 8 Wet cleaning only (EPO)
   E21.229          Subclass E21.229 indent level is 8 Combining dry and wet cleaning steps (EPO)
   E21.23          Subclass E21.23 indent level is 7 With simultaneous mechanical treatment, e.g., chemical-mechanical polishing (EPO)
   E21.231          Subclass E21.231 indent level is 7 Using mask (EPO)
   E21.232          Subclass E21.232 indent level is 8 Characterized by their composition, e.g., multilayer masks, materials (EPO)
   E21.233          Subclass E21.233 indent level is 8 Characterized by their size, orientation, disposition, behavior, shape, in horizontal or vertical plane (EPO)
   E21.234          Subclass E21.234 indent level is 9 Characterized by their behavior during process, e.g., soluble mask, redeposited mask (EPO)
   E21.235          Subclass E21.235 indent level is 9 Characterized by process involved to create mask, e.g., lift-off mask, sidewall, or to modify the mask, e.g., pre-treatment, post-treatment (EPO)
   E21.236          Subclass E21.236 indent level is 9 Process specially adapted to improve resolution of mask (EPO)
   E21.237          Subclass E21.237 indent level is 6 Mechanical treatment, e.g., grinding, polishing, cutting (EPO)
   E21.238          Subclass E21.238 indent level is 7 Making grooves, e.g., cutting (EPO)
   E21.239          Subclass E21.239 indent level is 7 Using abrasion, e.g., sand-blasting (EPO)
   E21.24          Subclass E21.24 indent level is 6 To form insulating layer thereon, e.g., for masking or by using photolithographic technique (EPO)
   E21.241          Subclass E21.241 indent level is 7 Post-treatment (EPO)
   E21.242          Subclass E21.242 indent level is 8 Of organic layer (EPO)
   E21.243          Subclass E21.243 indent level is 8 Planarization of insulating layer (EPO)
   E21.244          Subclass E21.244 indent level is 9 Involving dielectric removal step (EPO)
   E21.245          Subclass E21.245 indent level is 10 Removal by chemical etching, e.g., dry etching (EPO)
   E21.246          Subclass E21.246 indent level is 11 Removal by selective chemical etching, e.g., selective dry etching through mask (EPO)
   E21.247          Subclass E21.247 indent level is 8 Doping insulating layer (EPO)
   E21.248          Subclass E21.248 indent level is 9 By ion implantation (EPO)
   E21.249          Subclass E21.249 indent level is 8 Etching insulating layer by chemical or physical means (EPO)
   E21.25          Subclass E21.25 indent level is 9 Etching inorganic layer (EPO)
   E21.251          Subclass E21.251 indent level is 10 By chemical means (EPO)
   E21.252          Subclass E21.252 indent level is 11 By dry-etching (EPO)
   E21.253          Subclass E21.253 indent level is 12 Of layers not containing Si, e.g., PZT, Al 2 O 3 (EPO)
   E21.254          Subclass E21.254 indent level is 9 Etching organic layer (EPO)
   E21.255          Subclass E21.255 indent level is 10 By chemical means (EPO)
   E21.256          Subclass E21.256 indent level is 11 By dry-etching (EPO)
   E21.257          Subclass E21.257 indent level is 9 Using mask (EPO)
   E21.258          Subclass E21.258 indent level is 7 Using masks (EPO)
   E21.259          Subclass E21.259 indent level is 7 Organic layers, e.g., photoresist (EPO)
   E21.26          Subclass E21.26 indent level is 8 Layer comprising organo-silicon compound (EPO)
   E21.261          Subclass E21.261 indent level is 9 Layer comprising polysiloxane compound (EPO)
   E21.262          Subclass E21.262 indent level is 10 Layer comprising hydrogen silsesquioxane (EPO)
   E21.263          Subclass E21.263 indent level is 10 Layer comprising silazane compounds (EPO)
   E21.264          Subclass E21.264 indent level is 8 Layers comprising fluoro hydrocarbon compounds, e.g., polytetrafluoroethylene (EPO)
   E21.265          Subclass E21.265 indent level is 8 By Langmuir-Blodgett technique (EPO)
   E21.266          Subclass E21.266 indent level is 7 Inorganic layer (EPO)
   E21.267          Subclass E21.267 indent level is 8 Composed of alternated layers or of mixtures of nitrides and oxides or of oxynitrides, e.g., formation of oxynitride by oxidation of nitride layer (EPO)
   E21.268          Subclass E21.268 indent level is 8 Of silicon (EPO)
   E21.269          Subclass E21.269 indent level is 9 Formed by deposition from a gas or vapor (EPO)
   E21.27          Subclass E21.27 indent level is 8 Carbon layer, e.g., diamond-like layer (EPO)
   E21.271          Subclass E21.271 indent level is 8 Composed of oxide or glassy oxide or oxide based glass (EPO)
   E21.272          Subclass E21.272 indent level is 9 With perovskite structure (EPO)
   E21.273          Subclass E21.273 indent level is 9 Deposition of porous oxide or porous glassy oxide or oxide based porous glass (EPO)
   E21.274          Subclass E21.274 indent level is 9 Deposition from gas or vapor (EPO)
   E21.275          Subclass E21.275 indent level is 10 Deposition of boron or phosphorus doped silicon oxide, e.g., BSG, PSG, BPSG (EPO)
   E21.276          Subclass E21.276 indent level is 10 Deposition of halogen doped silicon oxide, e.g., fluorine doped silicon oxide (EPO)
   E21.277          Subclass E21.277 indent level is 10 Deposition of carbon doped silicon oxide, e.g., SiOC (EPO)
   E21.278          Subclass E21.278 indent level is 10 Deposition of silicon oxide (EPO)
   E21.279          Subclass E21.279 indent level is 11 On silicon body (EPO)
   E21.28          Subclass E21.28 indent level is 10 Deposition of aluminum oxide (EPO)
   E21.281          Subclass E21.281 indent level is 11 On a silicon body (EPO)
   E21.282          Subclass E21.282 indent level is 9 Formed by oxidation (EPO)
   E21.283          Subclass E21.283 indent level is 10 Of semiconductor material, e.g., by oxidation of semiconductor body itself (EPO)
   E21.284          Subclass E21.284 indent level is 11 By thermal oxidation (EPO)
   E21.285          Subclass E21.285 indent level is 12 Of silicon (EPO)
   E21.286          Subclass E21.286 indent level is 12 Of Group III-V compound (EPO)
   E21.287          Subclass E21.287 indent level is 11 By anodic oxidation (EPO)
   E21.288          Subclass E21.288 indent level is 12 Of silicon (EPO)
   E21.289          Subclass E21.289 indent level is 12 Of Group III-V compound (EPO)
   E21.29          Subclass E21.29 indent level is 10 Of metallic layer, e.g., Al deposited on body, e.g., formation of multi-layer insulating structures (EPO)
   E21.291          Subclass E21.291 indent level is 11 By anodic oxidation (EPO)
   E21.292          Subclass E21.292 indent level is 8 Inorganic layer composed of nitride (EPO)
   E21.293          Subclass E21.293 indent level is 9 Of silicon nitride (EPO)
   E21.294          Subclass E21.294 indent level is 6 Deposition/post-treatment of noninsulating, e.g., conductive - or resistive - layers on insulating layers (EPO)
   E21.295          Subclass E21.295 indent level is 7 Deposition of layer comprising metal, e.g., metal, alloys, metal compounds (EPO)
   E21.296          Subclass E21.296 indent level is 8 Of metal-silicide layer (EPO)
   E21.297          Subclass E21.297 indent level is 7 Deposition of semiconductive layer, e.g., poly - or amorphous silicon layer (EPO)
   E21.298          Subclass E21.298 indent level is 7 Deposition of superconductive layer (EPO)
   E21.299          Subclass E21.299 indent level is 7 Deposition of conductive or semi-conductive organic layer (EPO)
   E21.3          Subclass E21.3 indent level is 7 Post treatment (EPO)
   E21.301          Subclass E21.301 indent level is 8 Oxidation of silicon-containing layer (EPO)
   E21.302          Subclass E21.302 indent level is 8 Nitriding of silicon-containing layer (EPO)
   E21.303          Subclass E21.303 indent level is 8 Planarization (EPO)
   E21.304          Subclass E21.304 indent level is 9 By chemical mechanical polishing (CMP) (EPO)
   E21.305          Subclass E21.305 indent level is 8 Physical or chemical etching of layer, e.g., to produce a patterned layer from pre-deposited extensive layer (EPO)
   E21.306          Subclass E21.306 indent level is 9 By physical means only (EPO)
   E21.307          Subclass E21.307 indent level is 10 Of silicon-containing layer (EPO)
   E21.308          Subclass E21.308 indent level is 9 By chemical means only (EPO)
   E21.309          Subclass E21.309 indent level is 10 By liquid etching only (EPO)
   E21.31          Subclass E21.31 indent level is 10 By vapor etching only (EPO)
   E21.311          Subclass E21.311 indent level is 11 Using plasma (EPO)
   E21.312          Subclass E21.312 indent level is 12 Of silicon-containing layer (EPO)
   E21.313          Subclass E21.313 indent level is 11 Pre- or post-treatment, e.g., anti-corrosion process (EPO)
   E21.314          Subclass E21.314 indent level is 9 Using mask (EPO)
   E21.315          Subclass E21.315 indent level is 8 Doping layer (EPO)
   E21.316          Subclass E21.316 indent level is 9 Doping polycrystalline or amorphous silicon layer (EPO)
   E21.317          Subclass E21.317 indent level is 5 To modify their internal properties, e.g., to produce internal imperfections (EPO)
   E21.318          Subclass E21.318 indent level is 6 Of silicon body, e.g., for gettering (EPO)
   E21.319          Subclass E21.319 indent level is 7 Using cavities formed by inert gas ion implantation, e.g., hydrogen, noble gas (EPO)
   E21.32          Subclass E21.32 indent level is 7 Of silicon on insulator (SOI) (EPO)
   E21.321          Subclass E21.321 indent level is 7 Thermally inducing defects using oxygen present in silicon body for intrinsic gettering (EPO)
   E21.322          Subclass E21.322 indent level is 6 Of Group III-V compound, e.g., to make them semi-insulating (EPO)
   E21.323          Subclass E21.323 indent level is 5 Of diamond body (EPO)
   E21.324          Subclass E21.324 indent level is 6 Thermal treatment for modifying the properties of semiconductor body, e.g., annealing, sintering (EPO)
   E21.325          Subclass E21.325 indent level is 6 For the formation of PN junction without ad dition of impurities (EPO)
   E21.326          Subclass E21.326 indent level is 6 Of Group III-V compound (EPO)
   E21.327          Subclass E21.327 indent level is 5 Application of electric current or field, e.g., for electroforming (EPO)
   E21.328          Subclass E21.328 indent level is 4 Radiation treatment (EPO)
   E21.329          Subclass E21.329 indent level is 5 Using natural radiation, e.g., alpha , beta or gamma radiation (EPO)
   E21.33          Subclass E21.33 indent level is 5 To produce chemical element by transmutation (EPO)
   E21.331          Subclass E21.331 indent level is 5 With high-energy radiation (EPO)
   E21.332          Subclass E21.332 indent level is 6 For etching, e.g., sputter etching (EPO)
   E21.333          Subclass E21.333 indent level is 6 For heating, e.g., electron beam heating (EPO)
   E21.334          Subclass E21.334 indent level is 6 Producing ions for implantation (EPO)
   E21.335          Subclass E21.335 indent level is 7 In Group IV semiconductor (EPO)
   E21.336          Subclass E21.336 indent level is 8 Of electrically active species (EPO)
   E21.337          Subclass E21.337 indent level is 9 Through-implantation (EPO)
   E21.338          Subclass E21.338 indent level is 8 Recoil-implantation (EPO)
   E21.339          Subclass E21.339 indent level is 8 Of electrically inactive species in silicon to make buried insulating layer (EPO)
   E21.34          Subclass E21.34 indent level is 7 In Group III-V compound (EPO)
   E21.341          Subclass E21.341 indent level is 8 Of electrically active species (EPO)
   E21.342          Subclass E21.342 indent level is 9 Through-implantation (EPO)
   E21.343          Subclass E21.343 indent level is 8 Characterized by the implantation of both electrically active and inactive species in the same semiconductor region to be doped (EPO)
   E21.344          Subclass E21.344 indent level is 7 In diamond (EPO)
   E21.345          Subclass E21.345 indent level is 7 Characterized by the angle between the ion beam and the crystal planes or the main crystal surface (EPO)
   E21.346          Subclass E21.346 indent level is 7 Using mask (EPO)
   E21.347          Subclass E21.347 indent level is 6 Using electromagnetic radiation, e.g., laser radiation (EPO)
   E21.348          Subclass E21.348 indent level is 7 Using X-ray laser (EPO)
   E21.349          Subclass E21.349 indent level is 7 Using incoherent radiation (EPO)
   E21.35          Subclass E21.35 indent level is 4 Multi-step process for manufacture of device of bipolar type, e.g., diodes, transistors, thyristors, resistors, capacitors) (EPO)
   E21.351          Subclass E21.351 indent level is 5 Device comprising one or two electrodes, e.g., diode, resistor or capacitor with PN or Schottky junctions (EPO)
   E21.352          Subclass E21.352 indent level is 6 Diode (EPO)
   E21.353          Subclass E21.353 indent level is 7 Tunnel diode (EPO)
   E21.354          Subclass E21.354 indent level is 7 Transit time diode, e.g., IMPATT, TRAPATT diode (EPO)
   E21.355          Subclass E21.355 indent level is 7 Break-down diode, e.g., Zener diode, avalanche diode (EPO)
   E21.356          Subclass E21.356 indent level is 8 Zener diode (EPO)
   E21.357          Subclass E21.357 indent level is 8 Avalanche diode (EPO)
   E21.358          Subclass E21.358 indent level is 7 Rectifier diode (EPO)
   E21.359          Subclass E21.359 indent level is 7 Schottky diode (EPO)
   E21.36          Subclass E21.36 indent level is 7 Planar diode (EPO)
   E21.361          Subclass E21.361 indent level is 7 Multi-layer diode, e.g., PNPN or NPNP diode (EPO)
   E21.362          Subclass E21.362 indent level is 7 Gat ed-diode structure, e.g., SITh, FCTh, FCD (EPO)
   E21.363          Subclass E21.363 indent level is 6 Resistor with PN junction (EPO)
   E21.364          Subclass E21.364 indent level is 6 Capacitor with PN - or Schottky junction, e.g., varactor (EPO)
   E21.365          Subclass E21.365 indent level is 6 Active layer is Group III-V compound (EPO)
   E21.366          Subclass E21.366 indent level is 7 Diode (EPO)
   E21.367          Subclass E21.367 indent level is 8 With an heterojunction, e.g., resonant tunneling diodes (RTD) (EPO)
   E21.368          Subclass E21.368 indent level is 8 Schottky diode (EPO)
   E21.369          Subclass E21.369 indent level is 5 Device comprising three or more electrodes (EPO)
   E21.37          Subclass E21.37 indent level is 6 Transistor (EPO)
   E21.371          Subclass E21.371 indent level is 7 Heterojunction transistor (EPO)
   E21.372          Subclass E21.372 indent level is 7 Bipolar thin film transistor (EPO)
   E21.373          Subclass E21.373 indent level is 7 Lateral transistor (EPO)
   E21.374          Subclass E21.374 indent level is 7 Schottky transistor (EPO)
   E21.375          Subclass E21.375 indent level is 7 Silicon vertical transistor (EPO)
   E21.376          Subclass E21.376 indent level is 8 Planar transistor (EPO)
   E21.377          Subclass E21.377 indent level is 8 Mesa-planar transistor (EPO)
   E21.378          Subclass E21.378 indent level is 8 Inverse transistor (EPO)
   E21.379          Subclass E21.379 indent level is 8 With single crystalline emitter, collector or base including extrinsic, link or graft base formed on th e silicon substrate, e.g., by epitaxy, recrystallization, after insulating device isolation (EPO)
   E21.38          Subclass E21.38 indent level is 8 Where main current goes through whole of silicon substrate, e.g., power bipolar transistor (EPO)
   E21.381          Subclass E21.381 indent level is 9 With a multi- emitter, e.g., interdigitated, multicellular, distributed (EPO)
   E21.382          Subclass E21.382 indent level is 7 Field-effect controlled bipolar-type transi stor, e.g., insulated gate bipolar transistor (IGBT) (EPO)
   E21.383          Subclass E21.383 indent level is 8 Vertical insulated gate bipolar transistor (EPO)
   E21.384          Subclass E21.384 indent level is 9 With recessed gate (EPO)
   E21.385          Subclass E21.385 indent level is 9 With recess formed by etching in source/emitter contact region (EPO)
   E21.386          Subclass E21.386 indent level is 7 Active layer, e.g., base, is Group III-V compound (EPO)
   E21.387          Subclass E21.387 indent level is 8 Heterojunction transistor (EPO)
   E21.388          Subclass E21.388 indent level is 6 Thyristor (EPO)
   E21.389          Subclass E21.389 indent level is 7 Lateral or planar thyristor (EPO)
   E21.39          Subclass E21.39 indent level is 7 Structurally associated with other devices (EPO)
   E21.391          Subclass E21.391 indent level is 8 Other device being a controlling device of the field-effect-type (EPO)
   E21.392          Subclass E21.392 indent level is 7 Bi-directional thyristor (EPO)
   E21.393          Subclass E21.393 indent level is 7 Active layer is Group III-V compound (EPO)
   E21.394          Subclass E21.394 indent level is 4 Multi-step process for the manufacture of unipolar device (EPO)
   E21.395          Subclass E21.395 indent level is 5 Transistor-like structure, e.g., hot electron transistor (HET); metal base transistor (MBT); resonant tunneling HET (RHET); resonant tunneling transistor (RTT ); bulk barrier transistor (BBT); planar doped barrier transistor (PDBT); charge injection transistor (CHINT); ballistic transistor (EPO)
   E21.396          Subclass E21.396 indent level is 5 Metal-insulator-semiconductor capacitor, e.g., trench capacitor (EPO)
   E21.397          Subclass E21.397 indent level is 6 Comprising PN junction, e.g., hybrid capacitor (EPO)
   E21.398          Subclass E21.398 indent level is 5 Active layer is Group III-V compound (EPO)
   E21.399          Subclass E21.399 indent level is 6 Transistor-like structure, e.g., hot electron transistor (HET), metal base transistor (MBT), resonant tunneling hot electron transistor (RHET), resonant tunneling transistor (RTT), bulk barrier transistor (BBT), planar doped barrier transistor (PDBT), charge injection transistor (CHINT) (EPO)
   E21.4          Subclass E21.4 indent level is 5 Field-effect transistor (EPO)
   E21.401          Subclass E21.401 indent level is 6 Using static field induced region, e.g., SIT, PBT (EPO)
   E21.402          Subclass E21.402 indent level is 7 Permeable base transistor (PBT) (EPO)
   E21.403          Subclass E21.403 indent level is 6 With heterojunction interface channel or gate, e.g., HFET, HIGFET, SISFET, HJFET, HEMT (EPO)
   E21.404          Subclass E21.404 indent level is 6 With one or zero or quasi-one or quasi-zero dimensional charge carrier gas channel, e.g., quantum wire FET; single electron trans istor (SET); striped channel transistor; coulomb blockade device (EPO)
   E21.405          Subclass E21.405 indent level is 6 Active layer is Group III-V compound, e.g., III-V velocity modulation transistor (VMT), NERFET (EPO)
   E21.406          Subclass E21.406 indent level is 7 Using static field induced region, e.g., SIT, PBT (EPO)
   E21.407          Subclass E21.407 indent level is 7 With an heterojunction interface channel or gate, e.g., HFET, HIGFET, SI SFET, HJFET, HEMT (EPO)
   E21.408          Subclass E21.408 indent level is 7 With one or zero or quasi-one or quasi-zero dimensional channel, e.g., in plane gate transistor (IPG), single electron transistor (SET), striped channel transistor, coulomb blockade device (EPO)
   E21.409          Subclass E21.409 indent level is 6 With an insulated gate (EPO)
   E21.41          Subclass E21.41 indent level is 7 Vertical transistor (EPO)
   E21.411          Subclass E21.411 indent level is 7 Thin film unipolar transistor (EPO)
   E21.412          Subclass E21.412 indent level is 8 Amorphous silicon or polysilicon transistor (EPO)
   E21.413          Subclass E21.413 indent level is 9 Lateral single gate single channel transistor with noninverted structure, i.e., channel layer is formed before gate (EPO)
   E21.414          Subclass E21.414 indent level is 9 Lateral single gate single channel transistor with inverted structure, i.e., channel layer is formed after gate (EPO)
   E21.415          Subclass E21.415 indent level is 8 Monocrystalline silicon transistor on insulating substrate, e.g., quartz substrate (EPO)
   E21.416          Subclass E21.416 indent level is 9 On sapphire substrate, e.g., silicon on sapphire (SOS) transistor (EPO)
   E21.417          Subclass E21.417 indent level is 7 With channel containing layer, e.g., p-base, fo rmed in or on drain region, e.g., DMOS transistor (EPO)
   E21.418          Subclass E21.418 indent level is 8 Vertical power DMOS transistor (EPO)
   E21.419          Subclass E21.419 indent level is 9 With recessed gate (EPO)
   E21.42          Subclass E21.42 indent level is 9 With recess formed by etching in source/base contact region (EPO)
   E21.421          Subclass E21.421 indent level is 7 With multiple gate, one gate having MOS structure and others having same or a different structure, i.e., non MOS, e.g., JFET gate (EPO)
   E21.422          Subclass E21.422 indent level is 7 With floating gate (EPO)
   E21.423          Subclass E21.423 indent level is 7 With charge trapping gate insulator, e.g., MNOS transistor (EPO)
   E21.424          Subclass E21.424 indent level is 7 Lateral single gate silicon transistor (EPO)
   E21.425          Subclass E21.425 indent level is 8 With source or drain region formed by Schottky barrier or conductor-insulator-semiconductor structure (EPO)
   E21.426          Subclass E21.426 indent level is 8 With single crystalline channel formed on the silicon substrate after insulating device isolation (EPO)
   E21.427          Subclass E21.427 indent level is 8 With asymmetry in channel direction, e.g., high-voltage lateral transistor with channel containing layer, e.g., p-base (EPO)
   E21.428          Subclass E21.428 indent level is 8 With a recessed gate, e.g., lateral U-MOS (EPO)
   E21.429          Subclass E21.429 indent level is 9 Using etching to form recess at gate location (EPO)
   E21.43          Subclass E21.43 indent level is 9 Recessing gate by adding semiconductor material at source (S) or drain (D) location, e.g., transist or with elevated single crystal S and D (EPO)
   E21.431          Subclass E21.431 indent level is 8 With source and drain recessed by etching or recessed and refi lled (EPO)
   E21.432          Subclass E21.432 indent level is 8 With source and drain contacts formation strictly before final gate formation, e.g., contact first technology (EPO)
   E21.433          Subclass E21.433 indent level is 8 Where the source and drain or source and drain extensions are self-aligned to sides of gate (EPO)
   E21.434          Subclass E21.434 indent level is 9 With initial gate mask or masking layer complementary to prospective gate location, e.g., with dummy source and drain contacts (EPO)
   E21.435          Subclass E21.435 indent level is 7 Lateral single gate single channel silicon transistor with both lightly doped source and drain extensions and source and drain self-aligned to sides of gate, e.g., LDD MOSFET, DDD MOSFET (EPO)
   E21.436          Subclass E21.436 indent level is 7 Gate comprising layer with ferroelectric properties (EPO)
   E21.437          Subclass E21.437 indent level is 7 With lightly doped drain selectively formed at side of gate (EPO)
   E21.438          Subclass E21.438 indent level is 7 Using self-aligned silicidation, i.e., salicide (EPO)
   E21.439          Subclass E21.439 indent level is 8 Providing different silicide thicknesses on gate and on source or drain (EPO)
   E21.44          Subclass E21.44 indent level is 7 Using self-aligned selective metal deposition simultaneously on gate and on source or drain (EPO)
   E21.441          Subclass E21.441 indent level is 7 Active layer is Group III-V compound (EPO)
   E21.442          Subclass E21.442 indent level is 7 With gate at side of channel (EPO)
   E21.443          Subclass E21.443 indent level is 7 Using self-aligned punch through stopper or threshold implant under gate region (EPO)
   E21.444          Subclass E21.444 indent level is 7 Using dummy gate wherein at least part of final gate is self-aligned to dummy gate (EPO)
   E21.445          Subclass E21.445 indent level is 6 With PN junction or heterojunction gate (EPO)
   E21.446          Subclass E21.446 indent level is 7 With PN homojunction gate (EPO)
   E21.447          Subclass E21.447 indent level is 8 Vertical transistor, e.g., tecnetrons (EPO)
   E21.448          Subclass E21.448 indent level is 7 With heterojunction gate (EPO)
   E21.449          Subclass E21.449 indent level is 7 Active layer is Group III-V compound (EPO)
   E21.45          Subclass E21.45 indent level is 6 With Schottky gate, e.g., MESFET (EPO)
   E21.451          Subclass E21.451 indent level is 7 Active layer being Group III-V compound (EPO)
   E21.452          Subclass E21.452 indent level is 8 Lateral single-gate transistors (EPO)
   E21.453          Subclass E21.453 indent level is 9 Process wherein final gate is made after formation of source and drain regions in active layer, e.g., dummy-gate process (EPO)
   E21.454          Subclass E21.454 indent level is 9 Process wherein final gate is made before formation, e.g., activation anneal, of source and drain regions in active layer (EPO)
   E21.455          Subclass E21.455 indent level is 9 Lateral transistor with two or more independen t gates (EPO)
   E21.456          Subclass E21.456 indent level is 5 Charge transfer device (EPO)
   E21.457          Subclass E21.457 indent level is 6 With insulated gate (EPO)
   E21.458          Subclass E21.458 indent level is 6 With Schottky gate (EPO)
   E21.459          Subclass E21.459 indent level is 3 Device having semiconductor body other than carbon, Si, Ge, SiC, Se, Te, Cu 2 O, CuI, and Group III-V compounds with or without impurities, e.g., doping materials (EPO)
   E21.46          Subclass E21.46 indent level is 4 Multistep process (EPO)
   E21.461          Subclass E21.461 indent level is 4 Deposition of semiconductor material on substrate, e.g., epitaxial growth (EPO)
   E21.462          Subclass E21.462 indent level is 5 Using physical deposition, e.g., vacuum deposition, sputtering (EPO)
   E21.463          Subclass E21.463 indent level is 5 Using reduction or decomposition of gaseous compound yielding solid condensate, i.e., chemical deposition (EPO)
   E21.464          Subclass E21.464 indent level is 5 Using liquid deposition (EPO)
   E21.465          Subclass E21.465 indent level is 6 From molten solution of compound or alloy, e.g., liquid phase epitaxy (EPO)
   E21.466          Subclass E21.466 indent level is 4 Diffusion of impurity material, e.g., dopant, electrode material, into or out of semiconductor body, or between semiconductor regions (EPO)
   E21.467          Subclass E21.467 indent level is 5 Using diffusion into or out of solid from or into gaseous phase (EPO)
   E21.468          Subclass E21.468 indent level is 5 Using diffusion into or out of solid from or into solid phase, e.g., doped oxide layer (EPO)
   E21.469          Subclass E21.469 indent level is 5 Using diffusion into or out of solid from or into liquid phase, e.g., alloy diffusion process (EPO)
   E21.47          Subclass E21.47 indent level is 4 Alloying of impurity material, e.g., dopant, electrode material, with semiconductor body (EPO)
   E21.471          Subclass E21.471 indent level is 4 Radiation treatment (EPO)
   E21.472          Subclass E21.472 indent level is 5 With high-energy radiation (EPO)
   E21.473          Subclass E21.473 indent level is 6 Producing ion implantation (EPO)
   E21.474          Subclass E21.474 indent level is 7 Using mask (EPO)
   E21.475          Subclass E21.475 indent level is 6 Using electromagnetic radiation, e.g., laser radiation (EPO)
   E21.476          Subclass E21.476 indent level is 4 Manufacture of electrodes on semiconductor bodies using processes or apparatus other than epitaxial growth, e.g., coating, diffusion, or alloying, or radiation treatment (EPO)
   E21.477          Subclass E21.477 indent level is 5 Deposition of conductive or insulating materials for electrode (EPO)
   E21.478          Subclass E21.478 indent level is 6 From gas or vapor, e.g., condensation (EPO)
   E21.479          Subclass E21.479 indent level is 6 From liquid, e.g., electrolytic deposition (EPO)
   E21.48          Subclass E21.48 indent level is 5 Involving application of pressure, e.g., thermo compression bonding (EPO)
   E21.481          Subclass E21.481 indent level is 5 Including application of mechanical vibration, e.g., ultrasonic vibration (EPO)
   E21.482          Subclass E21.482 indent level is 4 Treatment of semiconductor body using process other than electromagnetic radiation (EPO)
   E21.483          Subclass E21.483 indent level is 5 To change their surface-physical characteristics or shape, e.g., etching, polishing, cutting (EPO)
   E21.484          Subclass E21.484 indent level is 6 Mechanical treatment, e.g., grinding, ultrasonic treatment (EPO)
   E21.485          Subclass E21.485 indent level is 6 Chemical or electrical treatment, e.g., electrolytic etching (EPO)
   E21.486          Subclass E21.486 indent level is 7 Using mask (EPO)
   E21.487          Subclass E21.487 indent level is 6 To form insulating layer thereon, e.g., for masking or by using photolithographic techniques; post treatment of these layers (EPO)
   E21.488          Subclass E21.488 indent level is 7 Using mask (EPO)
   E21.489          Subclass E21.489 indent level is 7 Post treatment of insulating layer (EPO)
   E21.49          Subclass E21.49 indent level is 8 Etching layer (EPO)
   E21.491          Subclass E21.491 indent level is 8 Doping layer (EPO)
   E21.492          Subclass E21.492 indent level is 7 Organic layer, e.g., photoresist (EPO)
   E21.493          Subclass E21.493 indent level is 7 Inorganic layer (EPO)
   E21.494          Subclass E21.494 indent level is 8 Composed of oxide or glassy oxide or oxide-based glass (EPO)
   E21.495          Subclass E21.495 indent level is 6 Deposition of noninsulating, e.g., conductive -, resistive -, layer on insulating layer (EPO)
   E21.496          Subclass E21.496 indent level is 7 Post treatment of layer (EPO)
   E21.497          Subclass E21.497 indent level is 5 Thermal treatment for modifying property of semiconductor body, e.g., annealing, sintering (EPO)
   E21.498          Subclass E21.498 indent level is 5 Application of electric current or fields, e.g., for electroforming (EPO)
   E21.499          Subclass E21.499 indent level is 3 Assembling semiconductor devices, e.g., packaging , including mounting, encapsulating, or treatment of packaged semiconductor (EPO)
   E21.5          Subclass E21.5 indent level is 4 Mounting semiconductor bodies in container (EPO)
   E21.501          Subclass E21.501 indent level is 4 Providing fillings in container, e.g., gas fillings (EPO)
   E21.502          Subclass E21.502 indent level is 4 Encapsulation, e.g., encapsulation layer, coating (EPO)
   E21.503          Subclass E21.503 indent level is 5 Encapsulation of active face of flip chip device, e.g., under filling or under encapsulation of flip-chip, encapsulation perform on chip or mounting substrate (EPO)
   E21.504          Subclass E21.504 indent level is 5 Moulds (EPO)
   E21.505          Subclass E21.505 indent level is 4 Insulative mounting semiconductor device on support (EPO)
   E21.506          Subclass E21.506 indent level is 4 Attaching or detaching leads or other conductive members, to be used for carrying current to or from device in operation (EPO)
   E21.507          Subclass E21.507 indent level is 5 Formation of contacts to semiconductor by use of metal layers separated by insulating layers, e.g., self-aligned contacts to source/drain or emitter/base (EPO)
   E21.508          Subclass E21.508 indent level is 6 Forming solder bumps (EPO)
   E21.509          Subclass E21.509 indent level is 5 Involving soldering or alloying process, e.g., soldering wires (EPO)
   E21.51          Subclass E21.51 indent level is 6 Mounting on metallic conductive member (EPO)
   E21.511          Subclass E21.511 indent level is 6 Mounting on insulating member provided with metallic leads, e.g., flip-chip mounting, conductive die mounting (EPO)
   E21.512          Subclass E21.512 indent level is 7 Right-up bonding (EPO)
   E21.513          Subclass E21.513 indent level is 6 Mounting on semiconductor conductive member (EPO)
   E21.514          Subclass E21.514 indent level is 5 Involving use of conductive adhesive (EPO)
   E21.515          Subclass E21.515 indent level is 5 Involving use of mechanical auxiliary part without use of alloying or soldering process, e.g., pressure contacts (EPO)
   E21.516          Subclass E21.516 indent level is 5 Involving automation techniques using film carriers (EPO)
   E21.517          Subclass E21.517 indent level is 5 Involving use of electron or laser beam (EPO)
   E21.518          Subclass E21.518 indent level is 5 Involving application of mechanical vibration, e.g., ultrasonic vibration (EPO)
   E21.519          Subclass E21.519 indent level is 5 Involving application of pressure, e.g., thermo-compression bonding (EPO)
   E21.52          Subclass E21.52 indent level is 2 Devices having no potential-jump barrier or surface barrier (EPO)
   E21.521          Subclass E21.521 indent level is 1 Testing or measuring during manufacture or treatment or reliability measurement, i.e., testing of parts followed by no processing which modifies parts as such (EPO)
   E21.522          Subclass E21.522 indent level is 2 Structural arrangement (EPO)
   E21.523          Subclass E21.523 indent level is 3 Additional lead-in metallization on device, e.g., additional pads or lands, lines in scribe line, sacrificed conductors, sacrificed frames (EPO)
   E21.524          Subclass E21.524 indent level is 3 Circuit for characterizing or monitoring manufacturing process, e.g., whole test die, wafer filled with test structures, onboard devices incorporated on each die, process/product control monitors or PCM, devices in scribe-line/kerf, drop-in devices (EPO)
   E21.525          Subclass E21.525 indent level is 2 Procedures, i.e., sequence of activities consisting of plurality of measurement and correction, marking or sorting steps (EPO)
   E21.526          Subclass E21.526 indent level is 3 Connection or disconnection of subentities or redundant parts of device in response to measurement, e.g., wafer scale, memory devices (EPO)
   E21.527          Subclass E21.527 indent level is 3 Optical enhancement of defects or not directly visible states, e.g., selective electrolytic deposition, bubbles in liquids, light emission, color change (EPO)
   E21.528          Subclass E21.528 indent level is 3 Acting in response to ongoing measurement without interruption of processing, e.g., endpoint detection, in-situ thickness measurement (EPO)
   E21.529          Subclass E21.529 indent level is 2 Measuring as part of manufacturing process (EPO)
   E21.53          Subclass E21.53 indent level is 3 For structural parameters, e.g., thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions (EPO)
   E21.531          Subclass E21.531 indent level is 3 For electrical parameters, e.g., resistance, deep-levels, CV, diffusions by electrical means (EPO)
   E21.532          Subclass E21.532 indent level is 1 Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (EPO)
   E21.533          Subclass E21.533 indent level is 2 Of thick- or thin-film circuits or parts thereof (EPO)
   E21.534          Subclass E21.534 indent level is 3 Of thick-film circuits or parts thereof (EPO)
   E21.535          Subclass E21.535 indent level is 3 Of thin-film circuits or parts thereof (EPO)
   E21.536          Subclass E21.536 indent level is 2 Manufacture of specific parts of devices (EPO)
   E21.537          Subclass E21.537 indent level is 3 Making of localized buried regions, e.g., buried collector layer, internal connection, substrate contacts (EPO)
   E21.538          Subclass E21.538 indent level is 4 Making of internal connections, substrate contacts (EPO)
   E21.539          Subclass E21.539 indent level is 4 For Group III-V compound semiconductor integrated circuits (EPO)
   E21.54          Subclass E21.54 indent level is 3 Making of isolation regions between components (EPO)
   E21.541          Subclass E21.541 indent level is 4 Between components manufactured in active substrate comprising SiC compound semiconductor (EPO)
   E21.542          Subclass E21.542 indent level is 4 Between components manufactured in active substrate comprising Group III-V compound semiconductor (EPO)
   E21.543          Subclass E21.543 indent level is 4 Between components manufactured in active substrate comprising Group II-VI compound semiconductor (EPO)
   E21.544          Subclass E21.544 indent level is 4 PN junction isolation (EPO)
   E21.545          Subclass E21.545 indent level is 4 Dielectric regions, e.g., EPIC dielectric isolation, LOCOS; trench refilling techniques, SOI technology, use of channel stoppers (EPO)
   E21.546          Subclass E21.546 indent level is 5 Using trench refilling with dielectric materials (EPO)
   E21.547          Subclass E21.547 indent level is 6 Dielectric material being obtained by full chemical transformation of nondielectric materials, such as polycrystalline silicon, metals (EPO)
   E21.548          Subclass E21.548 indent level is 6 Concurrent filling of plurality of trenches having different trench shape or dimension, e.g., rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches (EPO)
   E21.549          Subclass E21.549 indent level is 6 Of trenches having shape other than rectangular or V shape, e.g., rounded corners, oblique or rounded trench walls (EPO)
   E21.55          Subclass E21.55 indent level is 7 Trench shape altered by local oxidation of silicon process step, e.g., trench corner rounding by LOCOS (EPO)
   E21.551          Subclass E21.551 indent level is 6 Introducing impurities in trench side or bottom walls, e.g., for forming channel stoppers or alter isolation behavior (EPO)
   E21.552          Subclass E21.552 indent level is 5 Using local oxidation of silicon, e.g., LOCOS, SWAMI, SILO (EPO)
   E21.553          Subclass E21.553 indent level is 6 In region recessed from surface, e.g., in recess, groove, tub or trench region (EPO)
   E21.554          Subclass E21.554 indent level is 7 Using auxiliary pillars in recessed region, e.g., to form LOCOS over extended areas (EPO)
   E21.555          Subclass E21.555 indent level is 7 Recessed region having shape other than rectangular, e.g., rounded or oblique shape (EPO)
   E21.556          Subclass E21.556 indent level is 6 Introducing electrical inactive or active impurities in local oxidation region, e.g., to alter LOCOS oxide growth characteristics or for additional isolation purpose (EPO)
   E21.557          Subclass E21.557 indent level is 7 Introducing electrical active impurities in local oxidation region solely for forming channel stoppers (EPO)
   E21.558          Subclass E21.558 indent level is 8 Introducing both types of electrical active impurities in local oxidation region solely for forming channel stoppers, e.g., for isolation of complementary doped regions (EPO)
   E21.559          Subclass E21.559 indent level is 6 With plurality of successive local oxidation steps (EPO)
   E21.56          Subclass E21.56 indent level is 5 Dielectric isolation using EPIC technique, i.e., epitaxial passivated integrated circuit (EPO)
   E21.561          Subclass E21.561 indent level is 5 Using semiconductor or insulator technology, i.e., SOI technology (EPO)
   E21.562          Subclass E21.562 indent level is 6 Using selective deposition of single crystal silicon, e.g., Selective Epitaxial Growth (SEG) (EPO)
   E21.563          Subclass E21.563 indent level is 6 Using silicon implanted buried insulating layers, e.g., oxide layers, i.e., SIMOX technique (EPO)
   E21.564          Subclass E21.564 indent level is 6 SOI together with lateral isolation, e.g., using local oxidation of silicon, or dielectric or polycrystalline material refilled trench or air gap isolation regions, e.g., completely isolated semiconductor islands (EPO)
   E21.565          Subclass E21.565 indent level is 6 Using full isolation by porous oxide silicon, i.e., FIPOS technique (EPO)
   E21.566          Subclass E21.566 indent level is 6 Using lateral overgrowth technique, i.e., ELO techniques (EPO)
   E21.567          Subclass E21.567 indent level is 6 Using bonding technique (EPO)
   E21.568          Subclass E21.568 indent level is 7 With separation/delamination along ion implanted layer, e.g., "Smart-cut", "Unibond" (EPO)
   E21.569          Subclass E21.569 indent level is 7 Using silicon etch back technique, e.g., BESOI, ELTRAN (EPO)
   E21.57          Subclass E21.57 indent level is 7 With separation/delamination along porous layer (EPO)
   E21.571          Subclass E21.571 indent level is 5 Using selective deposition of single crystal silicon, i.e., SEG technique (EPO)
   E21.572          Subclass E21.572 indent level is 4 Polycrystalline semiconductor regions (EPO)
   E21.573          Subclass E21.573 indent level is 4 Air gaps (EPO)
   E21.574          Subclass E21.574 indent level is 4 Isolation by field effect (EPO)
   E21.575          Subclass E21.575 indent level is 3 Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (EPO)
   E21.576          Subclass E21.576 indent level is 4 Characterized by formation and post treatment of dielectrics, e.g., planarizing (EPO)
   E21.577          Subclass E21.577 indent level is 5 By forming via holes (EPO)
   E21.578          Subclass E21.578 indent level is 6 Tapered via holes (EPO)
   E21.579          Subclass E21.579 indent level is 6 For "dual damascene" type structures (EPO)
   E21.58          Subclass E21.58 indent level is 5 Planarizing dielectric (EPO)
   E21.581          Subclass E21.581 indent level is 5 Dielectric comprising air gaps (EPO)
   E21.582          Subclass E21.582 indent level is 5 Characterized by formation and post treatment of conductors, e.g., patterning (EPO)
   E21.583          Subclass E21.583 indent level is 5 Planarization; smoothing (EPO)
   E21.584          Subclass E21.584 indent level is 5 Barrier, adhesion or liner layer (EPO)
   E21.585          Subclass E21.585 indent level is 5 Filling of holes, grooves, vias or trenches with conductive material (EPO)
   E21.586          Subclass E21.586 indent level is 6 By selective deposition of conductive material in vias, e.g., selective chemical vapor deposition on semiconductor material, plating (EPO)
   E21.587          Subclass E21.587 indent level is 6 By deposition over sacrificial masking layer, e.g., lift-off (EPO)
   E21.588          Subclass E21.588 indent level is 6 Reflowing or applying pressure to fill contact hole, e.g., to remove voids (EPO)
   E21.589          Subclass E21.589 indent level is 5 By forming conductive members before deposition of protective insulating material, e.g., pillars, studs (EPO)
   E21.59          Subclass E21.59 indent level is 5 Local interconnects; local pads (EPO)
   E21.591          Subclass E21.591 indent level is 5 Modifying pattern or conductivity of conductive members, e.g., formation of alloys, reduction of contact resistances (EPO)
   E21.592          Subclass E21.592 indent level is 6 By altering solid-state characteristics of conductive members, e.g., fuses, in situ oxidation, laser melting (EPO)
   E21.593          Subclass E21.593 indent level is 6 By forming silicide of refractory metal (EPO)
   E21.594          Subclass E21.594 indent level is 6 By using super-conducting material (EPO)
   E21.595          Subclass E21.595 indent level is 6 Modifying pattern (EPO)
   E21.596          Subclass E21.596 indent level is 7 Using laser, e.g., laser cutting, laser direct writing, laser repair (EPO)
   E21.597          Subclass E21.597 indent level is 4 Formed through semiconductor substrate (EPO)
   E21.598          Subclass E21.598 indent level is 2 Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (EPO)
   E21.599          Subclass E21.599 indent level is 3 With subsequent division of substrate into plural individual devices (EPO)
   E21.6          Subclass E21.6 indent level is 4 Involving separation of active layers from substrate (EPO)
   E21.601          Subclass E21.601 indent level is 5 Leaving reusable substrate, e.g., epitaxial lift-off process (EPO)
   E21.602          Subclass E21.602 indent level is 4 To produce devices each consisting of plurality of components, e.g., integrated circuits (EPO)
   E21.603          Subclass E21.603 indent level is 5 Substrate is semiconductor, using combination of semiconductor substrates, e.g., diamond, SiC, Si, Group III-V compound, and/or Group II-VI compound semiconductor substrates (EPO)
   E21.604          Subclass E21.604 indent level is 5 Substrate is semiconductor, using diamond technology (EPO)
   E21.605          Subclass E21.605 indent level is 5 Substrate is semiconductor, using SiC technology (EPO)
   E21.606          Subclass E21.606 indent level is 5 Substrate being semiconductor, using silicon technology (EPO)
   E21.608          Subclass E21.608 indent level is 6 Bipolar technology (EPO)
   E21.609          Subclass E21.609 indent level is 7 Comprising combination of vertical and lateral transistors (EPO)
   E21.61          Subclass E21.61 indent level is 7 Comprising merged transistor logic or integrated injection logic (EPO)
   E21.611          Subclass E21.611 indent level is 7 Complementary devices, e.g., complementary transistors (EPO)
   E21.612          Subclass E21.612 indent level is 8 Complementary vertical transistors (EPO)
   E21.613          Subclass E21.613 indent level is 7 Memory structures (EPO)
   E21.614          Subclass E21.614 indent level is 6 Three-dimensional integrated circuits stacked in different levels (EPO)
   E21.615          Subclass E21.615 indent level is 6 Field-effect technology (EPO)
   E21.616          Subclass E21.616 indent level is 7 MIS technology (EPO)
   E21.617          Subclass E21.617 indent level is 8 Combination of charge coupled devices, i.e., CCD or BBD (EPO)
   E21.618          Subclass E21.618 indent level is 8 With particular manufacturing method of channel, e.g., channel implants, halo or pocket implants, or channel materials (EPO)
   E21.619          Subclass E21.619 indent level is 8 With particular manufacturing method of source or drain, e.g., specific S or D implants or silicided S or D structures or raised S or D structures (EPO)
   E21.62          Subclass E21.62 indent level is 9 Manufacturing common source or drain regions between plurality of conductor-insulator-semiconductor structures (EPO)
   E21.621          Subclass E21.621 indent level is 8 With particular manufacturing method of gate conductor, e.g., particular materials, shapes (EPO)
   E21.622          Subclass E21.622 indent level is 9 Silicided or salicided gate conductors (EPO)
   E21.623          Subclass E21.623 indent level is 9 Gate conductors with different gate conductor materials or different gate conductor implants, e.g., dual gate structures (EPO)
   E21.624          Subclass E21.624 indent level is 9 Gate conductors with different shapes, lengths or dimensions (EPO)
   E21.625          Subclass E21.625 indent level is 8 With particular manufacturing method of gate insulating layer, e.g., different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants (EPO)
   E21.626          Subclass E21.626 indent level is 8 With particular manufacturing method of gate sidewall spacers, e.g., double spacers, particular spacer material or shape (EPO)
   E21.627          Subclass E21.627 indent level is 8 Interconnection or wiring or contact manufacturing related aspects (EPO)
   E21.628          Subclass E21.628 indent level is 8 Isolation region manufacturing related aspects, e.g., to avoid interaction of isolation region with adjacent structure (EPO)
   E21.629          Subclass E21.629 indent level is 8 With particular manufacturing method of vertical transistor structures, i.e., with channel vertical to substrate surface (EPO)
   E21.63          Subclass E21.63 indent level is 8 With particular manufacturing method of wells or tubs, e.g., twin tubs, high energy well implants, buried implanted layers for lateral isolation (BILLI) (EPO)
   E21.631          Subclass E21.631 indent level is 8 Combination of enhancement and depletion transistors (EPO)
   E21.632          Subclass E21.632 indent level is 8 Complementary field-effect transistors, e.g., CMOS (EPO)
   E21.633          Subclass E21.633 indent level is 9 With particular manufacturing method of channel, e.g., channel implants, halo or pocket implants, or channel materials (EPO)
   E21.634          Subclass E21.634 indent level is 9 With particular manufacturing method of source or drain, e.g., specific S or D implants or silicided S or D structures or raised S or D structures (EPO)
   E21.635          Subclass E21.635 indent level is 9 With particular manufacturing method of gate conductor, e.g., particular materials, shapes (EPO)
   E21.636          Subclass E21.636 indent level is 10 Silicided or salicided gate conductors (EPO)
   E21.637          Subclass E21.637 indent level is 10 Gate conductors with different gate conductor materials or different gate conductor implants, e.g., dual gate structures (EPO)
   E21.638          Subclass E21.638 indent level is 10 Gate conductors with different shapes, lengths or dimensions (EPO)
   E21.639          Subclass E21.639 indent level is 9 With particular manufacturing method of gate insulating layer, e.g., different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants (EPO)
   E21.64          Subclass E21.64 indent level is 9 With particular manufacturing method of gate sidewall spacers, e.g., double spacers, particular spacer material or shape (EPO)
   E21.641          Subclass E21.641 indent level is 9 Interconnection or wiring or contact manufacturing related aspects (EPO)
   E21.642          Subclass E21.642 indent level is 9 Isolation region manufacturing related aspects, e.g., to avoid interaction of isolation region with adjacent structure (EPO)
   E21.643          Subclass E21.643 indent level is 9 With particular manufacturing method of vertical transistor structures, i.e., with channel vertical to substrate surface (EPO)
   E21.644          Subclass E21.644 indent level is 8 With particular manufacturing method of wells or tubs, e.g., twin tubs, high energy well implants, buried implanted layers for lateral isolation (BILLI) (EPO)
   E21.645          Subclass E21.645 indent level is 8 Memory structures (EPO)
   E21.646          Subclass E21.646 indent level is 8 Dynamic random access memory structures (DRAM) (EPO)
   E21.647          Subclass E21.647 indent level is 9 Characterized by type of capacitor (EPO)
   E21.648          Subclass E21.648 indent level is 10 Capacitor stacked over transfer transis tor (EPO)
   E21.649          Subclass E21.649 indent level is 11 Making connection between transistor and capacitor, e.g., plug (EPO)
   E21.65          Subclass E21.65 indent level is 11 Capacitor extending under transfer transistor area (EPO)
   E21.651          Subclass E21.651 indent level is 11 Capacitor in U- or V-shaped trench in substrate (EPO)
   E21.652          Subclass E21.652 indent level is 12 In combination with vertical transistor (EPO)
   E21.653          Subclass E21.653 indent level is 12 Making connection between transistor and capacitor, e.g., buried strap (EPO)
   E21.654          Subclass E21.654 indent level is 10 Characterized by type of transistor; manufacturing of transistor (EPO)
   E21.655          Subclass E21.655 indent level is 11 Transistor in U- or V-shaped trench in substrate (EPO)
   E21.656          Subclass E21.656 indent level is 10 Characterized by data lines (EPO)
   E21.657          Subclass E21.657 indent level is 11 Making bit line (EPO)
   E21.658          Subclass E21.658 indent level is 11 Making bit line contact (EPO)
   E21.659          Subclass E21.659 indent level is 11 Making word line (EPO)
   E21.66          Subclass E21.66 indent level is 10 Simultaneous fabrication of periphery and memory cells (EPO)
   E21.661          Subclass E21.661 indent level is 9 Static random access memory structures (SRAM) (EPO)
   E21.662          Subclass E21.662 indent level is 9 Read-only memory structures (ROM), i.e., nonvolatile memory structures (EPO)
   E21.663          Subclass E21.663 indent level is 10 Ferroelectric nonvolatile memory structures (EPO)
   E21.664          Subclass E21.664 indent level is 11 With ferroelectric capacitor (EPO)
   E21.665          Subclass E21.665 indent level is 10 Magnetic nonvolatile memory structures, e.g., MRAM (EPO)
   E21.666          Subclass E21.666 indent level is 10 PROM (EPO)
   E21.667          Subclass E21.667 indent level is 10 ROM only (EPO)
   E21.668          Subclass E21.668 indent level is 11 With source and drain on same level, e.g., lateral channel (EPO)
   E21.669          Subclass E21.669 indent level is 12 Source or drain contact programmed (EPO)
   E21.67          Subclass E21.67 indent level is 12 Gate contact programmed (EPO)
   E21.671          Subclass E21.671 indent level is 12 Doping programmed, e.g., mask ROM (EPO)
   E21.672          Subclass E21.672 indent level is 13 Entire channel doping programmed (EPO)
   E21.673          Subclass E21.673 indent level is 13 Source or drain doping programmed (EPO)
   E21.674          Subclass E21.674 indent level is 12 Gate programmed, e.g., different gate material or no gate (EPO)
   E21.675          Subclass E21.675 indent level is 12 Gate dielectric programmed, e.g., different thickness (EPO)
   E21.676          Subclass E21.676 indent level is 11 With source and drain on different levels, e.g., vertical channel (EPO)
   E21.677          Subclass E21.677 indent level is 11 With FETs on different levels, e.g., 3D ROM (EPO)
   E21.678          Subclass E21.678 indent level is 11 Simultaneous fabrication of periphery and memory cells (EPO)
   E21.679          Subclass E21.679 indent level is 10 Charge trapping insulator nonvolatile memory structures (EPO)
   E21.68          Subclass E21.68 indent level is 10 Electrically programmable (EPROM), i.e., floating gate memory structures (EPO)
   E21.681          Subclass E21.681 indent level is 11 With conductive layer as control gate (EPO)
   E21.682          Subclass E21.682 indent level is 12 With source and drain on same level and without cell select transistor (EPO)
   E21.683          Subclass E21.683 indent level is 13 Simultaneous fabrication of periphery and memory cells (EPO)
   E21.684          Subclass E21.684 indent level is 14 Including one type of peripheral FET (EPO)
   E21.685          Subclass E21.685 indent level is 15 Control gate layer used for peripheral FET (EPO)
   E21.686          Subclass E21.686 indent level is 15 Intergate dielectric layer used for peripheral FET (EPO)
   E21.687          Subclass E21.687 indent level is 15 Floating gate layer used for peripheral FET (EPO)
   E21.688          Subclass E21.688 indent level is 15 Floating gate dielectric layer used for peripheral FET (EPO)
   E21.689          Subclass E21.689 indent level is 14 Including different types of peripheral FETs (EPO)
   E21.69          Subclass E21.69 indent level is 12 With source and drain on same level and with cell select transistor (EPO)
   E21.691          Subclass E21.691 indent level is 13 Simultaneous fabrication of periphery and memory cells (EPO)
   E21.692          Subclass E21.692 indent level is 12 With source and drain on different levels, e.g., sloping channel (EPO)
   E21.693          Subclass E21.693 indent level is 13 For vertical channel (EPO)
   E21.694          Subclass E21.694 indent level is 11 With doped region as control gate (EPO)
   E21.695          Subclass E21.695 indent level is 6 Combination of bipolar and field-effect technologies (EPO)
   E21.696          Subclass E21.696 indent level is 7 Bipolar and MOS technologies (EPO)
   E21.697          Subclass E21.697 indent level is 5 Substrate is Group III-V semiconductor (EPO)
   E21.698          Subclass E21.698 indent level is 5 Substrate is Group II-VI semiconductor (EPO)
   E21.699          Subclass E21.699 indent level is 5 Substrate is semiconductor other than diamond, SiC, Si, Group III-V compound, or Group II-VI compound (EPO)
   E21.7          Subclass E21.7 indent level is 4 Substrate is nonsemiconductor body, e.g., insulating body (EPO)
   E21.701          Subclass E21.701 indent level is 5 Substrate is sapphire, e.g., silicon on sapphire structure (SOS) (EPO)
   E21.702          Subclass E21.702 indent level is 5 To produce devices, each consisting of single circuit element (EPO)
   E21.703          Subclass E21.703 indent level is 5 Substrate is semiconductor body (EPO)
   E21.704          Subclass E21.704 indent level is 6 Substrate is nonsemiconductor body, e.g., insulating body (EPO)
   E21.705          Subclass E21.705 indent level is 2 Assembly of devices consisting of solid-state components formed in or on a common substrate; assembly of integrated circuit devices (EPO)
 
CROSS-REFERENCE ART COLLECTIONS
 
[List of Patents for class 257 subclass 900]  900           MOSFET TYPE GATE SIDEWALL INSULATING SPACER
[List of Patents for class 257 subclass 901]  901           MOSFET SUBSTRATE BIAS
[List of Patents for class 257 subclass 902]  902           FET WITH METAL SOURCE REGION
[List of Patents for class 257 subclass 903]  903           FET CONFIGURATION ADAPTED FOR USE AS STATIC MEMORY CELL
[List of Patents for class 257 subclass 904]  904           Subclass 904 indent level is 1 WITH PASSIVE COMPONENTS, (e.g., POLYSILICON RESISTORS)
[List of Patents for class 257 subclass 905]  905           PLURAL DRAM CELLS SHARE COMMON CONTACT OR COMMON TRENCH
[List of Patents for class 257 subclass 906]  906           DRAM WITH CAPACITOR ELECTRODES USED FOR ACCESSING (E.G., BIT LINE IS CAPACITOR PLATE)
[List of Patents for class 257 subclass 907]  907           FOLDED BIT LINE DRAM CONFIGURATION
[List of Patents for class 257 subclass 908]  908           DRAM CONFIGURATION WITH TRANSISTORS AND CAPACITORS OF PAIRS OF CELLS ALONG A STRAIGHT LINE BETWEEN ADJACENT BIT LINES
[List of Patents for class 257 subclass 909]  909           MACROCELL ARRAYS (E.G., GATE ARRAYS WITH VARIABLE SIZE OR CONFIGURATION OF CELLS)
[List of Patents for class 257 subclass 910]  910           DIODE ARRAYS (E.G., DIODE READ-ONLY MEMORY ARRAY)
[List of Patents for class 257 subclass 911]  911           LIGHT SENSITIVE ARRAY ADAPTED TO BE SCANNED BY ELECTRON BEAM (E.G.,VIDICON DEVICE)
[List of Patents for class 257 subclass 912]  912           CHARGE TRANSFER DEVICE USING BOTH ELECTRON AND HOLE SIGNAL CARRIERS
[List of Patents for class 257 subclass 913]  913           WITH MEANS TO ABSORB OR LOCALIZE UNWANTED IMPURITIES OR DEFECTS FROM SEMICONDUCTORS (E.G., HEAVY METAL GETTERING)
[List of Patents for class 257 subclass 914]  914           POLYSILICON CONTAINING OXYGEN, NITROGEN, OR CARBON (E.G., SIPOS)
[List of Patents for class 257 subclass 915]  915           WITH TITANIUM NITRIDE PORTION OR REGION
[List of Patents for class 257 subclass 916]  916           NARROW BAND GAP SEMICONDUCTOR MATERIAL (>>1EV)
[List of Patents for class 257 subclass 917]  917           PLURAL DOPANTS OF SAME CONDUCTIVITY TYPE IN SAME REGION
[List of Patents for class 257 subclass 918]  918           LIGHT EMITTING REGENERATIVE SWITCHING DEVICE (E.G., LIGHT EMITTING SCR) ARRAYS, CIRCUITRY, ETC.
[List of Patents for class 257 subclass 919]  919           ELEMENTS OF SIMILAR CONSTRUCTION CONNECTED IN SERIES OR PARALLEL TO AVERAGE OUT MANUFACTURING VARIATIONS IN CHARACTERISTICS
[List of Patents for class 257 subclass 920]  920           CONDUCTOR LAYERS ON DIFFERENT LEVELS CONNECTED IN PARALLEL (E.G., TO REDUCE RESISTANCE)
[List of Patents for class 257 subclass 921]  921           RADIATION HARDENED SEMICONDUCTOR DEVICE
[List of Patents for class 257 subclass 922]  922           WITH MEANS TO PREVENT INSPECTION OF OR TAMPERING WITH AN INTEGRATED CIRCUIT (E.G., "SMART CARD", ANTI-TAMPER)
[List of Patents for class 257 subclass 923]  923           WITH MEANS TO OPTIMIZE ELECTRICAL CONDUCTOR CURRENT CARRYING CAPACITY (E.G., PARTICULAR CONDUCTOR ASPECT RATIO)
[List of Patents for class 257 subclass 924]  924           WITH PASSIVE DEVICE (E.G., CAPACITOR), OR BATTERY, AS INTEGRAL PART OF HOUSING OR HOUSING ELEMENT (E.G., CAP)
[List of Patents for class 257 subclass 925]  925           BRIDGE RECTIFIER MODULE
[List of Patents for class 257 subclass 926]  926           ELONGATED LEAD EXTENDING AXIALLY THROUGH ANOTHER ELONGATED LEAD
[List of Patents for class 257 subclass 927]  927           DIFFERENT DOPING LEVELS IN DIFFERENT PARTS OF PN JUNCTION TO PRODUCE SHAPED DEPLETION LAYER
[List of Patents for class 257 subclass 928]  928           WITH SHORTED PN OR SCHOTTKY JUNCTION OTHER THAN EMITTER JUNCTION
[List of Patents for class 257 subclass 929]  929           PN JUNCTION ISOLATED INTEGRATED CIRCUIT WITH ISOLATION WALLS HAVING MINIMUM DOPANT CONCENTRATION AT INTERMEDIATE DEPTH IN EPITAXIAL LAYER (E.G., DIFFUSED FROM BOTH SURFACES OF EPITAXIAL LAYER)
[List of Patents for class 257 subclass 930]  930           THERMOELECTRIC (E.G., PELTIER EFFECT) COOLING
 
FOREIGN ART COLLECTIONS
 
   FOR000          CLASS-RELATED FOREIGN DOCUMENTS

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