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[Search a list of Patent Appplications for class 710]  Class   710ELECTRICAL COMPUTERS AND DIGITAL DATA PROCESSING SYSTEMS: INPUT/OUTPUT
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[List of Patents for class 710 subclass 1]  1           INPUT/OUTPUT DATA PROCESSING
[List of Patents for class 710 subclass 2]  2           Subclass 2 indent level is 1 Input/Output expansion
[List of Patents for class 710 subclass 3]  3           Subclass 3 indent level is 1 Input/Output addressing
[List of Patents for class 710 subclass 4]  4           Subclass 4 indent level is 2 Address data transfer
[List of Patents for class 710 subclass 5]  5           Subclass 5 indent level is 1 Input/Output command process
[List of Patents for class 710 subclass 6]  6           Subclass 6 indent level is 2 Operation scheduling
[List of Patents for class 710 subclass 7]  7           Subclass 7 indent level is 2 Concurrently performing Input/Output operation and other operation unrelated to Input/Output
[List of Patents for class 710 subclass 8]  8           Subclass 8 indent level is 1 Peripheral configuration
[List of Patents for class 710 subclass 9]  9           Subclass 9 indent level is 2 Address assignment
[List of Patents for class 710 subclass 10]  10           Subclass 10 indent level is 2 Configuration initialization
[List of Patents for class 710 subclass 11]  11           Subclass 11 indent level is 2 Protocol selection
[List of Patents for class 710 subclass 12]  12           Subclass 12 indent level is 2 As input or output
[List of Patents for class 710 subclass 13]  13           Subclass 13 indent level is 2 By detachable memory
[List of Patents for class 710 subclass 14]  14           Subclass 14 indent level is 2 Mode selection
[List of Patents for class 710 subclass 15]  15           Subclass 15 indent level is 1 Peripheral monitoring
[List of Patents for class 710 subclass 16]  16           Subclass 16 indent level is 2 Characteristic discrimination
[List of Patents for class 710 subclass 17]  17           Subclass 17 indent level is 2 Availability monitoring
[List of Patents for class 710 subclass 18]  18           Subclass 18 indent level is 2 Activity monitoring
[List of Patents for class 710 subclass 19]  19           Subclass 19 indent level is 2 Status updating
[List of Patents for class 710 subclass 20]  20           Subclass 20 indent level is 1 Concurrent Input/Output processing and data transfer
[List of Patents for class 710 subclass 21]  21           Subclass 21 indent level is 2 Concurrent data transferring
[List of Patents for class 710 subclass 22]  22           Subclass 22 indent level is 1 Direct Memory Accessing (DMA)
[List of Patents for class 710 subclass 23]  23           Subclass 23 indent level is 2 Programmed control memory accessing
[List of Patents for class 710 subclass 24]  24           Subclass 24 indent level is 2 By command chaining
[List of Patents for class 710 subclass 25]  25           Subclass 25 indent level is 2 Timing
[List of Patents for class 710 subclass 26]  26           Subclass 26 indent level is 2 Using addressing
[List of Patents for class 710 subclass 27]  27           Subclass 27 indent level is 2 Via separate bus
[List of Patents for class 710 subclass 28]  28           Subclass 28 indent level is 2 With access regulating
[List of Patents for class 710 subclass 29]  29           Subclass 29 indent level is 1 Flow controlling
[List of Patents for class 710 subclass 30]  30           Subclass 30 indent level is 1 Frame forming
[List of Patents for class 710 subclass 31]  31           Subclass 31 indent level is 1 Transfer direction selection
[List of Patents for class 710 subclass 32]  32           Subclass 32 indent level is 1 Transfer termination
[List of Patents for class 710 subclass 33]  33           Subclass 33 indent level is 1 Data transfer specifying
[List of Patents for class 710 subclass 34]  34           Subclass 34 indent level is 2 Transferred data counting
[List of Patents for class 710 subclass 35]  35           Subclass 35 indent level is 2 Burst data transfer
[List of Patents for class 710 subclass 36]  36           Subclass 36 indent level is 1 Input/Output access regulation
[List of Patents for class 710 subclass 37]  37           Subclass 37 indent level is 2 Access dedication
[List of Patents for class 710 subclass 38]  38           Subclass 38 indent level is 2 Path selection
[List of Patents for class 710 subclass 39]  39           Subclass 39 indent level is 2 Access request queuing
[List of Patents for class 710 subclass 40]  40           Subclass 40 indent level is 2 Access prioritization
[List of Patents for class 710 subclass 41]  41           Subclass 41 indent level is 3 Dynamic
[List of Patents for class 710 subclass 42]  42           Subclass 42 indent level is 3 Group
[List of Patents for class 710 subclass 43]  43           Subclass 43 indent level is 3 Physical position
[List of Patents for class 710 subclass 44]  44           Subclass 44 indent level is 3 Prioritized polling
[List of Patents for class 710 subclass 45]  45           Subclass 45 indent level is 3 Time-slot accessing
[List of Patents for class 710 subclass 46]  46           Subclass 46 indent level is 2 Input/Output polling
[List of Patents for class 710 subclass 47]  47           Subclass 47 indent level is 3 Polled interrupt
[List of Patents for class 710 subclass 48]  48           Subclass 48 indent level is 2 Input/Output interrupting
[List of Patents for class 710 subclass 49]  49           Subclass 49 indent level is 3 Masking
[List of Patents for class 710 subclass 50]  50           Subclass 50 indent level is 3 Vectored
[List of Patents for class 710 subclass 51]  51           Subclass 51 indent level is 2 Accessing via a multiplexer
[List of Patents for class 710 subclass 52]  52           Subclass 52 indent level is 1 Input/Output data buffering
[List of Patents for class 710 subclass 53]  53           Subclass 53 indent level is 2 Alternately filling or emptying buffers
[List of Patents for class 710 subclass 54]  54           Subclass 54 indent level is 2 Queue content modification
[List of Patents for class 710 subclass 55]  55           Subclass 55 indent level is 2 Contents validation
[List of Patents for class 710 subclass 56]  56           Subclass 56 indent level is 2 Buffer space allocation or deallocation
[List of Patents for class 710 subclass 57]  57           Subclass 57 indent level is 2 Fullness indication
[List of Patents for class 710 subclass 58]  58           Subclass 58 indent level is 1 Input/Output process timing
[List of Patents for class 710 subclass 59]  59           Subclass 59 indent level is 2 Processing suspension
[List of Patents for class 710 subclass 60]  60           Subclass 60 indent level is 2 Transfer rate regulation
[List of Patents for class 710 subclass 61]  61           Subclass 61 indent level is 2 Synchronous data transfer
[List of Patents for class 710 subclass 62]  62           Subclass 62 indent level is 1 Peripheral adapting
[List of Patents for class 710 subclass 63]  63           Subclass 63 indent level is 2 Universal
[List of Patents for class 710 subclass 64]  64           Subclass 64 indent level is 2 Via common units and peripheral-specific units
[List of Patents for class 710 subclass 65]  65           Subclass 65 indent level is 2 Input/Output data modification
[List of Patents for class 710 subclass 66]  66           Subclass 66 indent level is 3 Width conversion
[List of Patents for class 710 subclass 67]  67           Subclass 67 indent level is 3 Keystroke interpretation
[List of Patents for class 710 subclass 68]  68           Subclass 68 indent level is 3 Data compression and expansion
[List of Patents for class 710 subclass 69]  69           Subclass 69 indent level is 3 Analog-to-digital or digital-to-analog
[List of Patents for class 710 subclass 70]  70           Subclass 70 indent level is 3 Digital-to-digital
[List of Patents for class 710 subclass 71]  71           Subclass 71 indent level is 3 Serial-to-parallel or parallel-to-serial
[List of Patents for class 710 subclass 72]  72           Subclass 72 indent level is 2 Application-specific peripheral adapting
[List of Patents for class 710 subclass 73]  73           Subclass 73 indent level is 3 For user input device
[List of Patents for class 710 subclass 74]  74           Subclass 74 indent level is 3 For data storage device
[List of Patents for class 710 subclass 100]  100           INTRASYSTEM CONNECTION (E.G., BUS AND BUS TRANSACTION PROCESSING)
[List of Patents for class 710 subclass 300]  300           Subclass 300 indent level is 1 Bus expansion or extension
[List of Patents for class 710 subclass 301]  301           Subclass 301 indent level is 2 Card insertion
[List of Patents for class 710 subclass 302]  302           Subclass 302 indent level is 3 Hot insertion
[List of Patents for class 710 subclass 303]  303           Subclass 303 indent level is 2 Docking station
[List of Patents for class 710 subclass 304]  304           Subclass 304 indent level is 3 Hot docking
[List of Patents for class 710 subclass 104]  104           Subclass 104 indent level is 1 System configuring
[List of Patents for class 710 subclass 105]  105           Subclass 105 indent level is 1 Protocol
[List of Patents for class 710 subclass 106]  106           Subclass 106 indent level is 2 Using transmitter and receiver
[List of Patents for class 710 subclass 107]  107           Subclass 107 indent level is 1 Bus access regulation
[List of Patents for class 710 subclass 108]  108           Subclass 108 indent level is 2 Bus locking
[List of Patents for class 710 subclass 109]  109           Subclass 109 indent level is 2 Bus polling
[List of Patents for class 710 subclass 110]  110           Subclass 110 indent level is 2 Bus master/slave controlling
[List of Patents for class 710 subclass 111]  111           Subclass 111 indent level is 2 Rotational prioritizing (i.e., round robin)
[List of Patents for class 710 subclass 112]  112           Subclass 112 indent level is 2 Bus request queuing
[List of Patents for class 710 subclass 113]  113           Subclass 113 indent level is 2 Centralized bus arbitration
[List of Patents for class 710 subclass 114]  114           Subclass 114 indent level is 3 Static bus prioritization
[List of Patents for class 710 subclass 115]  115           Subclass 115 indent level is 4 Physical position bus prioritization
[List of Patents for class 710 subclass 116]  116           Subclass 116 indent level is 3 Dynamic bus prioritization
[List of Patents for class 710 subclass 117]  117           Subclass 117 indent level is 3 Time-slotted bus accessing
[List of Patents for class 710 subclass 118]  118           Subclass 118 indent level is 3 Delay reduction
[List of Patents for class 710 subclass 119]  119           Subclass 119 indent level is 2 Decentralized bus arbitration
[List of Patents for class 710 subclass 120]  120           Subclass 120 indent level is 3 Hierarchical or multilevel accessing
[List of Patents for class 710 subclass 121]  121           Subclass 121 indent level is 3 Static bus prioritization
[List of Patents for class 710 subclass 122]  122           Subclass 122 indent level is 4 Physical position bus prioritization
[List of Patents for class 710 subclass 123]  123           Subclass 123 indent level is 3 Dynamic bus prioritization
[List of Patents for class 710 subclass 124]  124           Subclass 124 indent level is 3 Time-slotted bus accessing
[List of Patents for class 710 subclass 125]  125           Subclass 125 indent level is 3 Delay reduction
[List of Patents for class 710 subclass 305]  305           Subclass 305 indent level is 1 Bus interface architecture
[List of Patents for class 710 subclass 306]  306           Subclass 306 indent level is 2 Bus bridge
[List of Patents for class 710 subclass 307]  307           Subclass 307 indent level is 3 Variable or multiple bus width
[List of Patents for class 710 subclass 308]  308           Subclass 308 indent level is 3 Direct memory access (e.g., DMA)
[List of Patents for class 710 subclass 309]  309           Subclass 309 indent level is 3 Arbitration
[List of Patents for class 710 subclass 310]  310           Subclass 310 indent level is 3 Buffer or que control
[List of Patents for class 710 subclass 311]  311           Subclass 311 indent level is 3 Intelligent bridge
[List of Patents for class 710 subclass 312]  312           Subclass 312 indent level is 3 Multiple bridges
[List of Patents for class 710 subclass 313]  313           Subclass 313 indent level is 3 Peripheral bus coupling (e.g., PCI, USB, ISA, and etc.)
[List of Patents for class 710 subclass 314]  314           Subclass 314 indent level is 3 Common protocol (e.g., PCI to PCI)
[List of Patents for class 710 subclass 315]  315           Subclass 315 indent level is 3 Different protocol (e.g., PCI to ISA)
[List of Patents for class 710 subclass 316]  316           Subclass 316 indent level is 2 Path selecting switch
[List of Patents for class 710 subclass 317]  317           Subclass 317 indent level is 3 Crossbar
[List of Patents for class 710 subclass 200]  200           ACCESS LOCKING
[List of Patents for class 710 subclass 220]  220           ACCESS POLLING
[List of Patents for class 710 subclass 240]  240           ACCESS ARBITRATING
[List of Patents for class 710 subclass 241]  241           Subclass 241 indent level is 1 Centralized arbitrating
[List of Patents for class 710 subclass 242]  242           Subclass 242 indent level is 1 Decentralized arbitrating
[List of Patents for class 710 subclass 243]  243           Subclass 243 indent level is 1 Hierarchical or multilevel arbitrating
[List of Patents for class 710 subclass 244]  244           Subclass 244 indent level is 1 Access prioritizing
[List of Patents for class 710 subclass 260]  260           INTERRUPT PROCESSING
[List of Patents for class 710 subclass 261]  261           Subclass 261 indent level is 1 Multimode interrupt processing
[List of Patents for class 710 subclass 262]  262           Subclass 262 indent level is 1 Interrupt inhibiting or masking
[List of Patents for class 710 subclass 263]  263           Subclass 263 indent level is 1 Interrupt queuing
[List of Patents for class 710 subclass 264]  264           Subclass 264 indent level is 1 Interrupt prioritizing
[List of Patents for class 710 subclass 265]  265           Subclass 265 indent level is 2 Variable
[List of Patents for class 710 subclass 266]  266           Subclass 266 indent level is 1 Programmable interrupt processing
[List of Patents for class 710 subclass 267]  267           Subclass 267 indent level is 1 Processor status
[List of Patents for class 710 subclass 268]  268           Subclass 268 indent level is 1 Source or destination identifier
[List of Patents for class 710 subclass 269]  269           Subclass 269 indent level is 1 Handling vector
 
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